US5593494A - Precision controlled precipitation of oxygen in silicon - Google Patents

Precision controlled precipitation of oxygen in silicon Download PDF

Info

Publication number
US5593494A
US5593494A US08/403,301 US40330195A US5593494A US 5593494 A US5593494 A US 5593494A US 40330195 A US40330195 A US 40330195A US 5593494 A US5593494 A US 5593494A
Authority
US
United States
Prior art keywords
wafers
oxygen
temperature
single crystal
crystal silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/403,301
Other languages
English (en)
Inventor
Robert Falster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GEA Till GmbH and Co
SunEdison Semiconductor Ltd
Original Assignee
SunEdison Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/403,301 priority Critical patent/US5593494A/en
Application filed by SunEdison Inc filed Critical SunEdison Inc
Assigned to MEMC ELECTRONIC MATERIALS, INC. reassignment MEMC ELECTRONIC MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FALSTER, ROBERT
Assigned to GEA TILL GMBH & CO. reassignment GEA TILL GMBH & CO. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TILL, VOLKER
Priority to TW084111819A priority patent/TW344850B/zh
Priority to DE69630328T priority patent/DE69630328T2/de
Priority to EP96301616A priority patent/EP0732431B1/en
Priority to JP8056054A priority patent/JPH08253392A/ja
Priority to KR1019960006755A priority patent/KR960035771A/ko
Priority to MYPI96000915A priority patent/MY115003A/en
Priority to CN96100507A priority patent/CN1061705C/zh
Priority to SG1996006358A priority patent/SG43246A1/en
Publication of US5593494A publication Critical patent/US5593494A/en
Application granted granted Critical
Assigned to MEMC ELECTRONIC MATERIALS, INC. reassignment MEMC ELECTRONIC MATERIALS, INC. TERMINATION OF SECURITY INTEREST Assignors: E.ON AG
Assigned to CITICORP USA, INC. reassignment CITICORP USA, INC. SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEMC ELECTRONIC MATERIALS, INC., MEMC INTERNATIONAL, INC., MEMC PASADENA, INC., MEMC SOUTHWEST INC., PLASMASIL, L.L.C., SIBOND, L.L.C.
Assigned to CITICORP USA, INC. reassignment CITICORP USA, INC. SECURITY AGREEMENT Assignors: MEMC ELECTRONIC MATERIALS, INC., MEMC INTERNATIONAL, INC., MEMC PASADENA, INC., MEMC SOUTHWEST INC., PLASMASIL, L.L.C., SIBOND, L.L.C.
Assigned to E. ON AG reassignment E. ON AG SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEMC ELECTRONIC MATERIALS, INC.
Assigned to CITICORP USA, INC. reassignment CITICORP USA, INC. SECURITY AGREEMENT Assignors: MEMC ELECTRONIC MATERIALS, INC., MEMC HOLDINGS CORPORATION, MEMC INTERNATIONAL, INC., MEMC PASADENA, INC., MEMC SOUTHWEST INC., PLASMASIL, L.L.C., SIBOND, L.L.C.
Assigned to CITICORP USA, INC. reassignment CITICORP USA, INC. SECURITY AGREEMENT Assignors: MEMC HOLDINGS CORPORATION, MEMC INTERNATIONAL, INC., MEMC SOUTHWEST INC., SIBOND, L.L.C., MEMC ELECTRONIC MATERIALS, INC., MEMC PASADENA, INC., PLASMASIL, L.L.C.
Assigned to MEMC ELECTRONIC MATERIALS, INC. reassignment MEMC ELECTRONIC MATERIALS, INC. RELEASE OF SECURITY INTEREST Assignors: CITICORP USA, INC.
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. SECURITY AGREEMENT Assignors: MEMC ELECTRONIC MATERIALS, INC., SOLAICX, SUNEDISON LLC
Assigned to GOLDMAN SACHS BANK USA reassignment GOLDMAN SACHS BANK USA SECURITY AGREEMENT Assignors: MEMC ELECTRONIC MATERIALS, INC., NVT, LLC, SOLAICX, INC., SUN EDISON LLC
Assigned to SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.), SUN EDISON LLC, NVT, LLC, SOLAICX reassignment SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.) RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: GOLDMAN SACHS BANK USA
Assigned to SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.), ENFLEX CORPORATION, SUN EDISON LLC, SOLAICX reassignment SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.) RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: BANK OF AMERICA, N.A.
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH reassignment DEUTSCHE BANK AG NEW YORK BRANCH SECURITY AGREEMENT Assignors: NVT, LLC, SOLAICX, SUN EDISON, LLC, SUNEDISON, INC.
Assigned to SUNEDISON, INC., SUN EDISON LLC, NVT, LLC, SOLAICX reassignment SUNEDISON, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: DEUTSCHE BANK AG NEW YORK BRANCH
Assigned to SIBOND, L.L.C., PLASMASIL, L.L.C., MEMC SOUTHWEST INC., MEMC ELECTRONIC MATERIALS, INC. (NOW KNOWN AS SUNEDISON, INC.), MEMC INTERNATIONAL, INC. (NOW KNOWN AS SUNEDISON INTERNATIONAL, INC.), MEMC PASADENA, INC. reassignment SIBOND, L.L.C. RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161 Assignors: CITICORP USA, INC.
Assigned to SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H) reassignment SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEMC ELECTRONIC MATERIALS, INC.
Assigned to SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD. reassignment SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD. NOTICE OF LICENSE AGREEMENT Assignors: SUNEDISON SEMICONDUCTOR LIMITED
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Definitions

  • the present invention relates generally to the fabrication of single crystal silicon substrates, and more particularly, to a process for fabricating single crystal silicon wafers having oxygen precipitate nucleation centers which can be stabilized and serve as a site for the growth of oxygen precipitates with the number of oxygen precipitates having a low order of dependance upon the oxygen concentration of the single crystal silicon.
  • Single crystal silicon which is the starting material for most processes for the fabrication of semiconductor electronic components, is commonly prepared with the so-called Czochralski (“Cz") process wherein a single seed crystal is immersed into molten silicon and then grown by slow extraction.
  • Cz Czochralski
  • oxygen comes into the crystal lattice from the quartz crucible in which it is held until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in solidified silicon.
  • concentrations are greater than the solubility of oxygen in solid silicon at the temperatures typical for the processes for the fabrication of integrated circuits.
  • the solubility of oxygen in it decreases rapidly, whereby in the resulting slices or wafers, oxygen is present in supersaturated concentrations.
  • Thermal treatment cycles which are typically employed in the fabrication of electronic devices can cause the precipitation of oxygen in silicon wafers which are supersaturated in oxygen. Depending upon their location in the wafer, the precipitates can be harmful or beneficial. Oxygen precipitates located in the active device region of the wafer can impair the operation of the device. Oxygen precipitates located in the bulk of the wafer, however, are capable of trapping undesired metal impurities that may come into contact with the wafer. The use of oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to internal or intrinsic gettering ("IG").
  • IG internal or intrinsic gettering
  • the electronic device fabrication process inherently includes a series of steps which, in principle, can be used to form a zone near the surface of the wafer which is free of oxygen precipitates (commonly referred to as a "denuded zone” or a “precipitate free zone”) with the balance of the wafer containing a sufficient number of oxygen precipitates for IG purposes.
  • Denuded zones can be formed, for example, in a high-low-high thermal sequence such as (a) oxygen outdiffusion heat treatment at a high temperature (>1100° C.) in an inert ambient for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600°-750° C.), and (c) growth of oxygen (SiO 2 ) precipitates at a high temperature (1000°-1150° C.).
  • a high-low-high thermal sequence such as (a) oxygen outdiffusion heat treatment at a high temperature (>1100° C.) in an inert ambient for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600°-750° C.), and (c) growth of oxygen (SiO 2 ) precipitates at a high temperature (1000°-1150° C.).
  • a critical requirement for many electronic device fabricators is that all wafers subjected to their thermal sequence have a uniform and reproducible denuded zone and a uniform and reproducible number density of oxygen precipitates outside the denuded zone. Uniformity and reproducibility have been difficult to achieve at a reasonable cost, however.
  • Bischoff et al. suggest a process for forming wafers having a wide denuded zone ( ⁇ 15 ⁇ m) with a high precipitate density (>10 12 /cm 3 ) in U.S. Pat. No. 4,437,922.
  • the denuded zone is formed first by annealing the wafers at 1100° C. for four hours.
  • Bischoff et al. suggest that the wafers be annealed at temperature in the range of 400° to 500° C. to nucleate a high density of very small precipitates and grow them to such a size to permit survival of a subsequent heat treatment such as 925° C. Thereafter, Bischoff et al.
  • Bischoff et al. A significant disadvantage of the Bischoff et al. process is its failure to take advantage of the high temperature steps which are routinely used in electronic device fabrication. These steps could be used to form the denuded zone and to stabilize the oxygen precipitates in the balance of the wafer, provided the precipitation behavior were tailored for the specific electronic device fabrication process. The additional steps required by Bischoff et al. add significant labor and cost to the wafers. Furthermore, nowhere do Bischoff et al. disclose any means for controlling the number density of the oxygen precipitates; Bischoff et al. merely disclosed how to consistently obtain a high density (>10 12 /cm 3 ) which may not be appropriate for many applications.
  • the present invention is directed to a process for controlling the density of oxygen precipitate nucleation centers in single crystal silicon.
  • the process comprises annealing the single crystal silicon at temperatures of at least about 350° C.
  • the annealing comprises (i) heat-treating the single crystal silicon at a temperature, T 1 , between about 350° C. and about 500° C. to form oxygen precipitate nucleation centers in the single crystal silicon and (ii) increasing the temperature of the single crystal silicon from T 1 to a second temperature, T 2 , between about 500° C. and about 750° C.
  • the rate of temperature increase from T 1 to T 2 is controlled such that the single crystal silicon, upon achieving T 2 , contains oxygen precipitate nucleation clusters formed at T 1 .
  • the annealing is terminated at a point in time when the oxygen precipitate nucleation centers are capable of being dissolved by heat-treating the silicon at temperatures not in excess of about 1150° C.
  • the present invention is also directed to a process for controlling the concentration of oxygen precipitate nucleation centers in single crystal silicon in which the silicon is heat-treated to dissolve the oxygen precipitate nucleation centers which were formed in the silicon during the growth of the single crystal.
  • the heat-treated single crystal silicon is then annealed at a temperature of at least about 350° C. to cause oxygen precipitate nucleation centers to be formed and then increased in size in the single crystal silicon with the annealing comprising (i) causing the single crystal silicon to achieve a first temperature, T 1 , which is between about 350° C. and about 500° C., and (ii) increasing the temperature of the single crystal silicon from T 1 to a second temperature, T 2 , which is between about 500° C. and about 750° C.
  • the average rate of temperature increase from T 1 to T 2 is controlled such that at an intermediate temperature, T int , between T 1 and T 2 , the single crystal silicon contains a population of oxygen precipitate nucleation clusters at least some of which were present a temperature which is less than T int but greater than T 1 and which have increased in size through the addition of oxygen atoms when the temperature was increased to T int .
  • the present invention is further directed to a process for controlling the concentration of oxygen precipitate nucleation centers in a set of at least 25 single crystal silicon wafers.
  • Each of the wafers in the set has a carbon concentration of less than 5 ⁇ 10 16 atoms/cm 3 .
  • the wafers also have a concentration of oxygen falling within a range of oxygen concentrations for the set with the difference between the maximum and the minimum concentration in the range of oxygen concentrations for the wafers in the set being at least 5 ⁇ 10 16 atoms/cm 3 .
  • the process comprises the steps of (a) heating (or cooling) the single crystal silicon to achieve a first temperature, T 1 , which is between about 350° C. and about 500° C.
  • the temperature is then increased from T 1 to a second temperature, T 2 , which is between about 500° C. and about 750° C. at an average rate of less than 25° C. per minute.
  • T 2 a second temperature
  • the increase in temperature from T 1 to T 2 is controlled such that the wafers in the set will contain oxygen precipitates upon being subjected to an oxygen precipitation heat treatment with the ratio of the maximum density to the minimum density of oxygen precipitates for the wafers in the set being no more than about 30.
  • the present invention is further directed to a set of at least twenty-five single crystal silicon wafers each of which contains a substantially uniform oxygen concentration at distances greater than 3 microns from the surface of the wafers.
  • the difference between the maximum and the minimum concentration of oxygen concentration for the wafers in the set is at least 5 ⁇ 10 16 atoms/cm 3 .
  • the wafers additionally contain oxygen precipitate nucleation centers in a density such that upon being subjected to an oxygen precipitation heat treatment, each of the wafers in the set will have a density of oxygen precipitates with the ratio of the maximum density to the minimum density of oxygen precipitates for the wafers in the set being no more than about 30.
  • FIG. 1 is a graph of the log of the oxygen precipitate density (“OPD")/cm 3 versus the initial oxygen concentration (atoms/cm 3 ) for two sets of wafers subject to a series of heat treatments as set forth in Example 1.
  • OPD oxygen precipitate density
  • FIG. 2 is a graph of the log of the oxygen precipitate density ("OPD")/cm 3 versus the the log of the initial oxygen concentration (atoms/cm 3 ) for two sets of wafers, one subjected to an isothermal anneal and the other subjected to a ramp anneal as set forth in Example 1.
  • OPD oxygen precipitate density
  • FIG. 3 is a graph of the change in oxygen concentration (“Delta Oxygen”)/cm 3 versus the the log of the initial oxygen concentration (atoms/cm 3 ) for a set of wafers subjected to a ramp anneal and a curve showing what the relationship would have been if the wafers had been isothermally annealed instead, as set forth in Example 2.
  • FIG. 4 is a graph which presents FIG. 3 and the data generated in Example 2 in a different form as described in Example 3.
  • the target precipitate density may fall anywhere within the range of about 10 7 to about 10 11 precipitates/cm 3 and the oxygen concentration of the silicon in which this target is achieved may fall anywhere within the range of about 6 ⁇ 10 17 to about 8.5 ⁇ 10 17 atoms/cm 3 (ASTM standard F-121-83), i.e., the range of oxygen concentration which is typical of Cz grown silicon.
  • the process of the present invention is designed to utilize the high temperature steps which are routinely used in electronic device fabrication.
  • Single crystal silicon which has been prepared by the process of the present invention contains oxygen precipitate nucleation centers which have a low order of dependence upon oxygen concentration.
  • the oxygen precipitate nucleation centers will dissolve in a region near the surface of the silicon to form a denuded zone whereas the oxygen precipitate nucleation centers in the bulk of the silicon will be stabilized and grown into oxygen precipitates, the number density of which is within a narrow range about a target density.
  • a single crystal silicon starting material is subjected to an annealing treatment which is referred to herein as ramped annealing.
  • the single crystal silicon is heated to a first temperature, T 1 , and the temperature of the silicon is then increased to a second temperature, T 2 , with the rate of temperature increase between T 1 and T 2 being controlled to maintain and grow oxygen precipitate nucleation centers which have been formed in the single crystal silicon during this process.
  • the first temperature, T 1 is between about 350° C. and about 500° C., preferably between about 375° C. and about 475° C., and most preferably, between about 400° C. and about 450° C.
  • the second temperature, T 2 is between about 500° C. and about 750° C., preferably between about 575° C. and about 725° C., more preferably, between about 600° C. and about 700° C., and most preferably, between about 600° C. and about 650° C.
  • the average rate at which the temperature of the silicon is increased between T 1 and T 2 will vary depending upon the oxygen concentration of the silicon, but typically will be between about 0.2° and about 25° C. per minute. In general, the rate of temperature increase decreases with decreasing oxygen concentration and thus, the average rate of temperature increase may be less than 10° C. per minute, 5° C. per minute, or even less than 1° C. per minute for silicon having less than about 7.2 ⁇ 10 17 oxygen atoms/cm 3 (as determined in accordance with ASTM Standard F-121-83).
  • the manner in which temperature is increased as a function of time may be optimized for any given process; that is, it may be increased linearly or in steps as a function of time and at varying rates between the temperatures which are intermediate of T 1 and T 2 .
  • the starting material for the process is single crystal silicon having a sufficient concentration of oxygen to enable its precipitation when subjected to an oxygen precipitation heat treatment.
  • Czochralski grown silicon typically has an oxygen concentration of about 6 ⁇ 10 17 to about 8.5 ⁇ 10 17 atoms/cm 3 (ASTM standard F-121-83) which is sufficient for the precipitation of oxygen.
  • Oxygen can be precipitated from silicon, for example, by subjecting the silicon to a heat treatment which comprises annealing the silicon at a temperature in the range of about 650° C. to about 875° C., preferably between about 800° C. and 875° C. to stabilize oxygen precipitate nucleation centers present in the silicon and annealing the silicon at a temperature of at least about 1000° C. to precipitate oxygen at the site of the stabilized nucleation centers.
  • the amount of time required to stabilize the nucleation centers is dependant upon the heat-treating temperature and, in general, less time is required to stabilize the nucleation centers as temperature is increased. For example, at least about six hours at a temperature of about 650° C.
  • a preferred heat treatment for precipitating oxygen comprises heating the wafers to 800° C. for four hours and then to 1000° C. for sixteen hours.
  • the single crystal silicon starting material should also have a low density of, and preferably, an essential absence of oxygen precipitate nucleation centers.
  • the presence (or density) of these nucleation centers cannot be directly measure using presently available techniques.
  • preexisting oxygen precipitate nucleation centers in the silicon can be stabilized and precipitates can be grown at these sites by subjecting the silicon to an oxygen precipitation heat treatment.
  • the detection limit for oxygen precipitates is currently about 10 7 precipitates/cm 3 .
  • silicon having a low density of oxygen precipitate nucleation centers shall mean silicon which, upon being annealed at a temperature of 800° C.
  • silicon having an essential absence of oxygen precipitate nucleation centers shall mean silicon which, upon being annealed at a temperature of 800° C. for four hours and then at a temperature of 1000° C. for sixteen hours, has less than 10 7 oxygen precipitates/cm 3 .
  • the silicon has less than 5 ⁇ 10 7 oxygen precipitates/cm 3 , and more preferably the silicon has less than 10 7 oxygen precipitates/cm 3 .
  • Oxygen precipitate nucleation centers typically form in silicon which is annealed at a temperature in the range of about 350° to about 750° C.
  • the single crystal silicon starting material therefore, may be silicon taken from "short" crystals, that is, silicon which has been grown in a Czochralski process until the seed end has cooled from the melting point of silicon (1410° C.) to about 750° C. after which the ingot is rapidly cooled. In this way, the time spent in the temperature range critical for nucleation center formation is kept to a minimum and the nucleation centers have inadequate time to form in the crystal puller.
  • the single crystal starting material is annealed to dissolve the oxygen precipitate nucleation centers which were formed during the growth of the single crystal.
  • oxygen precipitate nucleation centers can be annealed out of silicon by rapidly heating the silicon to a temperature of at least about 875° C. and preferably continuing to increase the temperature to at least 1000° C. By the time the silicon reaches 1000° C., substantially all (e.g., >99%) of such defects have annealed out. It is important that the wafers be rapidly heated to these temperatures, i.e., that the rate of temperature increase be at least about 10° C. per minute and more preferably at least about 50° C. per minute.
  • oxygen precipitate nucleation centers in the single crystal silicon starting material may be dissolved by annealing the silicon at a temperature of at least about 875° C. for a period of at least about 30 seconds, preferably at least about 10 minutes.
  • the dissolution may be carried out in a conventional furnace or in a rapid thermal annealing (RTA) system.
  • RTA rapid thermal annealing
  • the dissolution may carried out on crystal ingots or on wafers.
  • Substitutional carbon when present as an impurity in single crystal silicon has the ability to catalyze the formation of oxygen precipitate nucleation centers.
  • the single crystal silicon starting material have a low concentration of carbon. That is, the single crystal silicon should have a concentration of carbon which is less than about 5 ⁇ 10 16 atoms/cm 3 , preferably which is less than 1 ⁇ 10 16 atoms/cm 3 , and more preferably less than 5 ⁇ 10 15 atoms/cm 3 .
  • the single crystal silicon should also preferably have a substantially uniform oxygen concentration as a function of depth from the silicon surface. Unlike prior methods used to control the precipitation of oxygen in silicon, it is unnecessary to subject the single crystal silicon to a high temperature step to cause the outdiffusion of oxygen in regions near the surface of the silicon prior to the ramped annealing steps of the present invention. Such high temperature steps when carried out for the sole purpose of forming a denuded zone add significant cost to the silicon wafer.
  • the single crystal silicon starting material for the ramped annealing sequence of steps have a uniform concentration of oxygen from the center of the silicon to regions of the wafer which are within 15 microns of the silicon surface, more preferably from the center of the silicon to regions of the wafer which are within 10 microns of the silicon surface, even more preferably from the center of the silicon to regions of the wafer which are within 5 microns of the silicon surface and most preferably from the center of the silicon to regions of the wafer which are within 3 microns of the silicon surface.
  • substantially uniform oxygen concentration shall mean a variance in the oxygen concentration of no more than about 50%, preferably no more than about 20% and most preferably no more than about 10%.
  • substantially uniform density of oxygen precipitate nucleation centers shall mean a variance in the number density of no more than a factor of 10, preferably no more than a factor of 5 and most preferably no more than a factor of 2.
  • the ramped annealing process of the present invention is distinguishable from conventional isothermal annealing processes.
  • a conventional isothermal annealing process the single crystal silicon is heated to a target temperature within the range of about 500° C. to about 650° C., annealed at that target temperature for a period of about fifteen minutes to several hours or more, and then cooled. During the annealing period, oxygen precipitate nucleation centers are formed.
  • a plot of the precipitate density versus initial oxygen concentration for a set of wafers which have been isothermally annealed will generally show an approximate dependence of [O i ] n where n is between about 25 and 30, provided the wafers have an essential absence of oxygen precipitate nucleation centers prior to the isothermal anneal.
  • the oxygen precipitate dependencies upon oxygen concentration of single crystal silicon can be significantly reduced. That is, the exponent "n" can be reduced to less than 25, preferably less than 20, more preferably less than 15 and optimally less than 10.
  • the ramped annealing process of the present invention begins with a relatively low first temperature, T 1 , designed to create only very small clusters, that is, clusters which form with a relatively weak oxygen concentration dependence.
  • the rate of temperature increase from T 1 to T 2 is controlled such that at an intermediate temperature, T int , between T 1 and T 2 , the single crystal silicon contains a population of oxygen precipitate nucleation clusters at least some of which, preferably the majority of which, were present at a temperature which is less than T int but greater than T 1 and which increased in size through the addition of oxygen atoms when the temperature was increased to T int (the balance of the population of oxygen precipitate nucleation centers which are present at T int being spontaneously formed at each T int ).
  • the result of ramped annealing is a population of larger clusters which exist at each intermediate temperature, T int , and ultimately at the second temperature, T 2 , whose density dependence on oxygen concentration is greatly reduced as compared to isothermal annealing.
  • these clusters are not of such a great size that their survival in subsequent device processing is insured; they can be dissolved by subsequent thermal processing.
  • wafers subjected to ramped annealing and thereafter to the high-low-high thermal process steps which typically occur in the fabrication of an electronic device will naturally and desirably form a denuded zone near the surface of the wafer and a target density of oxygen precipitates outside the denuded zone.
  • the range of precipitation densities for a given oxygen content is readily adjustable with a wide variety of parameters which allow for the setting of both an average target value and the slope of the oxygen concentration dependence. These parameters are:
  • the first temperature, T 1 is maintained for a period of one hour or less whereas the second temperature, T 2 , is maintained for a period which is determined by the magnitude of the second temperature.
  • T 2 is between about 600° C. and 650° C.
  • T 2 will typically be maintained for no more than four hours, preferably for no more than about two hours and more preferably for no more than about one hour.
  • T 2 is between about 650° C. and 700° C.
  • T 2 will typically be maintained for no more than two hours, preferably for no more than about one hour and more preferably for no more than about one-half hour.
  • T 2 is between about 700° C. and 750° C., T 2 will typically be maintained for no more than one hour, preferably for no more than about one-half hour and more preferably for no more than about one-quarter hour.
  • the average ramp rate between T 1 and T 2 will be between about 0.2° C. and 25° C. per minute.
  • the ramp between any two temperatures in the temperature range of T 1 to T 2 should be controlled to maintain and grow oxygen precipitate nucleation centers which existed at a lesser temperature.
  • the silicon After the single crystal silicon is subjected to ramped annealing, it is important that the silicon not be subjected to a heat-treatment which stabilizes oxygen precipitation nucleation centers prior to a heat-treatment which causes the formation of a denuded zone. Otherwise, the oxygen clusters (oxygen precipitate nucleation centers) which were nucleated and grown during the ramped annealing step would be stabilized substantially throughout the entire thickness of the silicon and effectively prevent the formation of a denuded zone during a subsequent electronic device fabrication process.
  • oxygen precipitate nucleation centers formed in single crystal silicon by ramped annealing in accordance with the present invention are capable of being dissolved.
  • the nucleation centers in the region near the surface of the wafer can be dissolved to form a denuded zone during a thermal processing step which is a natural and inherent part of an electronic device fabrication process.
  • the oxygen precipitate centers can be stabilized and serve as the site for the growth of oxygen precipitates in later processing steps with the number density of the precipitates outside the denuded zone being within a relatively narrow range about a target value.
  • the number density of the precipitates outside the denuded zone for a set of wafers can be controlled to have a low order of dependence upon oxygen concentration.
  • sets of wafers sliced from one or more crystal ingots grown by the Czochralski technique can be prepared which have a relatively narrow range of distribution about a target oxygen precipitate number density without resort to sorting based upon oxygen concentration or thermal history, or by requiring that the silicon contain unacceptably high carbon concentrations.
  • a set of wafers sliced from single crystal silicon grown by the Czochralski technique and subjected to ramped annealing and then to an oxygen precipitate stabilization and growth heat treatment can have an oxygen precipitate density within a narrow range about a target density which may be anywhere between about 10 7 to about 10 11 precipitates/cm 3 .
  • OPD T target precipitate density for the value of O i T .
  • OPD T + ⁇ OPD + maximum oxygen precipitate density in population
  • OPD T - ⁇ OPD - minimum oxygen precipitate density in population
  • O i T any value which can be achieved with Czochralski grown silicon and ⁇ O i is between about 0.5 ppma and 2 ppma
  • O i T is any value which can be achieved with Czochralski grown silicon and ⁇ O i is between about 0.5 ppma and 2 ppma
  • O i T is any value which can be achieved with Czochralski grown silicon and ⁇ O i is between about 0.5 ppma and 2 ppma
  • O i T is any value which can be achieved with Czochralski grown silicon and ⁇ O i is between about 0.5 ppma and 2 ppma
  • ⁇ O i is between about 0.5 ppma and 2 ppma
  • Tables I-III are calculated values for the predicted maximum to minimum precipitate values in a population of wafers (hereinafter the "OPD max/min ratio") for selected orders of dependence upon oxygen concentration, target oxygen concentration, and ranges of oxygen concentration about the specified target, for the wafers in the population.
  • the target oxygen concentration and range of oxygen concentrations is expressed in ppma with 1 ppma being equivalent to 5 ⁇ 10 16 atoms/cm 3 .
  • sets of wafers having an oxygen concentration of 12 ⁇ 1 ppma, 13 ⁇ 1 ppma, 14 ⁇ 1 ppma, 15 ⁇ 1 ppma, 16 ⁇ 1 ppma, or 17 ⁇ 1 ppma may be prepared with the ratio of the maximum to minimum oxygen precipitate density for the wafers in the set being less than 50, 40, 30, 20, 15, 10 or even 5.
  • sets of wafers having an oxygen concentration of 12 ⁇ 1.5 ppma, 13 ⁇ 1.5 ppma, 14 ⁇ 1.5 ppma, 15 ⁇ 1.5 ppma, 16 ⁇ 1.5 ppma, or 17 ⁇ 1.5 ppma may be prepared with the ratio of the maximum to minimum oxygen precipitate density for the wafers in the set being less than 100, 50, 40, 30, 20, 15, 10 or even 5.
  • sets of wafers having an oxygen concentration of 12 ⁇ 2 ppma, 13 ⁇ 2 ppma, 14 ⁇ 2 ppma, 15 ⁇ 2 ppma, 16 ⁇ 2 ppma, or 17 ⁇ 2 ppma may be prepared with the ratio of the maximum to minimum oxygen precipitate density for the wafers in the set being less than 200, 150, 100, 50, 40, 30, 25, 15, 10 or even 5.
  • These sets of wafers may be contained, for example, in wafer cassettes of the type in which wafers are typically stored and shipped, in boats of the type which are typically used for heat-treating silicon wafers, or in an equivalent wafer carrier.
  • the improvement of the ramped annealing treatment on the isothermal treatment is remarkable.
  • the oxygen precipitate density ("OPD") of the isothermally annealed group shows an approximate 32th power dependence on initial oxygen concentration (“O i ”) whereas the ramp annealed material shows only a 13th power dependence.
  • An effect of this reduction is, for example, that a variation in precipitation within a ⁇ 1 ppma oxygen concentration is reduced from about two orders of magnitude to about a factor of 2, i.e., an improvement by a factor of 50.
  • Example 2 The procedures of Example 1 were repeated except that three sets of wafers were sliced from three different crystals (45DSE, XE8999, and XEH001) and two sets of wafers were sliced from different portions of a fourth crystal (22FWJ, and 22FWA) and none of the wafers were subjected to an isothermal anneal.
  • the change in oxygen concentration (“delta oxygen”) as a result of this anneal as a function of the initial oxygen concentration is presented in FIG. 3.
  • FIG. 3 Also presented in FIG. 3 is a generally smooth, S-shaped curve which depicts what the change in oxygen concentration would be as a function of the initial oxygen concentration if the wafers had been isothermally annealed, the curve being based upon considerable prior experimental data. The improvement of ramped annealing over isothermal annealing is evident from this data.
  • FIG. 4 Another way of illustrating the advantages of the invention using the data generated in Example 2 appears in FIG. 4.
  • such a specification could only be met in standard isothermal annealed material by using a first oxygen specification of ⁇ 0.3 ppma, which is practically infeasible with conventional crystal pulling technology.
  • the same tight oxygen precipitation specification could be met with a first oxygen specification of ⁇ 1 ppma which is routinely achieved using conventional crystal pulling technology.
  • the first oxygen concentration specification could even be widened beyond ⁇ 1 ppma and still achieve significantly better performance than the standard production methods currently used today.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
US08/403,301 1995-03-14 1995-03-14 Precision controlled precipitation of oxygen in silicon Expired - Lifetime US5593494A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US08/403,301 US5593494A (en) 1995-03-14 1995-03-14 Precision controlled precipitation of oxygen in silicon
TW084111819A TW344850B (en) 1995-03-14 1995-11-08 Precision controlled precipitation of oxygen in silicon
DE69630328T DE69630328T2 (de) 1995-03-14 1996-03-08 Präziser kontrollierter Niederschlag von Sauerstoff in Silizium
EP96301616A EP0732431B1 (en) 1995-03-14 1996-03-08 Precision controlled precipitation of oxygen in silicon
JP8056054A JPH08253392A (ja) 1995-03-14 1996-03-13 シリコン中の酸素の精密制御析出
KR1019960006755A KR960035771A (ko) 1995-03-14 1996-03-13 단결정 실리콘내의 산소 침착 생성핵 중심 농도 제어 방법 및 그 방법에 의해 제조된 단결정 실리콘 웨이퍼들로 이루어진 웨이퍼 세트
MYPI96000915A MY115003A (en) 1995-03-14 1996-03-13 Precision controlled precipitation of oxygen in silicon
CN96100507A CN1061705C (zh) 1995-03-14 1996-03-13 精密控制硅中氧的沉淀
SG1996006358A SG43246A1 (en) 1995-03-14 1996-03-13 Precision controlled precipitation of oxygen in silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/403,301 US5593494A (en) 1995-03-14 1995-03-14 Precision controlled precipitation of oxygen in silicon

Publications (1)

Publication Number Publication Date
US5593494A true US5593494A (en) 1997-01-14

Family

ID=23595295

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/403,301 Expired - Lifetime US5593494A (en) 1995-03-14 1995-03-14 Precision controlled precipitation of oxygen in silicon

Country Status (9)

Country Link
US (1) US5593494A (zh)
EP (1) EP0732431B1 (zh)
JP (1) JPH08253392A (zh)
KR (1) KR960035771A (zh)
CN (1) CN1061705C (zh)
DE (1) DE69630328T2 (zh)
MY (1) MY115003A (zh)
SG (1) SG43246A1 (zh)
TW (1) TW344850B (zh)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US5904768A (en) * 1996-10-15 1999-05-18 Memc Electronic Materials, Inc. Process for controlling the oxygen content in silicon wafers heavily doped with antimony or arsenic
US6180220B1 (en) * 1997-02-26 2001-01-30 Memc Electronic Materials, Inc. Ideal Oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6191010B1 (en) 1998-09-02 2001-02-20 Memc Electronic Materials, Inc. Process for preparing an ideal oxygen precipitating silicon wafer
US6190631B1 (en) * 1997-04-09 2001-02-20 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US6236104B1 (en) 1998-09-02 2001-05-22 Memc Electronic Materials, Inc. Silicon on insulator structure from low defect density single crystal silicon
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
US6284039B1 (en) * 1998-10-14 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafers substantially free of grown-in defects
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US6361619B1 (en) 1998-09-02 2002-03-26 Memc Electronic Materials, Inc. Thermally annealed wafers having improved internal gettering
US20020068149A1 (en) * 1998-11-16 2002-06-06 Eiichi Koyama Three-dimension ceramics structure and method for producing the same
US6409826B2 (en) 1997-04-09 2002-06-25 Memc Electronic Materials, Inc. Low defect density, self-interstitial dominated silicon
US20020083889A1 (en) * 1998-10-14 2002-07-04 Memc Electronic Materials, Inc. Thermal annealing process for producing low defect density single crystal silicon
US20020100410A1 (en) * 2001-01-26 2002-08-01 Memc Electronic Materials, Inc. Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults
US20020179006A1 (en) * 2001-04-20 2002-12-05 Memc Electronic Materials, Inc. Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
US20030051657A1 (en) * 1997-04-09 2003-03-20 Memc Electronic Materials, Inc. Vacancy, dominated, defect-free silicon
US20030054641A1 (en) * 2001-04-11 2003-03-20 Memc Electronic Materials, Inc. Control of thermal donor formation in high resistivity CZ silicon
US6562123B2 (en) 1998-06-26 2003-05-13 Memc Electronic Materials, Inc. Process for growing defect-free silicon wherein the grown silicon is cooled in a separate chamber
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6666915B2 (en) 1999-06-14 2003-12-23 Memc Electronic Materials, Inc. Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US20050005841A1 (en) * 2003-07-08 2005-01-13 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
US20050006796A1 (en) * 1998-08-05 2005-01-13 Memc Electronic Materials, Inc. Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices
US20050032337A1 (en) * 2000-06-30 2005-02-10 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US20070105279A1 (en) * 2005-11-09 2007-05-10 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20070155134A1 (en) * 2005-12-27 2007-07-05 Katsuhiko Nakai Annealed wafer and manufacturing method of annealed wafer
US20070269361A1 (en) * 2006-05-19 2007-11-22 Memc Electronic Materials, Inc. Silicon material with controlled agglomerated point defects and oxygen clusters induced by the lateral surface
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US20110177682A1 (en) * 2007-06-29 2011-07-21 Memc Electronic Materials, Inc. Suppression of oxygen precipitation in heavily doped single crystal silicon substrates
US20180342402A1 (en) * 2016-11-14 2018-11-29 Shin-Etsu Chemical Co., Ltd. Method for producing high-photoelectric-conversion-efficiency solar cell and high-photoelectric-conversion-efficiency solar cell

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1914796B1 (en) * 1998-09-02 2012-06-06 MEMC Electronic Materials, Inc. Method of forming non-oxygen precipitating Czochralski silicon wafers
EP1983561A2 (en) * 2001-07-10 2008-10-22 Shin-Etsu Handotai Company Limited Silicon epitaxial wafer manufacturing method and a silicon epitaxial wafer manufactured accordingly
TWI276161B (en) * 2001-12-21 2007-03-11 Memc Electronic Materials Ideal oxygen precipitating silicon wafers with nitrogen/carbon stabilized oxygen precipitate nucleation centers and process for making the same
US6808781B2 (en) 2001-12-21 2004-10-26 Memc Electronic Materials, Inc. Silicon wafers with stabilized oxygen precipitate nucleation centers and process for making the same
US7201800B2 (en) 2001-12-21 2007-04-10 Memc Electronic Materials, Inc. Process for making silicon wafers with stabilized oxygen precipitate nucleation centers
KR20040007025A (ko) * 2002-07-16 2004-01-24 주식회사 하이닉스반도체 반도체 웨이퍼 제조 방법
CN100338270C (zh) * 2004-11-05 2007-09-19 北京有色金属研究总院 一种单晶硅抛光片热处理工艺
JP5597378B2 (ja) * 2009-03-27 2014-10-01 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの熱処理方法
TWI614808B (zh) 2012-11-19 2018-02-11 太陽愛迪生公司 藉由活化非活性氧沉澱核製造高沉澱密度晶圓之方法
JP6260100B2 (ja) * 2013-04-03 2018-01-17 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
FR3009380B1 (fr) * 2013-08-02 2015-07-31 Commissariat Energie Atomique Procede de localisation d'une plaquette dans son lingot
SG11201900068PA (en) * 2016-07-06 2019-02-27 Tokuyama Corp Single crystal silicon plate-shaped body and production method therefor
CN109841513A (zh) * 2017-11-24 2019-06-04 上海新昇半导体科技有限公司 一种晶片及其制造方法、电子装置
CN109346433B (zh) * 2018-09-26 2020-10-23 上海新傲科技股份有限公司 半导体衬底的键合方法以及键合后的半导体衬底

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2080780A (en) * 1980-07-18 1982-02-10 Secr Defence Heat treatment of silicon slices
EP0090320A1 (en) * 1982-03-26 1983-10-05 International Business Machines Corporation A method for tailoring oxygen precipitate particle density and distribution in silicon
EP0098406A1 (en) * 1982-07-06 1984-01-18 Texas Instruments Incorporated Ramped nucleation of solid state phase changes
US4474641A (en) * 1981-04-29 1984-10-02 U.S. Philips Corporation Method of drawing a silicon rod
US4622082A (en) * 1984-06-25 1986-11-11 Monsanto Company Conditioned semiconductor substrates
US4809196A (en) * 1986-04-10 1989-02-28 International Business Machines Corporation Method for designating/sorting semiconductor wafers according to predicted oxygen precipitation behavior
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
EP0390672A2 (en) * 1989-03-31 1990-10-03 Shin-Etsu Handotai Company Limited Method for heat process of silicon
US5096839A (en) * 1989-09-20 1992-03-17 Kabushiki Kaisha Toshiba Silicon wafer with defined interstitial oxygen concentration
JPH04124094A (ja) * 1990-09-12 1992-04-24 Fujitsu Ltd シリコン単結晶の酸素析出方法
US5131974A (en) * 1989-11-16 1992-07-21 Shin-Etsu Handotai Co., Ltd. Method of controlling oxygen concentration in single crystal and an apparatus therefor
EP0536958A1 (en) * 1991-10-07 1993-04-14 Shin-Etsu Handotai Company Limited Process for producing a semiconductor wafer
US5286658A (en) * 1991-03-05 1994-02-15 Fujitsu Limited Process for producing semiconductor device
US5385115A (en) * 1990-09-21 1995-01-31 Komatsu Electronic Metals Co., Ltd. Semiconductor wafer heat treatment method
US5403406A (en) * 1990-11-15 1995-04-04 Memc Electronic Materials, Spa Silicon wafers having controlled precipitation distribution

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197827A (en) * 1981-05-29 1982-12-04 Hitachi Ltd Semiconductor substrate
WO1989011731A1 (en) * 1988-05-17 1989-11-30 Xicor, Inc. Deposited tunneling oxide
JPH0226031A (ja) * 1988-07-14 1990-01-29 Toshiba Ceramics Co Ltd シリコンウェーハ
DE3841352A1 (de) * 1988-12-08 1990-06-21 Philips Patentverwaltung Verfahren zur herstellung eines maskentraegers aus sic fuer strahlungslithographie-masken
CA2064486C (en) * 1992-03-31 2001-08-21 Alain Comeau Method of preparing semiconductor wafer with good intrinsic gettering

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2080780A (en) * 1980-07-18 1982-02-10 Secr Defence Heat treatment of silicon slices
US4474641A (en) * 1981-04-29 1984-10-02 U.S. Philips Corporation Method of drawing a silicon rod
EP0090320A1 (en) * 1982-03-26 1983-10-05 International Business Machines Corporation A method for tailoring oxygen precipitate particle density and distribution in silicon
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
EP0098406A1 (en) * 1982-07-06 1984-01-18 Texas Instruments Incorporated Ramped nucleation of solid state phase changes
US4622082A (en) * 1984-06-25 1986-11-11 Monsanto Company Conditioned semiconductor substrates
US4809196A (en) * 1986-04-10 1989-02-28 International Business Machines Corporation Method for designating/sorting semiconductor wafers according to predicted oxygen precipitation behavior
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
EP0390672A2 (en) * 1989-03-31 1990-10-03 Shin-Etsu Handotai Company Limited Method for heat process of silicon
US5110404A (en) * 1989-03-31 1992-05-05 Shin-Etsu Handotai Co., Ltd. Method for heat processing of silicon
US5096839A (en) * 1989-09-20 1992-03-17 Kabushiki Kaisha Toshiba Silicon wafer with defined interstitial oxygen concentration
US5131974A (en) * 1989-11-16 1992-07-21 Shin-Etsu Handotai Co., Ltd. Method of controlling oxygen concentration in single crystal and an apparatus therefor
JPH04124094A (ja) * 1990-09-12 1992-04-24 Fujitsu Ltd シリコン単結晶の酸素析出方法
US5385115A (en) * 1990-09-21 1995-01-31 Komatsu Electronic Metals Co., Ltd. Semiconductor wafer heat treatment method
US5403406A (en) * 1990-11-15 1995-04-04 Memc Electronic Materials, Spa Silicon wafers having controlled precipitation distribution
US5286658A (en) * 1991-03-05 1994-02-15 Fujitsu Limited Process for producing semiconductor device
EP0536958A1 (en) * 1991-10-07 1993-04-14 Shin-Etsu Handotai Company Limited Process for producing a semiconductor wafer

Cited By (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788763A (en) * 1995-03-09 1998-08-04 Toshiba Ceramics Co., Ltd. Manufacturing method of a silicon wafer having a controlled BMD concentration
US5904768A (en) * 1996-10-15 1999-05-18 Memc Electronic Materials, Inc. Process for controlling the oxygen content in silicon wafers heavily doped with antimony or arsenic
US6306733B1 (en) 1997-02-26 2001-10-23 Memc Electronic Materials, Spa Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6586068B1 (en) 1997-02-26 2003-07-01 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile and a process for the preparation thereof
US6180220B1 (en) * 1997-02-26 2001-01-30 Memc Electronic Materials, Inc. Ideal Oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US20030196586A1 (en) * 1997-02-26 2003-10-23 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6537368B2 (en) 1997-02-26 2003-03-25 Memc Electronic Materials Spa Ideal oxygen precipitating epitaxial silicon wafers and oxygen out-diffusion-less process therefor
US6204152B1 (en) 1997-02-26 2001-03-20 Memc Electronic Materials, Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6849119B2 (en) 1997-02-26 2005-02-01 Memc Electronic Materials, Inc. Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US20050205000A1 (en) * 1997-04-09 2005-09-22 Memc Electronic Materials, Inc. Low defect density silicon
US6190631B1 (en) * 1997-04-09 2001-02-20 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US6555194B1 (en) 1997-04-09 2003-04-29 Memc Electronic Materials, Inc. Process for producing low defect density, ideal oxygen precipitating silicon
US7229693B2 (en) 1997-04-09 2007-06-12 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US20050238905A1 (en) * 1997-04-09 2005-10-27 Memc Electronic Materials, Inc. Vacancy-dominated, defect-free silicon
US6632278B2 (en) 1997-04-09 2003-10-14 Memc Electronic Materials, Inc. Low defect density epitaxial wafer and a process for the preparation thereof
US20050170610A1 (en) * 1997-04-09 2005-08-04 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US6409826B2 (en) 1997-04-09 2002-06-25 Memc Electronic Materials, Inc. Low defect density, self-interstitial dominated silicon
US20070224783A1 (en) * 1997-04-09 2007-09-27 Memc Electronic Materials, Inc. Process for forming low defect density, ideal oxygen precipitating silicon
US6896728B2 (en) 1997-04-09 2005-05-24 Memc Electronic Materials, Inc. Process for producing low defect density, ideal oxygen precipitating silicon
US20040025782A1 (en) * 1997-04-09 2004-02-12 Memc Electronic Materials, Inc. Process for producing low defect density, ideal oxygen precipitating silicon
US7442253B2 (en) 1997-04-09 2008-10-28 Memc Electronic Materials, Inc. Process for forming low defect density, ideal oxygen precipitating silicon
US20040089224A1 (en) * 1997-04-09 2004-05-13 Memc Electronic Materials, Inc. Process for producing low defect density silicon
US20030051657A1 (en) * 1997-04-09 2003-03-20 Memc Electronic Materials, Inc. Vacancy, dominated, defect-free silicon
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US6913647B2 (en) 1998-06-26 2005-07-05 Memc Electronic Materials, Inc. Process for cooling a silicon ingot having a vacancy dominated region to produce defect free silicon
US6562123B2 (en) 1998-06-26 2003-05-13 Memc Electronic Materials, Inc. Process for growing defect-free silicon wherein the grown silicon is cooled in a separate chamber
US20040003770A1 (en) * 1998-06-26 2004-01-08 Memc Electronic Materials, Inc. Process for cooling a silicon ingot having a vacancy dominated region to produce defect free silicon
US20050006796A1 (en) * 1998-08-05 2005-01-13 Memc Electronic Materials, Inc. Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices
US20070238266A1 (en) * 1998-08-05 2007-10-11 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
US7242037B2 (en) 1998-08-05 2007-07-10 Memc Electronic Materials, Inc. Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices
US7618879B2 (en) 1998-08-05 2009-11-17 Memc Electronics Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
US6713370B2 (en) 1998-09-02 2004-03-30 Memc Electronic Materials, Inc. Process for the preparation of an ideal oxygen precipitating silicon wafer capable of forming an enhanced denuded zone
US6849901B2 (en) 1998-09-02 2005-02-01 Memc Electronic Materials, Inc. Device layer of a silicon-on-insulator structure having vacancy dominated and substantially free of agglomerated vacancy-type defects
US6191010B1 (en) 1998-09-02 2001-02-20 Memc Electronic Materials, Inc. Process for preparing an ideal oxygen precipitating silicon wafer
US6579779B1 (en) 1998-09-02 2003-06-17 Memc Electronic Materials, Inc. Process for the preparation of an ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile capable of forming an enhanced denuded zone
US6361619B1 (en) 1998-09-02 2002-03-26 Memc Electronic Materials, Inc. Thermally annealed wafers having improved internal gettering
US6236104B1 (en) 1998-09-02 2001-05-22 Memc Electronic Materials, Inc. Silicon on insulator structure from low defect density single crystal silicon
US20050130394A1 (en) * 1998-09-02 2005-06-16 Memc Electronic Materials, Inc. Process for implementing oxygen into a silicon wafer having a region which is free of agglomerated intrinsic point defects
US6686260B2 (en) 1998-09-02 2004-02-03 Memc Electronics Materials, Inc. Process for producing thermally annealed wafers having improved internal gettering
US20080020168A1 (en) * 1998-09-02 2008-01-24 Memc Electronic Materials, Inc. Silicon on insulator structure with a single crystal cz silicon device layer having a region which is free of agglomerated intrinsic point defects
US6709511B2 (en) 1998-09-02 2004-03-23 Memc Electronic Materials, Inc. Process for suppressing oxygen precipitation in vacancy dominated silicon
US6342725B2 (en) 1998-09-02 2002-01-29 Memc Electronic Materials, Inc. Silicon on insulator structure having a low defect density handler wafer and process for the preparation thereof
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
US6432197B2 (en) 1998-09-02 2002-08-13 Memc Electronic Materials, Inc. Process for the preparation of non-oxygen precipitating Czochralski silicon wafers
US7097718B2 (en) 1998-10-14 2006-08-29 Memc Electronic Materials, Inc. Single crystal silicon wafer having an epitaxial layer substantially free from grown-in defects
US6743289B2 (en) 1998-10-14 2004-06-01 Memc Electronic Materials, Inc. Thermal annealing process for producing low defect density single crystal silicon
US6284039B1 (en) * 1998-10-14 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafers substantially free of grown-in defects
US6565649B2 (en) 1998-10-14 2003-05-20 Memc Electronic Materials, Inc. Epitaxial wafer substantially free of grown-in defects
US20030205191A1 (en) * 1998-10-14 2003-11-06 Memc Electronic Materials, Inc. Single crystal silicon wafer having an epitaxial layer substantially free from grown-in defects
US20020083889A1 (en) * 1998-10-14 2002-07-04 Memc Electronic Materials, Inc. Thermal annealing process for producing low defect density single crystal silicon
US6416836B1 (en) 1998-10-14 2002-07-09 Memc Electronic Materials, Inc. Thermally annealed, low defect density single crystal silicon
US20020068149A1 (en) * 1998-11-16 2002-06-06 Eiichi Koyama Three-dimension ceramics structure and method for producing the same
US6284384B1 (en) 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
US20050098092A1 (en) * 1998-12-09 2005-05-12 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
US6537655B2 (en) 1998-12-09 2003-03-25 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
US6958092B2 (en) 1998-12-09 2005-10-25 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering and a method for the preparation thereof
US6666915B2 (en) 1999-06-14 2003-12-23 Memc Electronic Materials, Inc. Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US20050032337A1 (en) * 2000-06-30 2005-02-10 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US20020100410A1 (en) * 2001-01-26 2002-08-01 Memc Electronic Materials, Inc. Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults
US6846539B2 (en) 2001-01-26 2005-01-25 Memc Electronic Materials, Inc. Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults
US20050150445A1 (en) * 2001-01-26 2005-07-14 Memc Electronic Materials, Inc. Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults
US7217320B2 (en) 2001-01-26 2007-05-15 Memc Electronics Materials, Inc. Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults
US20050158969A1 (en) * 2001-04-11 2005-07-21 Memc Electronic Materials, Inc. Control of thermal donor formation in high resistivity CZ silicon
US7135351B2 (en) 2001-04-11 2006-11-14 Memc Electronic Materials, Inc. Method for controlling of thermal donor formation in high resistivity CZ silicon
US6897084B2 (en) 2001-04-11 2005-05-24 Memc Electronic Materials, Inc. Control of oxygen precipitate formation in high resistivity CZ silicon
US20030054641A1 (en) * 2001-04-11 2003-03-20 Memc Electronic Materials, Inc. Control of thermal donor formation in high resistivity CZ silicon
US20020179006A1 (en) * 2001-04-20 2002-12-05 Memc Electronic Materials, Inc. Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
US20060075960A1 (en) * 2001-04-20 2006-04-13 Memc Electronic Materials, Inc. Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
US6955718B2 (en) 2003-07-08 2005-10-18 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
US20050005841A1 (en) * 2003-07-08 2005-01-13 Memc Electronic Materials, Inc. Process for preparing a stabilized ideal oxygen precipitating silicon wafer
US20070105279A1 (en) * 2005-11-09 2007-05-10 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US7485928B2 (en) 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090130824A1 (en) * 2005-11-09 2009-05-21 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US8026145B2 (en) 2005-11-09 2011-09-27 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US8545622B2 (en) * 2005-12-27 2013-10-01 Siltronic Ag Annealed wafer and manufacturing method of annealed wafer
US20070155134A1 (en) * 2005-12-27 2007-07-05 Katsuhiko Nakai Annealed wafer and manufacturing method of annealed wafer
US8216362B2 (en) 2006-05-19 2012-07-10 Memc Electronic Materials, Inc. Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during CZ growth
US20070269361A1 (en) * 2006-05-19 2007-11-22 Memc Electronic Materials, Inc. Silicon material with controlled agglomerated point defects and oxygen clusters induced by the lateral surface
US8673248B2 (en) 2006-05-19 2014-03-18 Memc Electronic Materials, Inc. Silicon material with controlled agglomerated point defects and oxygen clusters induced by the lateral surface
US20110177682A1 (en) * 2007-06-29 2011-07-21 Memc Electronic Materials, Inc. Suppression of oxygen precipitation in heavily doped single crystal silicon substrates
US20090252974A1 (en) * 2007-06-29 2009-10-08 Memc Electronic Materials, Inc. Epitaxial wafer having a heavily doped substrate and process for the preparation thereof
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US20180342402A1 (en) * 2016-11-14 2018-11-29 Shin-Etsu Chemical Co., Ltd. Method for producing high-photoelectric-conversion-efficiency solar cell and high-photoelectric-conversion-efficiency solar cell
US10692736B2 (en) * 2016-11-14 2020-06-23 Shin-Etsu Chemical Co., Ltd. Method for producing high-photoelectric-conversion-efficiency solar cell and high-photoelectric-conversion-efficiency solar cell

Also Published As

Publication number Publication date
SG43246A1 (en) 1997-10-17
MY115003A (en) 2003-03-31
CN1061705C (zh) 2001-02-07
DE69630328T2 (de) 2004-05-06
JPH08253392A (ja) 1996-10-01
KR960035771A (ko) 1996-10-28
TW344850B (en) 1998-11-11
DE69630328D1 (de) 2003-11-20
CN1136604A (zh) 1996-11-27
EP0732431B1 (en) 2003-10-15
EP0732431A1 (en) 1996-09-18

Similar Documents

Publication Publication Date Title
US5593494A (en) Precision controlled precipitation of oxygen in silicon
US5994761A (en) Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
US6336968B1 (en) Non-oxygen precipitating czochralski silicon wafers
US4851358A (en) Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
US4868133A (en) Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US5401669A (en) Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
US6579779B1 (en) Process for the preparation of an ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile capable of forming an enhanced denuded zone
US5882989A (en) Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US4481044A (en) High-temperature Hg anneal for HgCdTe
EP1914796B1 (en) Method of forming non-oxygen precipitating Czochralski silicon wafers
JPH04124094A (ja) シリコン単結晶の酸素析出方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEMC ELECTRONIC MATERIALS, INC., MISSOURI

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FALSTER, ROBERT;REEL/FRAME:007468/0720

Effective date: 19950427

AS Assignment

Owner name: GEA TILL GMBH & CO., GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TILL, VOLKER;REEL/FRAME:007488/0632

Effective date: 19950505

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: MEMC ELECTRONIC MATERIALS, INC., MISSOURI

Free format text: TERMINATION OF SECURITY INTEREST;ASSIGNOR:E.ON AG;REEL/FRAME:012263/0944

Effective date: 20011113

Owner name: CITICORP USA, INC., DELAWARE

Free format text: SECURITY INTEREST;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012273/0145

Effective date: 20011113

Owner name: CITICORP USA, INC., DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012280/0161

Effective date: 20011113

AS Assignment

Owner name: E. ON AG, GERMANY

Free format text: SECURITY INTEREST;ASSIGNOR:MEMC ELECTRONIC MATERIALS, INC.;REEL/FRAME:012407/0806

Effective date: 20011025

AS Assignment

Owner name: CITICORP USA, INC., DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC PASADENA, INC.;PLASMASIL, L.L.C.;SIBOND, L.L.C.;AND OTHERS;REEL/FRAME:012365/0345

Effective date: 20011221

AS Assignment

Owner name: CITICORP USA, INC., DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC ELECTRONIC MATERIALS, INC.;MEMC PASADENA, INC.;PLASMASIL, L.L.C.;AND OTHERS;REEL/FRAME:013964/0378;SIGNING DATES FROM 20020303 TO 20030303

Owner name: CITICORP USA, INC., DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC ELECTRONIC MATERIALS, INC.;MEMC PASADENA, INC.;PLASMASIL, L.L.C.;AND OTHERS;SIGNING DATES FROM 20020303 TO 20030303;REEL/FRAME:013964/0378

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: MEMC ELECTRONIC MATERIALS, INC., MISSOURI

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:016641/0045

Effective date: 20050602

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: BANK OF AMERICA, N.A., MASSACHUSETTS

Free format text: SECURITY AGREEMENT;ASSIGNORS:MEMC ELECTRONIC MATERIALS, INC.;SUNEDISON LLC;SOLAICX;REEL/FRAME:026064/0720

Effective date: 20110317

AS Assignment

Owner name: GOLDMAN SACHS BANK USA, NEW JERSEY

Free format text: SECURITY AGREEMENT;ASSIGNORS:NVT, LLC;SUN EDISON LLC;SOLAICX, INC.;AND OTHERS;REEL/FRAME:029057/0810

Effective date: 20120928

AS Assignment

Owner name: SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS,

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:031870/0031

Effective date: 20131220

Owner name: SUN EDISON LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:031870/0031

Effective date: 20131220

Owner name: SOLAICX, OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:GOLDMAN SACHS BANK USA;REEL/FRAME:031870/0092

Effective date: 20131220

Owner name: ENFLEX CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:031870/0031

Effective date: 20131220

Owner name: NVT, LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:GOLDMAN SACHS BANK USA;REEL/FRAME:031870/0092

Effective date: 20131220

Owner name: SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS,

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:GOLDMAN SACHS BANK USA;REEL/FRAME:031870/0092

Effective date: 20131220

Owner name: SUN EDISON LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:GOLDMAN SACHS BANK USA;REEL/FRAME:031870/0092

Effective date: 20131220

Owner name: SOLAICX, OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:031870/0031

Effective date: 20131220

AS Assignment

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, NEW JERSEY

Free format text: SECURITY AGREEMENT;ASSIGNORS:SUNEDISON, INC.;SOLAICX;SUN EDISON, LLC;AND OTHERS;REEL/FRAME:032177/0359

Effective date: 20140115

AS Assignment

Owner name: SOLAICX, OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH;REEL/FRAME:032382/0724

Effective date: 20140228

Owner name: SUNEDISON, INC., MISSOURI

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH;REEL/FRAME:032382/0724

Effective date: 20140228

Owner name: SUN EDISON LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH;REEL/FRAME:032382/0724

Effective date: 20140228

Owner name: NVT, LLC, MARYLAND

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH;REEL/FRAME:032382/0724

Effective date: 20140228

AS Assignment

Owner name: MEMC INTERNATIONAL, INC. (NOW KNOWN AS SUNEDISON I

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

Owner name: SIBOND, L.L.C., MISSOURI

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

Owner name: PLASMASIL, L.L.C., MISSOURI

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

Owner name: MEMC PASADENA, INC., TEXAS

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

Owner name: MEMC SOUTHWEST INC., MISSOURI

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

Owner name: MEMC ELECTRONIC MATERIALS, INC. (NOW KNOWN AS SUNE

Free format text: RELEASE OF SECURITY INTEREST TO REEL/FRAME: 012280/0161;ASSIGNOR:CITICORP USA, INC.;REEL/FRAME:032458/0794

Effective date: 20140313

AS Assignment

Owner name: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H), S

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEMC ELECTRONIC MATERIALS, INC.;REEL/FRAME:033023/0430

Effective date: 20140523

AS Assignment

Owner name: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD., MISS

Free format text: NOTICE OF LICENSE AGREEMENT;ASSIGNOR:SUNEDISON SEMICONDUCTOR LIMITED;REEL/FRAME:033099/0001

Effective date: 20140527