US5592005A - Punch-through field effect transistor - Google Patents

Punch-through field effect transistor Download PDF

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US5592005A
US5592005A US08/415,009 US41500995A US5592005A US 5592005 A US5592005 A US 5592005A US 41500995 A US41500995 A US 41500995A US 5592005 A US5592005 A US 5592005A
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region
semiconductor device
body region
gate electrode
source
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Brian H. Floyd
Fwu-Iuan Hshieh
Mike F. Chang
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Vishay Siliconix Inc
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Siliconix Inc
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Priority to US08/415,009 priority Critical patent/US5592005A/en
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Assigned to SILICONIX INCORPORATED reassignment SILICONIX INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, MIKE F., FLOYD, BRIAN H., HSHIEH, FWU-IUAN
Priority to KR1019960706704A priority patent/KR100256903B1/ko
Priority to EP96909739A priority patent/EP0763259B1/de
Priority to JP52947096A priority patent/JP3202021B2/ja
Priority to DE69621200T priority patent/DE69621200T2/de
Priority to PCT/US1996/003639 priority patent/WO1996030947A1/en
Publication of US5592005A publication Critical patent/US5592005A/en
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Priority to US08/962,885 priority patent/US6069043A/en
Priority to US09/481,135 priority patent/US6444527B1/en
Assigned to COMERICA BANK, AS AGENT reassignment COMERICA BANK, AS AGENT SECURITY AGREEMENT Assignors: SILICONIX INCORPORATED, VISHAY DALE ELECTRONICS, INC., VISHAY INTERTECHNOLOGY, INC., VISHAY MEASUREMENTS GROUP, INC., VISHAY SPRAGUE, INC., SUCCESSOR IN INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC
Assigned to SILICONIX INCORPORATED, A DELAWARE CORPORATION, VISHAY DALE ELECTRONICS, INC., A DELAWARE CORPORATION, VISHAY GENERAL SEMICONDUCTOR, LLC, F/K/A GENERAL SEMICONDUCTOR, INC., A DELAWARE LIMITED LIABILITY COMPANY, VISHAY INTERTECHNOLOGY, INC., A DELAWARE CORPORATION, VISHAY MEASUREMENTS GROUP, INC., A DELAWARE CORPORATION, VISHAY SPRAGUE, INC., SUCCESSOR-IN-INTEREST TO VISHAY EFI, INC. AND VISHAY THIN FILM, LLC, A DELAWARE CORPORATION, VISHAY VITRAMON, INCORPORATED, A DELAWARE CORPORATION, YOSEMITE INVESTMENT, INC., AN INDIANA CORPORATION reassignment SILICONIX INCORPORATED, A DELAWARE CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: COMERICA BANK, AS AGENT, A TEXAS BANKING ASSOCIATION (FORMERLY A MICHIGAN BANKING CORPORATION)
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Assigned to VISHAY INTERTECHNOLOGY, INC., VISHAY SPRAGUE, INC., SPRAGUE ELECTRIC COMPANY, VISHAY TECHNO COMPONENTS, LLC, VISHAY VITRAMON, INC., VISHAY EFI, INC., DALE ELECTRONICS, INC., VISHAY DALE ELECTRONICS, INC., SILICONIX INCORPORATED reassignment VISHAY INTERTECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

  • This invention relates to semiconductor devices and more particular to a trenched field effect transistor especially suitable for low voltage switching applications.
  • FETs Field effect transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • FIG. 1 shows only a portion of a single transistor including the polysilicon (polycrystalline silicon) gate electrode 10 which in this case is N-type polysilicon which is insulated by a gate oxide layer 12 on its sides and bottom in a trench 14 and insulated on its top side by an oxide layer 18.
  • the trench 14 extends through the N+ doped source region 22 through the P doped base region 24 and into the N+ doped drain region 26.
  • the drain electrode 30 is formed on the underside of the drain region 26 and the source electrode 32 formed on the top side of the source region.
  • FIG. 1(c) of this article and shown here in present FIG. 2 is the somewhat similar so-called EXTFET which is identical to the INVFET except for having an additional N- doped drift region 36 formed underlying the P doped base region 24.
  • the P base region 24 is formed by diffusion (hence does not exhibit uniform doping) and is fairly heavily doped. It is believed that a typical surface concentration of the P base region 24 is 10 17 /cm 3 .
  • These devices are both intended to avoid full depletion of the P base (body) region 24. They each have the gate electrode 10 doped to the same conductivity type as is the drain region 26 (i.e. N type) as shown in FIGS. 1 and 2.
  • the "mesa" width i.e. the width of the source region between two adjacent trenches, is typically 3 ⁇ m and a typical cell pitch for an N-channel device is about 6 ⁇ m. Blocking is accomplished by a quasi-neutral (undepleted) PN junction at a V gs (gate source voltage) of zero.
  • the ACCUFET offers the best specific on resistance at the expense of poor blocking capability, while the INVFET and EXTFET offer improved blocking at the expense of increased specific on resistance.
  • On-state resistance is a well known parameter of the efficiency of a power transistor and is the ratio of drain-to-source voltage to drain current when the device is fully turned on.
  • On-state specific resistance refers to resistance times cross sectional area of the substrate carrying the drain current.
  • This disclosure is directed to a MOS semiconductor device suitable especially for low voltage power application where low leakage blocking capability is desirable.
  • the off-state blocking of a trenched field effect transistor is achieved by a gate controlled barrier region between the source and drain. Similar to the above described INVFET, forward conduction occurs through an inversion region between the source and the drain (substrate). Unlike the INVFET, however, blocking is achieved by a gate controlled depletion barrier and not by a quasi-neutral PN junction. The depletion barrier is formed and controlled laterally and vertically so as to realize the benefits of ultra-low on-state specific resistance combined with the low current leakage blocking.
  • this structure is relatively easily fabricated and has blocking superior to that of prior art ACCUFET devices, with low leakage current at zero applied gate-source voltage. Moreover, in the blocking state there is no quasi-neutral PN junction, and therefore, like the ACCUFET, this structure offers the advantage of containing no parasitic bipolar PN junction.
  • the present device's on-state specific resistance is comparable to that of the ACCUFET, and like the ACCUFET offers on-state specific resistance superior to that of the INVFET and EXTFET as described in the above mentioned article by Syau et al.
  • an N+ drain region underlies a lightly doped P- body region which is overlain by an N+ source region.
  • the body region is formed by lightly doped epitaxy with uniform or almost uniform doping concentration, typically in a range of 10 14 to 10 16 /cm 3 .
  • the gate electrodes are formed in trenches which extend through the source region, through the body region, and partially into the drain (substrate) region. Alternatively, the gate electrodes do not extend into the drain region.
  • the polysilicon gate electrodes themselves are P doped, i.e. having a doping type the same as that of the body region. Additionally, the mesas (holding the source regions) located between adjacent gate electrode trenches are less than 1.5 ⁇ m wide, and the cell pitch is less than 3 ⁇ m.
  • the epitaxial P body region is depleted due to the applied drain-source bias V ds , and hence a punch-through type condition occurs vertically.
  • lateral gate control combined with the narrow mesa width (under 1.5 ⁇ m) increases the effective depletion barrier to majority carrier flow and prevents conduction.
  • the present device is referred to herein as the PT-FET for "punch-through field effect transistor".
  • a complementary P-channel device is implemented and has advantages comparable to those of the above described N-channel device.
  • the above described embodiment has a floating body region, thus allowing bidirectional operation.
  • a body contact region is provided extending into the body region from the principal surface of the semiconductor structure, thus allowing a source region to body region short via the source metallization for forward blocking-only applications.
  • the present PT-FET has a fully depleted (punch-through) lightly doped body region at a small applied drain-source voltage.
  • This differs from the P body region in the above described INVFET and EXTFET which must, by design, be undepleted to avoid punch-through.
  • the threshold voltage is low due to the lightly doped P body region and the device has an on-state specific resistance similar to that of the ACCUFET and superior to that of the INVFET or EXTFET.
  • FIG. 1 shows a prior art INVFET.
  • FIG. 2 shows a prior art EXTFET.
  • FIG. 3 shows an N-channel PT-FET in accordance with the present invention.
  • FIG. 4A shows operation of the present PT-FET in equilibrium.
  • FIG. 4B shows operation of the present PT-FET in the blocking (off) state with an applied drain-source voltage.
  • FIG. 4C shows operation of the present PT-FET in the on state.
  • FIG. 5 shows dimensions and further detail of one embodiment of a PT-FET.
  • FIGS. 6, 7 and 8 show three termination and poly runner structures suitable for use with the present PT-FET.
  • FIGS. 9A, 9B and 9C show process steps to fabricate a PT-FET in accordance with the present invention.
  • FIGS. 10A and 10B show two top side layouts for a PT-FET.
  • FIG. 11 shows a P-channel PT-FET.
  • FIG. 12 shows another embodiment of a PT-FET with a body contact region and the body region shorted to the source.
  • FIG. 3 shows a cross section (not to scale) of a portion of a trenched N-channel PT-FET in accordance with the present invention.
  • FIG. 2 like the other figures herein, is not to scale and that furthermore the various doped semiconductor regions shown herein, which are illustrated as precisely defined regions delineated by borderlines, are conventional representations of doped regions having in reality gradient dopant levels at their edges.
  • typically power MOSFETs include a large number of cells, the cells having various shapes such as square, circular, hexagonal, linear or others. These cells are evident in a top side view, several of which are provided below.
  • the PT-FET is conventional and may be fabricated in any one of a number of well known cell structures.
  • the present illustrations are therefore typically of only one cell or a portion of two cells as delineated by the gate trenches, and are not intended to illustrate an entire power transistor which would typically include hundreds or thousands of such cells.
  • FIG. 3 shows one embodiment of an N-channel PT-FET including a drain (substrate) region 40 which is N+ doped to have a resistivity of e.g. 0.002 ⁇ -cm. Formed immediately over the drain region 40 is a P- doped body region 42 having a doping concentration in the range of e.g. 10 14 to 10 16 /cm 3 and a typical doping concentration of 10 15 /cm 3 .
  • N+ doped source region 44 Overlying the body region 42 is the N+ doped source region 44 which is doped to a concentration of e.g. 2 ⁇ 10 19 /cm 3 .
  • a conventional metallized drain contact 48 is formed the backside of the semiconductor substrate.
  • trenches 50A, 50B Formed in the upper portion of the semiconductor structure are trenches 50A, 50B, which respectively hold P+ doped polysilicon gate electrodes 52A, 52B which are each doped P-type to a maximum attainable value. (It is to be understood that gate electrodes 52A, 52B are connected to each other outside the plane of the drawing).
  • Each trench 50A, 50B is lined with gate oxide layer 54 e.g. 500 ⁇ thick (a typical range is 400 to 800 ⁇ ) to insulate the polysilicon gate electrodes from the silicon sidewalls and bottom of the trenches 50A, 50B.
  • the passivation layer typically boro-phosphosilicate glass BPSG
  • the top side source contact metallization In this case the body region 42 is a "floating region", having no electrical contact made thereto. This structure has been found especially suitable for high current, low voltage switching applications, i.e. less than 25 volts.
  • FIGS. 4A, 4B and 4C The principle of operation of this device is illustrated in FIGS. 4A, 4B and 4C.
  • FIG. 4A illustrates equilibrium
  • FIG. 4B illustrates operation in the blocking (off) state.
  • the gate-source bias voltage (V gs ) is equal to zero in both FIGS. 4A and 4B.
  • V ds the drain-source voltage
  • FIG. 4A illustrates the body depletion for the situation where the drain-source voltage is equal to zero. (It is to be understood that there is plus (+) charge depletion in the N+ source and drain regions which is not drawn for simplicity.) This is an equilibrium state in terms of the charge distribution, as shown in FIG. 4A.
  • the drain-source voltage is greater than zero while the gate-source voltage is still equal to zero.
  • the body region is fully depleted.
  • the leakage current is controlled by an electron energy barrier formed within the body depletion region as shown.
  • the leakage current is reduced to acceptably low levels (e.g., 1% of that of an ACCUFET) by the P-doped polysilicon gate electrodes 52A, 52B.
  • a P-type polysilicon gate electrode for an N-channel device that is, the polysilicon gate electrode having the same conductivity type as the adjacent body region
  • the P-type polysilicon gate electrode allows the body region to remain fully depleted while it enhances the energy barrier to reduce leakage to acceptable levels (levels superior to those of the ACCUFET).
  • FIG. 4C illustrates the on state conduction which is typically the situation with the gate-source voltage being greater than the transistor threshold voltage and the drain-source voltage is greater than zero.
  • the inversion regions are along the trench 50A, 50B side walls which conduct majority carrier through the inversion region. Current flow takes place when the drain-source voltage is greater than zero, in the direction shown by the arrow.
  • the lightly doped body region 42 allows a low threshold voltage, while in addition the on-state specific resistance is superior to that of the INVFET or the EXTFET, and comparable to that of the ACCUFET.
  • FIG. 5 shows additional detail of an N channel PT-FET which is otherwise similar to that of FIGS. 3 and 4.
  • the conventional (passivation) layer 58 which is BPSG overlying each polysilicon gate electrode, and the metal, e.g. aluminum, source contact.
  • the gate oxide 54 thickness 500 ⁇
  • the source region 44 thickness (0.25 ⁇ m).
  • the typical trench 50A, 50B depth is 2.1 ⁇ m, which extends through the source region 44 and body region 42 and partially into the substrate region 40.
  • An exemplary thickness of the substrate (drain region 40) is 500 ⁇ m.
  • the mesa (the silicon between two adjacent gate trenches) is e.g. 1 ⁇ m (under 1.5 ⁇ m) in width while each trench 50A, 50B is 1 ⁇ m (under 1.5 ⁇ m) in width, thus allowing an exemplary 2 ⁇ m to 3 ⁇ m pitch per cell.
  • FIGS. 3, 4 and 5 each only illustrate one cell or a portion of two cells in the active portion of a typical multi-cell PT-FET.
  • FIG. 6 illustrates a first embodiment of a PT-FET with at the left side a termination region 64. At the right side is a "poly runner" region 68 for contacting low-resistivity metal (not shown) to the relatively higher resistivity gate electrode material.
  • FIG. 6 shows a number of cells (additional cells are omitted, as suggested by the broken lines) in the active region of the device.
  • the left side termination region 64 includes, adjacent the leftmost trench 50C, the absence of any N+ source region. Also present in termination region 64 is a BPSG layer 58A.
  • Source contact 60 is located between BPSG portions 58A, 58.
  • the right side poly runner region 68 (mesa), again there is no source region to the right of trench 50E.
  • This mesa provides a wide contact region for running metallization to select regions of polysilicon for the purpose of lowering total gate resistance.
  • the field oxide is also present in the poly runner region 68.
  • Polysilicon structure 52F includes a gate runner to the polysilicon gate electrode 52E of the adjacent cell in trench 50E.
  • FIG. 7 shows a second PT-FET having a termination region and poly runner region which differ from those of FIG. 6 in two ways.
  • P+ regions 62A, 62B are provided in both the left side termination and right side poly runner regions 64, 68. These P+ regions 62A, 62B prevent leakage in the relatively wide poly runner region 68 and prevent inversion in both the termination 64 and poly runner regions 68.
  • the N+ source regions 44A, 44B are present respectively in the termination and poly runner regions.
  • the polysilicon ("poly") runner in the right side poly runner region 68 extends over to contact the N+ region 44B in the poly runner region 68, with a contact 60B made to that N+ region for purposes of electrostatic (ESD) robustness.
  • FIG. 8 shows a third PT-FET similar to that of FIG. 7 in having the N+ regions 44A, 44B respectively in the termination and poly runner regions, but not having a P+ region in the termination or poly runner regions. Additionally the N+ region 44B in the right side poly runner region 68 does not have an exterior metallized contact (is floating) to prevent leakage in the relatively wide mesa region.
  • FIG. 8 is similar to FIGS. 6 and 7 in that polysilicon structure 52F includes a runner to the gate electrode 52E in adjacent trench 50E.
  • FIGS. 9A through 9C A process for fabricating an N-channel PT-FET is illustrated in FIGS. 9A through 9C.
  • an N+ doped silicon substrate 40 (having a resistivity e.g. 0.001-0.005 ⁇ -cm) is provided, on which is grown epitaxially a lightly doped P- region 42 having a doping concentration of 10 15 /cm 3 which becomes the body region.
  • a typical final thickness of this P-epitaxial layer 42 after all processing is 2 ⁇ m.
  • an active region mask (not shown) is formed over the principal surface of the epitaxial layer 42 to pattern the field oxide in the termination region and optionally in the poly runner region.
  • the active region mask patterns the field oxide in the termination region and opens the areas for active cells.
  • a source mask is formed and patterned, and then through the openings in the source mask the N+ source region 44 is implanted and diffused to a thickness (depth) of approximate 0.25 ⁇ m and a final surface doping concentration of e.g. 2 ⁇ 10 19 /cm 3 .
  • the N+ source region 44 due to the source region mask, is not implanted in the termination 64 and poly runner regions 68 (as shown in FIG. 6 for instance) in some embodiments.
  • the N+ source region implant is a maskless step which occurs before the field oxide/active mask steps.
  • the source region implant occurs after the active mask steps.
  • the upper surface of the P-doped epitaxial layer 42 is masked and the mask is patterned to define the trench locations.
  • the trenches are then conventionally anisotropically etched by e.g. dry etching to a depth of approximately 2.1 ⁇ m.
  • a gate oxide layer 54 e.g. 500 ⁇ thick (in a range of 400 to 800 ⁇ ) is formed lining the trenches and over the entire surface of the epitaxial layer 42.
  • a layer of polysilicon is deposited filling the trenches and over the entire surface of the epitaxial layer.
  • the polysilicon is then heavily doped with a P type dopant before it is patterned.
  • a mask is then applied to the upper surface of the polysilicon and the mask is patterned and the polysilicon etched to define the gate electrodes and the polysilicon runners (as described above) connecting the gate electrodes.
  • the P+ region 62A, 62B is implanted using a mask by e.g. a high energy implant, either before or after the trenches are etched and filled.
  • a layer of BPSG 58 is formed thereover and subsequently patterned using a mask to define the contact openings to the silicon surface.
  • the metallization layer is deposited and conventionally patterned using a mask. Then conventionally a final e.g. PSG or nitride passivation layer (not shown) is formed and masked to define the contact pads.
  • a final e.g. PSG or nitride passivation layer (not shown) is formed and masked to define the contact pads.
  • FIG. 10A illustrates a top side view of a portion of the PT-FET in accordance with one embodiment.
  • the cells are rectangular and isolated by the trenches, the small rectangles being the source regions 70-1 . . . , 70-n.
  • the trenches are formed in a criss-cross pattern to define the rectangular cells.
  • the mesa region 82 surrounding the cells is the termination region as in FIGS. 6-8.
  • FIG. 10B shows alternatively a linear cell type arrangement where the trenches, while criss-crossing, have a different spacing in the left-right direction than they do in the vertical direction in the drawing.
  • This represents a linear open-cell geometry with source regions 72-1, 72-2, . . . , 72-n each isolated by the trenches and termination mesa region 82.
  • FIG. 11 depicts the P-channel complement of the PT-FET of FIG. 3.
  • This PT-FET has all conductivity types opposite to that of the PT-FET of FIG. 3. Shown are drain region 82, body region 84, source region 86, and N+ doped gate electrodes 88A, 88B. Similarly, in the termination region (not shown) the conductivity types are complementary to those of FIG. 3.
  • the dimensions of the PT-FET of FIG. 11 would be similar to those of FIG. 5, as is the doping concentration for each particular region within well known material constraints.
  • FIG. 12 shows another embodiment of an N-channel PT-FET which in most respects is identical to that of FIG. 3, but has the addition of a P+ doped body contact region 92 formed in an upper portion of the semiconductor structure. This allows, via a conventional source-body contact (not shown in FIG. 12), the shorting of the source region 44 to the body region 42. This prevents bidirectional operation and so provides a device which operates with forward conductivity only.

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  • General Physics & Mathematics (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US08/415,009 1995-03-31 1995-03-31 Punch-through field effect transistor Expired - Lifetime US5592005A (en)

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US08/415,009 US5592005A (en) 1995-03-31 1995-03-31 Punch-through field effect transistor
KR1019960706704A KR100256903B1 (ko) 1995-03-31 1996-03-29 전계효과 트랜지스터
EP96909739A EP0763259B1 (de) 1995-03-31 1996-03-29 Durchgriff-feldeffekttransistor
JP52947096A JP3202021B2 (ja) 1995-03-31 1996-03-29 パンチスルー電界効果トランジスタ
DE69621200T DE69621200T2 (de) 1995-03-31 1996-03-29 Durchgriff-feldeffekttransistor
PCT/US1996/003639 WO1996030947A1 (en) 1995-03-31 1996-03-29 Punch-through field effect transistor
US08/962,885 US6069043A (en) 1995-03-31 1997-11-12 Method of making punch-through field effect transistor
US09/481,135 US6444527B1 (en) 1995-03-31 2000-01-11 Method of operation of punch-through field effect transistor

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JPH09511876A (ja) 1997-11-25
JP3202021B2 (ja) 2001-08-27
EP0763259A1 (de) 1997-03-19
US6444527B1 (en) 2002-09-03
US20020055232A1 (en) 2002-05-09
EP0763259B1 (de) 2002-05-15
KR100256903B1 (ko) 2000-05-15
WO1996030947A1 (en) 1996-10-03
DE69621200T2 (de) 2002-08-29
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KR970703622A (ko) 1997-07-03
DE69621200D1 (de) 2002-06-20

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