US20050029618A1 - Structure and method of forming a dual-trench field effect transistor - Google Patents

Structure and method of forming a dual-trench field effect transistor Download PDF

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US20050029618A1
US20050029618A1 US10934969 US93496904A US2005029618A1 US 20050029618 A1 US20050029618 A1 US 20050029618A1 US 10934969 US10934969 US 10934969 US 93496904 A US93496904 A US 93496904A US 2005029618 A1 US2005029618 A1 US 2005029618A1
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semiconductor
mosfet
stripe
trench
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Bruce Marchant
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Marchant Bruce D.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

A field effect transistor includes a semiconductor region of a first conductivity type and a well region of a second conductivity type over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation of U.S. application Ser. No. 10/741,464, filed Dec. 18, 2003, which is a division of U.S. Pat. No. 6,713,813 issued Mar. 30, 2004, which disclosures are incorporated herein by reference for all purposes.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Embodiments of the invention relate to field effect transistors such as MOSFET (metal oxide semiconductor field effect transistor) devices and methods for making field effect transistors.
  • [0003]
    Power MOSFET devices are well known and are used in many applications. Exemplary applications include automotive electronics, portable electronics, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its drain-to-source on-state resistance (RDS(on)), which is defined as the total resistance encountered by a drain current. RDS(on) is proportional to the amount of power consumed while the MOSFET device is on. In a vertical power MOSFET device, this total, resistance is composed of several resistive components including an inversion channel resistance (“channel resistance”), a starting substrate resistance, an epitaxial portion resistance and other resistances. The epitaxial portion is typically in the form of a layer and may be referred to as an “epilayer”. RDS(on) can be reduced in a MOSFET device by reducing the resistance of one or more of these MOSFET device components.
  • [0004]
    Reducing RDS(on) is desirable. For example, reducing RDS(on) for a MOSFET device reduces its power consumption and also cuts down on wasteful heat dissipation. The reduction of RDS(on) for a MOSFET device preferably takes place without detrimentally impacting other MOSFET characteristics such as the maximum breakdown voltage (BVDSS) of the device. At the maximum breakdown voltage, a reverse-biased epilayer/well diode in a MOSFET breaks down resulting in significant and uncontrolled current flowing between the source and drain.
  • [0005]
    It is also desirable to maximize the breakdown voltage for a MOSFET device without increasing RDS(on). The breakdown voltage for a MOSFET device can be increased, for example, by increasing the resistivity of the epilayer or increasing the thickness of the epilayer. However, increasing the epilayer thickness or the epilayer resistivity undesirably increases RDS(on).
  • [0006]
    It would be desirable to provide for a MOSFET device with a high breakdown voltage and a low RDS(on). Embodiments of the invention address this and other problems.
  • BRIEF SUMMARY OF THE INVENTION
  • [0007]
    Embodiments of the invention are directed to dual-trench field effect transistors and methods of manufacture. In one embodiment, a semiconductor region of a first conductivity type has a thickness defined by the distance between upper and lower surfaces of the semiconductor region. A well region of a second conductivity type is over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of second conductivity type forms a PN junction with the semiconductor region.
  • [0008]
    Another embodiment of the invention is directed to a method of forming a field effect transistor. A well region is formed in a semiconductor region of a first conductivity type. The well region is of a second conductivity type and has an upper surface and a lower surface. A plurality of gate trenches are formed which extend into the semiconductor region to a depth below the lower surface of the well region. A plurality of stripe trenches are formed which extend deeper into the semiconductor region than the plurality of gate trenches. The plurality of stripe trenches is laterally spaced from one or more of the plurality of gate trenches. The plurality of stripe trenches are at least partially filled with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.
  • [0009]
    These and other embodiments of the invention are described in greater detail below with reference to the appended drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    FIGS. 1(a) to 1(f) show schematic cross-sectional views of a conventional vertical trench MOSFET device. The figures show vertically expanding depletion regions as increasing reverse bias voltages are applied.
  • [0011]
    FIGS. 1(a) to 1(f) show schematic cross-sectional views of a conventional vertical trench MOSFET device. The figures show vertically expanding depletion regions as increasing reverse bias voltages are applied.
  • [0012]
    FIGS. 2(a) to 2(f) show schematic cross-sectional views of a vertical trench MOSFET device according to an embodiment of the invention. The figures show horizontally expanding depletion regions as increasing reverse bias voltages are applied.
  • [0013]
    FIGS. 3(a) to 3(f) show schematic cross sectional views of a vertical trench MOSFET device according to an embodiment of the invention. The figures show horizontally expanding depletion regions as increasing reverse bias voltages are applied.
  • [0014]
    FIG. 4 is a bar graph illustrating the various resistive components making up RDS(on) in various MOSFET devices with different breakdown voltage ratings.
  • [0015]
    FIG. 5 is a graph comparing reverse IV curves for conventional trench MOSFET devices with a reverse IV curve for a trench MOSFET device according to an embodiment of the invention.
  • [0016]
    FIG. 6 is a graph showing reverse IV curves for trench MOSFET devices with different P− stripe depths. The curves show the effect of varying P− stripe depths on BVDSS.
  • [0017]
    FIG. 7 is a graph showing reverse IV curves for trench MOSFET devices with different P− stripe widths. The curves show the effect of varying P− stripe widths on BVDSS.
  • [0018]
    FIGS. 8(a) to 8(d) are cross-sectional views illustrating a method for forming a MOSFET device according to an embodiment of the invention.
  • [0019]
    FIG. 8(e) shows a cross-sectional view of a MOSFET device with a stripe having a P− lining and a dielectric inner portion.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0020]
    The present inventor has found that the resistance of the epilayer in a MOSFET becomes an increasingly significant component of RDS(on) for increasing MOSFET voltage breakdown ratings. For example, computer simulations have indicated that for a 30 volt N-channel trench MOSFET device, the epilayer resistance is about 30% or more of the total specific RDS(on). In another example, for a 200 V N-channel trench MOSFET device, the epilayer resistance is about 75 to 90% of the total specific RDS(on). Thus, for higher voltage applications in particular, it would be desirable to reduce the resistance of the epilayer and thus reduce RDS(on) for a corresponding MOSFET device. The reduction of RDS(on) preferably takes place without degrading the breakdown voltage characteristics of the MOSFET device.
  • [0021]
    The present inventor has found that the resistance of the epilayer in a MOSFET becomes an increasingly significant component of RDS(on) for increasing MOSFET voltage breakdown ratings. For example, computer simulations have indicated that for a 30 volt N-channel trench MOSFET device, the epilayer resistance is about 30% or more of the total specific RDS(on). In another example, for a 200 V N-channel trench MOSFET device, the epilayer resistance is about 75 to 90% of the total specific RDS(on). Thus, for higher voltage applications in particular, it would be desirable to reduce the resistance of the epilayer and thus reduce RDS(on) for a corresponding MOSFET device. The reduction of RDS(on) preferably takes place without degrading the breakdown voltage characteristics of the MOSFET device.
  • [0022]
    Many numerical examples are provided to illustrate embodiments of the invention. It is to be understood that numerical examples such as breakdown voltage, RDS(on), etc. are provided herein for illustrative purposes only. These and other numbers or values in the application may vary significantly or insignificantly depending upon the specific semiconductor fabrication process used and, in particular, with future advances in semiconductor processing.
  • [0023]
    Under normal operation, the maximum breakdown voltage (BVDSS) of a trench or planar DMOSFET (double diffused metal oxide semiconductor field effect transistor) is obtained by forming a depletion region at a junction between the epilayer and a well region of opposite conductivity type as the epilayer. The depletion region is formed by applying a reverse bias voltage across the junction. At the breakdown voltage, the reverse-biased epilayer/well diode breaks down and significant current starts to flow. Current flows between the source and drain by an avalanche multiplication process while the gate and the source are shorted together.
  • [0024]
    The formation of depletion regions in a conventional trench MOSFET device can be described with reference to FIGS. 1(a) to 1(f). These figures show schematic cross-sectional views of a conventional vertical trench MOSFET device. Each cross-section shows a plurality of gate structures 45 at a major surface of a semiconductor substrate 29. The semiconductor substrate 29 comprises an N− epilayer 32 and a drain region 31. In FIG. 1(a), N+ source regions, P− wells, and P+ body regions are shown. In order to clearly illustrate the horizontal depletion effect, N+ source regions and P+ body regions are not shown in FIGS. 1(b) to 1(f), 2(a) to 2(f), and 3(a) to 3(f).
  • [0025]
    In this example, the N− epilayer 32 has a resistivity of about 5.0 ohm-cm and an epilayer dopant concentration, Nd(epi), of about 1×1015 cm−3. The thickness of the N− epilayer 32 is about 20 microns. The device also has an “effective” epilayer thickness (sometimes referred to as “effective epi”) of about 16.5 microns. The effective epilayer thickness is the thickness of the epilayer after taking into account any up diffusion of atoms from the N+ drain region 31 and the formation of regions such as doped regions (e.g., P− wells) in the semiconductor substrate 29. For example, the effective epilayer thickness can be substantially equal to the distance between the bottom of a P+ body or a P− well and the endpoint of any up-diffused donors in the N− epilayer 32 from the N+ substrate 31. The effective epilayer for the device may also include the drift region for the device.
  • [0026]
    Each of the FIGS. 1(a) to 1(f) also shows the maximum electric field established (“Emax”) as different reverse bias voltages are applied. As shown in the figures, as the reverse bias voltage is increased, Emax also increases. If Emax exceeds the critical electric field for a given dopant concentration, avalanche breakdown occurs. Consequently, Emax is desirably less than the critical electric field.
  • [0027]
    FIGS. 1(a) to 1(f) respectively show how the depletion region 50 expands as increasing reverse bias voltages of 0V, 10V, 50V, 100V, 200V, and 250V are applied to the conventional trench MOSFET device. As shown in the figures, as greater reverse bias voltages are applied, the depletion region 50 spreads “vertically” in a direction from the P-well/epilayer interface to the N+ drain region 31. This vertical growth of the depletion region forces the trade-off between lower RDS(on) and higher BVDSS in conventional trench MOSFET devices.
  • [0028]
    The present invention provides an improved MOSFET device wherein the depletion region initially spreads “horizontally” as higher reverse bias voltages are applied. In embodiments of the invention, a number of additional (and preferably deep) trenches are formed in the semiconductor substrate. These deep trenches are eventually used to form stripes that induce the formation of a horizontally spreading depletion region. The stripes comprise a material of the opposite type conductivity to the epilayer. For example, the stripes may comprise a P type material (e.g., a P, P+, or P− silicon) while the epilayer may comprise an N type material. Individual stripes may be present between adjacent gate structures and can extend from the major surface of the semiconductor substrate and into the epilayer. The stripes can also extend any suitable distance into the epilayer. For example, in some embodiments, the stripes extend all the way to the epilayer/drain region interface. The presence of the stripes allows the use of a lower resistance epilayer without exceeding the critical electric field. As will be explained in greater detail below, RDS(on) can be reduced without detrimentally affecting other MOSFET device characteristics such as the breakdown voltage.
  • [0029]
    FIGS. 2(a) to 2(f) illustrate an embodiment of the invention. These figures illustrate how a depletion region spreads as greater reverse bias voltages are applied. The gate bias voltages applied in the examples shown in FIGS. 2(a) to 2(f) are 0V, 1V, 2V, 10V, 200V, and 250V. Like the conventional trench MOSFET device shown in FIGS. 1(a) to 1(f), each of the cross-sections of FIGS. 2(a) to 2(f) include a plurality of trench gate structures 45 and a N-epilayer 32. The N− epilayer 32 is present in a semiconductor substrate 29.
  • [0030]
    However, in FIGS. 2(a) to 2(f), a plurality of trenches forming stripes 35 (e.g., P stripes) of the opposite conductivity type as the N− epilayer 32 are respectively disposed between adjacent gate structures 45. In this example, the stripes 35 comprise a P type material. As shown in FIGS. 2(a) to 2(c), as greater reverse bias voltages are applied, the depletion region 50 initially spreads “horizontally” away from the sides of the stripes 35. The regions between adjacent stripes 35 are quickly depleted of charge carriers as the depletion region 32 expands from the side-surfaces of adjacent stripes 35. After the regions between adjacent stripes 35 are depleted of charge carriers, the depletion region 50 spreads vertically in a direction from the ends of the stripes 35 towards the N+ drain region 31. The epilayer 32 in the embodiment is depleted of charge carriers much more quickly than when depletion initially occurs in a “vertical” manner (e.g., as shown in FIGS. 1(a) to 1(f)). As illustrated in FIG. 2(c) (reverse bias voltage=2V) and FIG. 1(e) (reverse bias voltage=200 V), the depletion region 50 is similar in area with significantly less applied voltage (2V compared to 200 V).
  • [0031]
    FIGS. 3(a) to 3(f) show cross sections of another MOSFET device according to another embodiment of the invention. In these figures, like elements are denoted by like numerals in prior figures. However, unlike the MOSFET devices described in prior figures, the epilayer 50 in the MOSFET device shown in FIGS. 3(a) to 3(f) has a resistivity of about 0.6 ohm-cm, a dopant concentration (Nd) of about 1×1016 cm−3, a thickness of about 16 microns, and an effective epilayer thickness of about 12.5 microns.
  • [0032]
    FIGS. 3(a) to 3(f) respectively show how the depletion region 50 changes at reverse bias voltages of 0V, 10V, 50V, 100V, 200V, and 250V. Like the MOSFET device embodiment shown in FIGS. 2(a) to 2(f), the depletion region 50 initially spreads “horizontally” as higher reverse bias voltages are applied. Also, in this example, the maximum electric field (Emax) at each of these applied reverse bias voltages does not exceed the critical field for avalanche breakdown for the stated dopant concentration. Consequently, a high breakdown voltage (e.g., 250 V) can be obtained while using a thinner and lower resistivity. The thinner and lower resistivity epilayer advantageously results in a lower resistance epilayer and thus, a reduced RDS(on) value. The dimensions and doping level in the stripes 35 are adjusted to balance the total charge in the stripes with the total charge in the epilayer depletion region 50.
  • [0033]
    As noted above, as the breakdown voltage ratings for MOSFET devices increase, the epilayer resistance becomes a significantly increasing component of the total specific RDS(on). For example, FIG. 4 shows a bar graph illustrating some components of RDS(on) for a number of N-channel MOSFET devices with different breakdown voltage ratings. Bar (a) represents the RDS(on) for a control N-channel 30 V MOSFET device at 500 A. Bars (b) to (f) refer to conventional trench N-channel MOSFET devices with respective breakdown voltages of 60, 80, 100, 150, and 200 V. As is clearly evident in FIG. 4, as the breakdown voltage increases, the epilayer resistance has a greater impact on RDS(on). For example, in the conventional 200 V N-channel MOSFET device example, the epilayer resistance constitutes over 90% of the total specific RDS(on). In contrast, in the 30 V N-channel MOSFET example, the epilayer resistance has a significantly lower impact on RDS(on).
  • [0034]
    In embodiments of the invention, the epilayer resistance can be lowered by incorporating trenched stripes in the epilayer. This reduces RDS(on) as compared to a similar conventional MOSFET device with a similar breakdown voltage rating. For example, bar (g) in FIG. 4 shows the improvement provided for a trench MOSFET device according to an exemplary embodiment of the invention. As shown, the epilayer resistance can be significantly reduced when using trenched stripes having the opposite conductivity of the epilayer in a MOSFET device. As shown at bar (g), the total specific RDS(on) for a 200 V trench N-channel MOSFET device is less than 1.4 milliohm-cm2. In contrast, for a conventional 200 V N-channel trench MOSFET without the stripes of the opposite conductivity, the total specific RDS(on) is about 7.5 milliohm-cm2. Accordingly, these exemplary embodiments of the invention can exhibit a greater than 5-fold reduction in RDS(on) than conventional trench MOSFET devices.
  • [0035]
    FIGS. 5 to 11 show graphs of reverse IV curves for MOSFET devices according to embodiments of the invention.
  • [0036]
    FIG. 5 is a graph showing reverse IV curves for conventional trench MOSFET devices and a MOSFET device according to an embodiment of the invention. FIG. 5 shows IV curves 500, 502 for two MOSFET devices without P− stripes. The first curve 500 is for a MOSFET device with an epilayer resistance of 0.8 milliohm-cm and an epilayer thickness of 15 microns. The second curve 502 is for a MOSFET device with an epilayer resistivity of 4.6 milliohm-cm and an epilayer thickness of 19.5 microns. As expected, the MOSFET device with the thicker epilayer and higher resistance has a higher breakdown voltage.
  • [0037]
    An IV curve 504 for an embodiment of the invention is also shown in FIG. 5. This exemplary embodiment has an epilayer resistance of about 0.8 ohm-cm, an epilayer thickness of about 15 microns and a P− stripe about 12 microns deep. As shown by the IV curve 504, this device embodiment has a relatively thin epilayer and a relatively low epilayer resistivity (and therefore a low RDS(on)). It also has a breakdown voltage approaching 220 V. The breakdown voltage is comparable to the breakdown voltage exhibited by a conventional MOSFET device having a thicker and more resistive epilayer.
  • [0038]
    FIG. 6 shows reverse IV curves for MOSFET devices according to embodiments of the invention. The curves show the effect of varying the P− stripe depth on BVDSS. In these devices, the epilayer has a resistance of about 0.8 ohm-cm and a thickness of about 13 microns. The P− stripe width is about 1.0 microns. The dopant concentration in the P− stripe is about 2.2×1016 cm−3. The P− stripe depth was varied at about 8, 10, and 12, microns. The IV curves for these variations show that the breakdown voltage increases as the depth of the P− stripes is increased.
  • [0039]
    FIG. 7 shows reverse IV curves for MOSFET devices according to embodiments of the invention. The curves show the effect of P− stripe width variations on BVDSS. In this example, the devices have an epilayer resistance of about 0.8 ohm-cm and a thickness of about 13 microns. The P− stripe depth is about 10 microns, and the dopant concentration in the P− stripe is about 2.2×1016 cm−3. IV curves for P− stripes with widths of about 0.8, 1.0, and 1.2 microns are shown. The IV curves show that the breakdown voltage is higher when the width of the P− stripes is equal to 1 micron.
  • [0040]
    Embodiments of the present invention can be applied to both trench and planar MOSFET technologies. However, trench MOSFET devices are preferred as they advantageously occupy less space than planar MOSFET devices. In either case, the breakdown voltage of the device may be from about 100 to about 400 volts in some embodiments. For illustrative purposes, a method of manufacturing a MOSFET device according to the present invention is described below in the context of a trenched gate process.
  • [0041]
    A detailed drawing of a power trench MOSFET device according to an embodiment of the invention is shown in FIG. 8(d). The power trench MOSFET device comprises a semiconductor substrate 29 having a drain region 31 and an N− epitaxial portion 32 proximate the drain region 31. The semiconductor substrate 29 may comprise any suitable semiconductor material including Si, GaAs, etc. The drift region for the MOSFET device may be present in the epitaxial portion 32 of the semiconductor substrate 29. A plurality of gate structures 45 are proximate the major surface 28 of the semiconductor substrate 29, and each gate structure 45 comprises a gate electrode 43 and a dielectric layer 44 on the gate electrode 43. A plurality of N+ source regions 36 are formed in the semiconductor substrate 29. Each N+ source region 36 is adjacent to one of the gate structures 45 and is formed in a plurality of P− well regions 34, which are also formed in the semiconductor substrate 29. Each P− well region 34 is disposed adjacent to one of the gate structures 45. A contact 41 for the source regions 36 is present on the major surface 28 of the semiconductor substrate 29. The contact 41 may comprise a metal such as aluminum. For purposes of clarity, other components which may be present in a MOSFET device (e.g., a passivation layer) may not be shown in FIG. 8(d).
  • [0042]
    In FIG. 8(d), a trenched P− stripe 35 is present in the semiconductor substrate 29. A plurality of P− stripes 35 may be respectively disposed between adjacent gate structures 45 when the gate structures 45 form an array of gate structures 45. The P− stripe 35 shown in FIG. 8(d) is disposed between adjacent gate structures 45. As shown, the P− stripe 35 shown in the figure is generally vertical and is oriented generally perpendicular to the orientation of the semiconductor substrate 29. The P− stripe 35 extends past the gate structures 45 and may penetrate most of the N− epitaxial portion 32. The N− epitaxial portion 32 in this embodiment surrounds the bottom and sides of the P− stripe 35. The dopant concentration at the sides and below the P− stripe 35 may be similar in this embodiment. Preferably, the P− stripe 35 has generally parallel sidewalls and a generally flat bottom. If the sidewalls are generally parallel, thin P− stripes 35 can be present between adjacent gate structures 45. The pitch between gate structures 45 can be minimized consequently resulting in MOSFET arrays of reduced size. In exemplary embodiments of the invention, the gate structure 45 (or gate electrode) pitch may be less than about 10 microns (e.g., between about 4 to about 6 microns). The width of the P− stripes 35 may be less than about 2 or 3 microns (e.g., between about 1 and about 2 microns).
  • [0043]
    The stripe trenches in embodiments of the invention are filled or lined with a material of the opposite doping to the epitaxial portion in the semiconductor substrate. An embodiment of this type is shown in FIG. 8(e) and is described in greater detail below. If the stripe is lined with a material of the opposite conductivity type as the epitaxial portion, the stripe may comprise an inner dielectric portion and an outer semiconductor layer of the opposite conductivity type as the epitaxial portion. For example, the inner dielectric portion may comprise silicon oxide or air while the outer semiconductor layer may comprise P or N type epitaxial silicon.
  • [0044]
    The presence of the doped stripes may also be used as a heavy body to improve the ruggedness of the formed device. For example, like the presence of a P type heavy body in the epilayer, the presence of P− stripes penetrating the epilayer is believed to stabilize voltage variations in the device, thus increasing the device's reliability.
  • [0045]
    Suitable methods for forming the inventive power trench MOSFET devices can be described with reference to FIGS. 8(a) to 8(d).
  • [0046]
    With reference to FIG. 8(a), a structure including a semiconductor substrate 29 is provided. The semiconductor substrate 29 may comprise an N+ drain region 31 and an N-epitaxial portion 32. Gate trenches 30 are formed proximate a major surface 28 of the semiconductor substrate 29. These gate trenches 30 may be formed by using, for example, anisotropic etching methods well known in the art. After the gate trenches 30 are formed, gate structures 45 are formed within the gate trenches 30 using methods well known in the art. Each gate structure 45 comprises a dielectric layer 44 and a gate electrode 43. The gate electrode 43 may comprise polysilicon and the dielectric layer 44 may comprise silicon dioxide.
  • [0047]
    Source regions, well regions, and other structures may also be formed in the semiconductor substrate 29 after or before forming the gate structures 45. With reference to FIG. 8(b), P− well regions 34 are formed in the semiconductor substrate 29 and then N+ source regions 36 are formed in the semiconductor substrate 29. Conventional ion implantation or conventional diffusion processes may be used to form these regions. In this example, these doped regions are formed after the formation of the gate structures 45.
  • [0048]
    Additional details regarding the formation of well regions, gate structures, source regions, and heavy bodies are present in U.S. patent application Ser. No. 08/970,221 entitled “Field Effect Transistor and Method of Its Manufacture”, by Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, and Dean Edward Probst. This application is assigned to the same assignee as the assignee of the present application and the application is herein incorporated by reference in its entirety for all purposes.
  • [0049]
    In preferred embodiments, after the source regions, well regions, and/or gate structures are formed, one or more stripe trenches 30 are formed in the semiconductor substrate 29. For example, after the P− well regions 34, the N+ source regions 36, and the gate structures 45 are formed, the stripe trench 30 shown in FIG. 8(c) may be formed, e.g., by an anisotropic etching process. The formed stripe trench 30 extends from the major surface 28 of the semiconductor substrate 29. It may extend any suitable distance past the gate structures 45 to the interface between the epitaxial portion 32 and the drain region 31. Preferably, the stripe trench 30 (and also the stripe material disposed therein) terminates at a depth which is between half the thickness of the N− epitaxial portion 32 and the full thickness of the epitaxial portion 32. For example, the stripe trench 30 may extend to the interface between the epitaxial portion 32 and the drain region 31.
  • [0050]
    After the stripe trench 30 is formed, as shown in FIG. 8(d), a stripe 35 is formed in the stripe trench 30. The stripe 35 comprises a material of the second conductivity type. In embodiments of the invention, the material of the second conductivity type is an epitaxial material such as epitaxial P type silicon (e.g., P, P+, P− silicon). The stripe trenches 30 may be filled using any suitable method including a selective epitaxial growth (SEG) process. For example, the trenches 30 may be filled with epitaxial silicon with doping occurring in-situ.
  • [0051]
    The material of the second conductivity type may completely fill the stripe trench 30 as shown in FIG. 8(d) or may line the stripe trench 35 as shown in FIG. 8(e). In FIG. 8(e), like numerals designate like elements as in FIG. 8(d). However, in this embodiment, the stripe 35 comprises a P− layer 35(a) and an inner dielectric material 35(b). The P− layer 35(a) may be deposited in the formed stripe trench first, and then the dielectric material 35(b) may be deposited to fill the enclosure formed by the P− layer 35(a). Alternatively, the inner dielectric material may be formed by oxidizing the P− layer 35(a). The dielectric material 35(b) may comprise a material such as silicon dioxide or air.
  • [0052]
    Other suitable methods which can be used to form doped epitaxial stripes of material in a trench are described in U.S. patent application Ser. No. 09/586,720 entitled “Method of Manufacturing A Trench MOSFET Using Selective Growth Epitaxy”, by Gordon Madsen and Joelle Sharp. This application is assigned to the same assignee as the present invention and is incorporated by reference herein in its entirety for all purposes.
  • [0053]
    As noted, the stripe trench 30 and the stripes 35 of a second conductivity type are preferably formed after at least one of the source regions 36, the gate structures 45, and the well regions 34 are formed. By forming the stripes 35 after the formation of these device elements, the stripes 35 are not subjected to the high temperature processing used to form the gate structures 45 or the P− well regions 34. For example, the high temperature processing (e.g., ion implantation, high temperature drives) used to form the P− well regions can last as long as 1 to 3 hours at high temperatures (e.g., greater than 1100° C.). The formation of the P− stripes 35 in the semiconductor substrate 29, on the other hand, does not detrimentally affect previously formed gate structures 45, P− well regions 34, or the N+ source regions 36. Forming these device elements before forming the P− stripes 35 reduces the likelihood that the P− stripes 35 in the epilayer will diffuse and lose their shape due to extended high temperature processing. If this occurs, the width of the P− stripes 35 may not be uniform down the P− stripe 35 and may decrease the effectiveness of the formed device. For example, dopant from a laterally enlarged P− stripe 35 could diffuse into the channel region of the MOSFET device thereby influencing the threshold voltage characteristics of the MOSFET device. Moreover, wider P− stripes can result in a larger gate structure 45 pitch, thus increasing the size of a corresponding array of gate structures 45.
  • [0054]
    After the P− stripes 35 are formed, additional layers of material may be deposited. Additional layers may include a metal contact layer 41 and a passivation layer (not shown). These additional layers may be formed by any suitable method known in the art.
  • [0055]
    Although a number of specific embodiments are shown and described, embodiments of the invention are not limited thereto. For example, embodiments of the invention have been described with reference to N type semiconductors, P− stripes, etc. It is understood that the invention is not limited thereto and that the doping polarities of the structures shown and described could be reversed. Also, although P− stripes are mentioned in detail, it is understood that the stripes used in embodiments of the invention may be P or N type. The stripes or other device elements may also have any suitable acceptor or donor concentration (e.g., +, ++, −, −−, etc.).
  • [0056]
    The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed. Moreover, any one or more features of any embodiment of the invention may be combined with any one or more other features of any other embodiment of the invention, without departing from the scope of the invention.

Claims (26)

  1. 1. A field effect transistor comprising:
    a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;
    a well region of a second conductivity type over the semiconductor region;
    a source region of the first conductivity type in an upper portion of the well region;
    a gate trench adjacent to the source region, the gate trench extending through the well region and terminating within an upper half of the semiconductor region; and
    a stripe trench extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, the stripe trench being filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
  2. 2. The field effect transistor of claim 1 wherein the depth at which the trip trench terminates is substantially near the bottom surface of the semiconductor region.
  3. 3. The field effect transistor of claim 2 wherein the gate trench terminates at a depth substantially near an interface between the semiconductor region and the well region.
  4. 4. The field effect transistor of claim 1 wherein the gate trench comprises a gate dielectric lining the trench sidewalls and a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap the source region along the vertical dimension.
  5. 5. The field effect transistor of claim 1 wherein the semiconductor region is an epitaxial layer extending over a substrate.
  6. 6. The field effect transistor of claim 1 wherein the stripe trench extends substantially deeper in the semiconductor region than does the gate trench.
  7. 7. The field effect transistor of claim 1 wherein the stripe trench terminates within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
  8. 8. The field effect transistor of claim 1 wherein the stripe trench is completely filled with the semiconductor material of the second conductivity type.
  9. 9. A field effect transistor comprising:
    a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;
    a well region of a second conductivity type over the semiconductor region;
    a plurality of gate trenches each extending through the well region and terminating within an upper half of the semiconductor region;
    a plurality of source regions of the first conductivity type in an upper portion of the well region, the plurality of source regions flanking the sides of the plurality of gate trenches; and
    a plurality of stripe trenches each extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, each stripe trench being filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
  10. 10. The field effect transistor of claim 9 wherein the depth at which the plurality of stripe trenches terminate is substantially near a bottom surface of the semiconductor region.
  11. 11. The field effect transistor of claim 10 wherein the plurality of gate trenches terminate at a depth substantially near an interface between the semiconductor region and the well region.
  12. 12. The field effect transistor of claim 9 wherein each of the plurality of gate trenches comprises:
    a gate dielectric lining the trench sidewalls; and
    a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap source regions flanking each side of the gate trench.
  13. 13. The field effect transistor of claim 9 wherein the semiconductor region is an epitaxial layer extending over a substrate.
  14. 14. The field effect transistor of claim 9 wherein the plurality of stripe trenches extend substantially deeper into the semiconductor region than do the gate trenches.
  15. 15. The field effect transistor of claim 9 wherein the plurality of stripe trenches terminate within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
  16. 16. The field effect transistor of claim 9 wherein the plurality of stripe trenches are spaced from one another and extend to such depth within the semiconductor region that upon applying a reverse voltage across a junction between the well region and the semiconductor region a substantial portion of the entire semiconductor region, including those portions of the semiconductor region between adjacent stripe trenches, becomes depleted of charge carriers.
  17. 17. The field effect transistor of claim 10 wherein each of the plurality of stripe trenches is completely filled with the semiconductor material of the second conductivity type.
  18. 18. A method of forming a field effect transistor comprising:
    forming a well region in a semiconductor region of a first conductivity type, the well region being of a second conductivity type and having an upper surface and a lower surface;
    forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region;
    forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below that of the plurality of gate trenches, the plurality of stripe trenches being laterally spaced from one or more of the plurality of gate trenches; and
    at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.
  19. 19. The method of claim 18 wherein the plurality of stripe trenches extend into the semiconductor region parallel to a current flow through the semiconductor region when the field effect transistor is in an on state.
  20. 20. The method of claim 18 wherein the plurality of stripe trenches are completely filled with the semiconductor material of the second conductivity type using selective epitaxial growth.
  21. 21. The method of claim 18 wherein the semiconductor material of the second conductivity type lines the sidewalls of the plurality of stripe trenches, the method further comprising:
    forming a dielectric material within the plurality of stripe trenches such that each stripe trench becomes substantially completely filled with the combination of the semiconductor material of the second conductivity type and the dielectric material.
  22. 22. The method of claim 18 wherein the plurality of stripe trenches are formed after forming the plurality of gate trenches and the well region.
  23. 23. The method of claim 18 wherein the semiconductor region is an epitaxial layer of the first conductivity type in which the well region is formed, the epitaxial layer having a thickness defined by the spacing between an upper surface and a lower surface of the epitaxial layer, wherein the plurality of stripe trenches extend into the epitaxial layer and terminate at a depth between one-half the thickness of the epitaxial layer and the lower surface of the epitaxial layer.
  24. 24. The method of claim 18 wherein the semiconductor region has a thickness defined by the vertical distance between an upper surface and a lower surface of the semiconductor region, the plurality of stripe trenches terminating within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
  25. 25. The method of claim 20 further comprising forming source regions in the well region.
  26. 26. The method of claim 25 wherein the semiconductor region comprises an epitaxial layer and a substrate both of the first conductivity type, the substrate forming a drain contact region, the method further comprising:
    forming the epitaxial layer over the substrate, the well region being formed in the epitaxial layer, and the plurality of stripe trenches and gate trenches extending into and terminating within the epitaxial layer.
US10934969 2001-01-30 2004-09-03 Structure and method of forming a dual-trench field effect transistor Abandoned US20050029618A1 (en)

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US09774780 US6713813B2 (en) 2001-01-30 2001-01-30 Field effect transistor having a lateral depletion structure
US10741464 US6818513B2 (en) 2001-01-30 2003-12-18 Method of forming a field effect transistor having a lateral depletion structure
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008106235A1 (en) * 2007-03-01 2008-09-04 International Rectifier Corporation Trench mosgated device with deep trench between gate trenches
US20110014764A1 (en) * 2001-01-30 2011-01-20 Marchant Bruce D Method of forming a dual-trench field effect transistor
CN102751190A (en) * 2011-04-22 2012-10-24 科轩微电子股份有限公司 Channel type power metal oxide semi-conductor structure with fast switching capacity and manufacture method

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7019358B2 (en) * 2003-07-31 2006-03-28 Clare, Inc. High voltage semiconductor device having an increased breakdown voltage relative to its on-resistance
US7268395B2 (en) * 2004-06-04 2007-09-11 International Rectifier Corporation Deep trench super switch device
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
KR101279574B1 (en) * 2006-11-15 2013-06-27 페어차일드코리아반도체 주식회사 High voltage semiconductor device and method of fabricating the same
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US7880224B2 (en) * 2008-01-25 2011-02-01 Infineon Technologies Austria Ag Semiconductor component having discontinuous drift zone control dielectric arranged between drift zone and drift control zone and a method of making the same
US9508805B2 (en) 2008-12-31 2016-11-29 Alpha And Omega Semiconductor Incorporated Termination design for nanotube MOSFET
US7943989B2 (en) * 2008-12-31 2011-05-17 Alpha And Omega Semiconductor Incorporated Nano-tube MOSFET technology and devices
US8299494B2 (en) * 2009-06-12 2012-10-30 Alpha & Omega Semiconductor, Inc. Nanotube semiconductor devices
US7910486B2 (en) * 2009-06-12 2011-03-22 Alpha & Omega Semiconductor, Inc. Method for forming nanotube semiconductor devices
US8129778B2 (en) * 2009-12-02 2012-03-06 Fairchild Semiconductor Corporation Semiconductor devices and methods for making the same
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) * 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
CN103151268B (en) * 2013-03-21 2016-02-03 矽力杰半导体技术(杭州)有限公司 A vertical double diffusion MOSFET and a manufacturing process
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
US9484404B2 (en) 2014-01-29 2016-11-01 Stmicroelectronics S.R.L. Electronic device of vertical MOS type with termination trenches having variable depth

Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3497777A (en) * 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) * 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US3660697A (en) * 1970-02-16 1972-05-02 Bell Telephone Labor Inc Monolithic semiconductor apparatus adapted for sequential charge transfer
US4003072A (en) * 1972-04-20 1977-01-11 Sony Corporation Semiconductor device with high voltage breakdown resistance
US4326332A (en) * 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4445202A (en) * 1980-11-12 1984-04-24 International Business Machines Corporation Electrically switchable permanent storage
US4579621A (en) * 1983-07-08 1986-04-01 Mitsubishi Denki Kabushiki Kaisha Selective epitaxial growth method
US4636281A (en) * 1984-06-14 1987-01-13 Commissariat A L'energie Atomique Process for the autopositioning of a local field oxide with respect to an insulating trench
US4638344A (en) * 1979-10-09 1987-01-20 Cardwell Jr Walter T Junction field-effect transistor controlled by merged depletion regions
US4639761A (en) * 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
US4746630A (en) * 1986-09-17 1988-05-24 Hewlett-Packard Company Method for producing recessed field oxide with improved sidewall characteristics
US4801986A (en) * 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4821095A (en) * 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US4823176A (en) * 1987-04-03 1989-04-18 General Electric Company Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
US4990463A (en) * 1988-07-05 1991-02-05 Kabushiki Kaisha Toshiba Method of manufacturing capacitor
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
US5079608A (en) * 1990-11-06 1992-01-07 Harris Corporation Power MOSFET transistor circuit with active clamp
US5105243A (en) * 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US5111253A (en) * 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5294824A (en) * 1992-07-31 1994-03-15 Motorola, Inc. High voltage transistor having reduced on-resistance
US5298761A (en) * 1991-06-17 1994-03-29 Nikon Corporation Method and apparatus for exposure process
US5300447A (en) * 1992-09-29 1994-04-05 Texas Instruments Incorporated Method of manufacturing a minimum scaled transistor
US5389815A (en) * 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5418376A (en) * 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5592005A (en) * 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5595927A (en) * 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5605852A (en) * 1992-07-23 1997-02-25 Siliconix Incorporated Method for fabricating high voltage transistor having trenched termination
US5616945A (en) * 1995-10-13 1997-04-01 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US5623152A (en) * 1995-02-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
US5629543A (en) * 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US5705409A (en) * 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5710072A (en) * 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5877528A (en) * 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US5879971A (en) * 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US5895952A (en) * 1994-12-30 1999-04-20 Siliconix Incorporated Trench MOSFET with multi-resistivity drain to provide low on-resistance
US5895951A (en) * 1996-04-05 1999-04-20 Megamos Corporation MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
US5897343A (en) * 1998-03-30 1999-04-27 Motorola, Inc. Method of making a power switching trench MOSFET having aligned source regions
US5900663A (en) * 1998-02-07 1999-05-04 Xemod, Inc. Quasi-mesh gate structure for lateral RF MOS devices
US5906680A (en) * 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
US6015727A (en) * 1998-06-08 2000-01-18 Wanlass; Frank M. Damascene formation of borderless contact MOS transistors
US6020250A (en) * 1994-08-11 2000-02-01 International Business Machines Corporation Stacked devices
US6034415A (en) * 1998-02-07 2000-03-07 Xemod, Inc. Lateral RF MOS device having a combined source structure
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US6037628A (en) * 1997-06-30 2000-03-14 Intersil Corporation Semiconductor structures with trench contacts
US6040600A (en) * 1997-02-10 2000-03-21 Mitsubishi Denki Kabushiki Kaisha Trenched high breakdown voltage semiconductor device
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6049108A (en) * 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US6064088A (en) * 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
US6063678A (en) * 1998-05-04 2000-05-16 Xemod, Inc. Fabrication of lateral RF MOS devices with enhanced RF properties
US6066878A (en) * 1997-11-10 2000-05-23 Intersil Corporation High voltage semiconductor structure
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
US6168996A (en) * 2001-01-02
US6168996B1 (en) * 1997-08-28 2001-01-02 Hitachi, Ltd. Method of fabricating semiconductor device
US6171935B1 (en) * 1998-05-06 2001-01-09 Siemens Aktiengesellschaft Process for producing an epitaxial layer with laterally varying doping
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US6174785B1 (en) * 1998-04-09 2001-01-16 Micron Technology, Inc. Method of forming trench isolation region for semiconductor device
US6184545B1 (en) * 1997-09-12 2001-02-06 Infineon Technologies Ag Semiconductor component with metal-semiconductor junction with low reverse current
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US6188105B1 (en) * 1999-04-01 2001-02-13 Intersil Corporation High density MOS-gated power device and process for forming same
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6194741B1 (en) * 1998-11-03 2001-02-27 International Rectifier Corp. MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6201279B1 (en) * 1998-10-22 2001-03-13 Infineon Technologies Ag Semiconductor component having a small forward voltage and high blocking ability
US6204097B1 (en) * 1999-03-01 2001-03-20 Semiconductor Components Industries, Llc Semiconductor device and method of manufacture
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6222233B1 (en) * 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
US6225649B1 (en) * 1998-01-22 2001-05-01 Mitsubishi Denki Kabushiki Kaisha Insulated-gate bipolar semiconductor device
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
US20020009832A1 (en) * 2000-06-02 2002-01-24 Blanchard Richard A. Method of fabricating high voltage power mosfet having low on-resistance
US20020014658A1 (en) * 2000-06-02 2002-02-07 Blanchard Richard A. High voltage power mosfet having low on-resistance
US6346469B1 (en) * 2000-01-03 2002-02-12 Motorola, Inc. Semiconductor device and a process for forming the semiconductor device
US6346464B1 (en) * 1999-06-28 2002-02-12 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US6351018B1 (en) * 1999-02-26 2002-02-26 Fairchild Semiconductor Corporation Monolithically integrated trench MOSFET and Schottky diode
US6353252B1 (en) * 1999-07-29 2002-03-05 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device having trenched film connected to electrodes
US6359308B1 (en) * 1999-07-22 2002-03-19 U.S. Philips Corporation Cellular trench-gate field-effect transistors
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6362112B1 (en) * 2000-11-08 2002-03-26 Fabtech, Inc. Single step etched moat
US6365930B1 (en) * 1999-06-03 2002-04-02 Stmicroelectronics S.R.L. Edge termination of semiconductor devices for high voltages with resistive voltage divider
US6368920B1 (en) * 1996-04-10 2002-04-09 Fairchild Semiconductor Corporation Trench MOS gate device
US6368921B1 (en) * 1999-09-28 2002-04-09 U.S. Philips Corporation Manufacture of trench-gate semiconductor devices
US6376878B1 (en) * 2000-02-11 2002-04-23 Fairchild Semiconductor Corporation MOS-gated devices with alternating zones of conductivity
US6376314B1 (en) * 1997-11-07 2002-04-23 Zetex Plc. Method of semiconductor device fabrication
US6376890B1 (en) * 1998-04-08 2002-04-23 Siemens Aktiengesellschaft High-voltage edge termination for planar structures
US20030060013A1 (en) * 1999-09-24 2003-03-27 Bruce D. Marchant Method of manufacturing trench field effect transistors with trenched heavy body
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure

Family Cites Families (175)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3412297A (en) 1965-12-16 1968-11-19 United Aircraft Corp Mos field-effect transistor with a onemicron vertical channel
US4337474A (en) 1978-08-31 1982-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4698653A (en) * 1979-10-09 1987-10-06 Cardwell Jr Walter T Semiconductor devices controlled by depletion regions
US4345265A (en) 1980-04-14 1982-08-17 Supertex, Inc. MOS Power transistor with improved high-voltage capability
US4868624A (en) 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4300150A (en) 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
GB2089119A (en) * 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
US4974059A (en) 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US4774556A (en) 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
US5283201A (en) * 1988-05-17 1994-02-01 Advanced Power Technology, Inc. High density power device fabrication process
US5262336A (en) 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US5034785A (en) 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
US4716126A (en) 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
JP2577330B2 (en) 1986-12-11 1997-01-29 三菱電機株式会社 Sided gate - production method DOO static induction thyristor
US5164325A (en) 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
EP0332822A1 (en) 1988-02-22 1989-09-20 Asea Brown Boveri Ag Field-effect-controlled bipolar power semiconductor device, and method of making the same
US4967245A (en) 1988-03-14 1990-10-30 Siliconix Incorporated Trench power MOSFET device
US5142640A (en) 1988-06-02 1992-08-25 Seiko Epson Corporation Trench gate metal oxide semiconductor field effect transistor
US4853345A (en) 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
US5268311A (en) 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5248894A (en) 1989-10-03 1993-09-28 Harris Corporation Self-aligned channel stop for trench-isolated island
US5071782A (en) 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
CN1019720B (en) * 1991-03-19 1992-12-30 电子科技大学 Power semiconductor device
US5164802A (en) 1991-03-20 1992-11-17 Harris Corporation Power vdmosfet with schottky on lightly doped drain of lateral driver fet
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
KR940006702B1 (en) 1991-06-14 1994-07-25 문정환 Manufacturing method of mosfet
JP2570022B2 (en) 1991-09-20 1997-01-08 株式会社日立製作所 Method for producing a constant voltage diode and the power converter and the voltage regulator diode using the same
JPH0613627A (en) 1991-10-08 1994-01-21 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JPH05304297A (en) 1992-01-29 1993-11-16 Nec Corp Semiconductor power device and manufacture thereof
US5315142A (en) 1992-03-23 1994-05-24 International Business Machines Corporation High performance trench EEPROM cell
JP2904635B2 (en) 1992-03-30 1999-06-14 株式会社東芝 Semiconductor device and manufacturing method thereof
US5554862A (en) 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
US5640034A (en) 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
US5233215A (en) 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
US5558313A (en) 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
GB9216599D0 (en) * 1992-08-05 1992-09-16 Philips Electronics Uk Ltd A semiconductor device comprising a vertical insulated gate field effect device and a method of manufacturing such a device
JPH06163907A (en) 1992-11-20 1994-06-10 Hitachi Ltd Voltage drive semiconductor device
US5326711A (en) * 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
DE4300806C1 (en) 1993-01-14 1993-12-23 Siemens Ag Vertical MOS transistor prodn. - with reduced trench spacing, without parasitic bipolar effects
US5341011A (en) 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor
DE4309764C2 (en) * 1993-03-25 1997-01-30 Siemens Ag Power MOSFET
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
BE1007283A3 (en) * 1993-07-12 1995-05-09 Philips Electronics Nv Semiconductor device with most with an extended drain area high voltage.
JPH07122749A (en) 1993-09-01 1995-05-12 Toshiba Corp Semiconductor device and its manufacture
JP3400846B2 (en) 1994-01-20 2003-04-28 三菱電機株式会社 Semiconductor device having a trench structure
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5434435A (en) 1994-05-04 1995-07-18 North Carolina State University Trench gate lateral MOSFET
US5424231A (en) 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
DE69525003D1 (en) 1994-08-15 2002-02-21 Siliconix Inc A method of manufacturing a DMOS transistor with grave structure using seven masks
US5581100A (en) * 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
US5583065A (en) * 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
JPH08204179A (en) 1995-01-26 1996-08-09 Fuji Electric Co Ltd Silicon carbide trench mosfet
US5670803A (en) 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
DE69602114D1 (en) 1995-02-10 1999-05-27 Siliconix Inc Trench field effect transistor with PN depletion layer barrier
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US6096608A (en) 1997-06-30 2000-08-01 Siliconix Incorporated Bidirectional trench gated power mosfet with submerged body bus extending underneath gate trench
US5648670A (en) 1995-06-07 1997-07-15 Sgs-Thomson Microelectronics, Inc. Trench MOS-gated device with a minimum number of masks
US5689128A (en) 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
DE19636302C2 (en) 1995-09-06 1998-08-20 Denso Corp Silicon carbide semiconductor device and methods for making
US5973367A (en) 1995-10-13 1999-10-26 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US5949124A (en) 1995-10-31 1999-09-07 Motorola, Inc. Edge termination structure
KR0159075B1 (en) 1995-11-11 1998-12-01 김광호 Trench dmos device and a method of fabricating the same
US5780343A (en) * 1995-12-20 1998-07-14 National Semiconductor Corporation Method of producing high quality silicon surface for selective epitaxial growth of silicon
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US6097063A (en) * 1996-01-22 2000-08-01 Fuji Electric Co., Ltd. Semiconductor device having a plurality of parallel drift regions
US6084268A (en) * 1996-03-05 2000-07-04 Semiconductor Components Industries, Llc Power MOSFET device having low on-resistance and method
DE19611045C1 (en) * 1996-03-20 1997-05-22 Siemens Ag Field effect transistor e.g. vertical MOS type
JP2000515684A (en) 1996-07-19 2000-11-21 シリコニックス・インコーポレイテッド High density trench dmos transistor having a trench bottom implanted region
US5808340A (en) 1996-09-18 1998-09-15 Advanced Micro Devices, Inc. Short channel self aligned VMOS field effect transistor
US5972741A (en) * 1996-10-31 1999-10-26 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device
KR100233832B1 (en) 1996-12-14 1999-12-01 정선종 Transistor of semiconductor device and method for manufacturing the same
JPH10256550A (en) 1997-01-09 1998-09-25 Toshiba Corp Semiconductor device
JP2001503177A (en) 1998-02-16 2001-03-06 エーセーテー,アイ コントロール テクニーク アクティエボラーグ Controlled photoelectric output interface visually
KR100225409B1 (en) 1997-03-27 1999-10-15 김덕중 Trench dmos and method of manufacturing the same
US6163052A (en) * 1997-04-04 2000-12-19 Advanced Micro Devices, Inc. Trench-gated vertical combination JFET and MOSFET devices
US6281547B1 (en) * 1997-05-08 2001-08-28 Megamos Corporation Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask
JPH113936A (en) 1997-06-13 1999-01-06 Nec Corp Manufacture of semiconductor device
JP3618517B2 (en) 1997-06-18 2005-02-09 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US6110799A (en) 1997-06-30 2000-08-29 Intersil Corporation Trench contact process
DE19731495C2 (en) * 1997-07-22 1999-05-20 Siemens Ag Field effect-controllable bipolar transistor and method for its preparation
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
DE19743342C2 (en) * 1997-09-30 2002-02-28 Infineon Technologies Ag Field effect transistor high packing density and process for its preparation
US5776813A (en) 1997-10-06 1998-07-07 Industrial Technology Research Institute Process to manufacture a vertical gate-enhanced bipolar transistor
KR100249505B1 (en) 1997-10-28 2000-03-15 정선종 Fabrication method of laterally double diffused mosfets
US6005271A (en) * 1997-11-05 1999-12-21 Magepower Semiconductor Corp. Semiconductor cell array with high packing density
US5943581A (en) 1997-11-05 1999-08-24 Vanguard International Semiconductor Corporation Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6191039B1 (en) 1997-11-15 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of CMP of polysilicon
US6180978B1 (en) * 1997-12-30 2001-01-30 Texas Instruments Incorporated Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions
JPH11204782A (en) * 1998-01-08 1999-07-30 Toshiba Corp Semiconductor device and manufacture therefor
DE19808348C1 (en) * 1998-02-27 1999-06-24 Siemens Ag Semiconductor component, such as field-effect power semiconductor device
US6137152A (en) 1998-04-22 2000-10-24 Texas Instruments - Acer Incorporated Planarized deep-shallow trench isolation for CMOS/bipolar devices
US6150697A (en) 1998-04-30 2000-11-21 Denso Corporation Semiconductor apparatus having high withstand voltage
US6303969B1 (en) 1998-05-01 2001-10-16 Allen Tan Schottky diode with dielectric trench
US6104054A (en) 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
DE19828191C1 (en) * 1998-06-24 1999-07-29 Siemens Ag Lateral high voltage transistor
KR100372103B1 (en) 1998-06-30 2003-03-31 주식회사 하이닉스반도체 Device isolation method of a semiconductor device
US6156611A (en) * 1998-07-20 2000-12-05 Motorola, Inc. Method of fabricating vertical FET with sidewall gate electrode
DE69818289T2 (en) 1998-07-23 2004-07-01 Mitsubishi Denki K.K. A process for producing a semiconductor device and semiconductor device characterized generatable
JP4253374B2 (en) 1998-07-24 2009-04-08 千住金属工業株式会社 Soldering method and jet solder bath of the printed circuit board
JP3988262B2 (en) 1998-07-24 2007-10-10 富士電機デバイステクノロジー株式会社 Vertical superjunction semiconductor device and a manufacturing method thereof
DE19839970C2 (en) 1998-09-02 2000-11-02 Siemens Ag Edge structure and the drift region for a semiconductor device, and methods for their preparation
DE19841754A1 (en) * 1998-09-11 2000-03-30 Siemens Ag Switching transistor with reduced switching losses
DE19843959B4 (en) 1998-09-24 2004-02-12 Infineon Technologies Ag A method of manufacturing a semiconductor device having a blocking pn junction
JP3382163B2 (en) * 1998-10-07 2003-03-04 株式会社東芝 The power semiconductor device
US7462910B1 (en) 1998-10-14 2008-12-09 International Rectifier Corporation P-channel trench MOSFET structure
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
JP3951522B2 (en) 1998-11-11 2007-08-01 富士電機デバイステクノロジー株式会社 Superjunction semiconductor device
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
JP3799888B2 (en) 1998-11-12 2006-07-19 富士電機デバイステクノロジー株式会社 Super junction semiconductor device and a manufacturing method thereof
US6156606A (en) 1998-11-17 2000-12-05 Siemens Aktiengesellschaft Method of forming a trench capacitor using a rutile dielectric material
JP2000156978A (en) 1998-11-17 2000-06-06 Fuji Electric Co Ltd Soft switching circuit
US6084264A (en) * 1998-11-25 2000-07-04 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics
GB9826041D0 (en) 1998-11-28 1999-01-20 Koninkl Philips Electronics Nv Trench-gate semiconductor devices and their manufacture
GB9826291D0 (en) * 1998-12-02 1999-01-20 Koninkl Philips Electronics Nv Field-effect semi-conductor devices
US6452230B1 (en) 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
JP3751463B2 (en) 1999-03-23 2006-03-01 株式会社東芝 High-voltage semiconductor device
DE19913375B4 (en) 1999-03-24 2009-03-26 Infineon Technologies Ag A method for manufacturing a MOS transistor structure
JP3417336B2 (en) 1999-03-25 2003-06-16 関西日本電気株式会社 An insulated gate semiconductor device and a manufacturing method thereof
US6316806B1 (en) * 1999-03-31 2001-11-13 Fairfield Semiconductor Corporation Trench transistor with a self-aligned source
WO2000068997A9 (en) 1999-05-06 2002-07-18 C P Clare Corp Mosfet with field reducing trenches in body region
WO2000068998A1 (en) 1999-05-06 2000-11-16 C.P. Clare Corporation High voltage mosfet structures
US6313482B1 (en) * 1999-05-17 2001-11-06 North Carolina State University Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein
US6433385B1 (en) 1999-05-19 2002-08-13 Fairchild Semiconductor Corporation MOS-gated power device having segmented trench and extended doping zone and process for forming same
US6291298B1 (en) 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
KR100829052B1 (en) * 1999-06-03 2008-05-19 제네럴 세미컨덕터, 인코포레이티드 A power mosfet, a method of forming a power mosfet, and another power mosfet made by the method
US6274905B1 (en) * 1999-06-30 2001-08-14 Fairchild Semiconductor Corporation Trench structure substantially filled with high-conductivity material
GB9916370D0 (en) 1999-07-14 1999-09-15 Koninkl Philips Electronics Nv Manufacture of semiconductor devices and material
GB9916520D0 (en) 1999-07-15 1999-09-15 Koninkl Philips Electronics Nv Manufacture of semiconductor devices and material
US6265269B1 (en) 1999-08-04 2001-07-24 Mosel Vitelic Inc. Method for fabricating a concave bottom oxide in a trench
JP4774580B2 (en) 1999-08-23 2011-09-14 富士電機株式会社 Superjunction semiconductor device
US6346489B1 (en) * 1999-09-02 2002-02-12 Applied Materials, Inc. Precleaning process for metal plug that minimizes damage to low-κ dielectric
US6228727B1 (en) 1999-09-27 2001-05-08 Chartered Semiconductor Manufacturing, Ltd. Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
JP3507732B2 (en) 1999-09-30 2004-03-15 株式会社東芝 Semiconductor device
US6271552B1 (en) 1999-10-04 2001-08-07 Xemod, Inc Lateral RF MOS device with improved breakdown voltage
US6365482B1 (en) * 1999-10-28 2002-04-02 Analog Devices, Inc. I.C. thin film resistor stabilization method
JP4450122B2 (en) 1999-11-17 2010-04-14 株式会社デンソー Silicon carbide semiconductor device
GB9929613D0 (en) 1999-12-15 2000-02-09 Koninkl Philips Electronics Nv Manufacture of semiconductor material and devices using that material
US6285060B1 (en) 1999-12-30 2001-09-04 Siliconix Incorporated Barrier accumulation-mode MOSFET
US6755363B2 (en) 2000-01-13 2004-06-29 Reinke Manufacturing Co., Inc. High torque driveline coupler
GB0002235D0 (en) 2000-02-02 2000-03-22 Koninkl Philips Electronics Nv Trenched schottky rectifiers
JP4765012B2 (en) * 2000-02-09 2011-09-07 富士電機株式会社 Semiconductor device and manufacturing method thereof
GB0003185D0 (en) 2000-02-12 2000-04-05 Koninkl Philips Electronics Nv An insulated gate field effect device
GB0003184D0 (en) 2000-02-12 2000-04-05 Koninkl Philips Electronics Nv A semiconductor device and a method of fabricating material for a semiconductor device
DE10007415C2 (en) 2000-02-18 2002-01-24 Infineon Technologies Ag Semiconductor device
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
JP2001244461A (en) 2000-02-28 2001-09-07 Toyota Central Res & Dev Lab Inc Vertical semiconductor device
CN101800243B (en) 2000-03-17 2012-11-07 通用半导体公司 Manufacture method of trench dmos transistor having a double gate structure
JP3636345B2 (en) * 2000-03-17 2005-04-06 富士電機デバイステクノロジー株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US6501129B2 (en) 2000-03-30 2002-12-31 Kabushiki Kaisha Toshiba Semiconductor device
JP4534303B2 (en) * 2000-04-27 2010-09-01 富士電機システムズ株式会社 Lateral superjunction semiconductor device
JP4240752B2 (en) 2000-05-01 2009-03-18 富士電機デバイステクノロジー株式会社 Semiconductor device
EP1285466A2 (en) 2000-05-13 2003-02-26 Philips Electronics N.V. Trench-gate semiconductor device and method of making the same
US6509240B2 (en) * 2000-05-15 2003-01-21 International Rectifier Corporation Angle implant process for cellular deep trench sidewall doping
DE10026924A1 (en) 2000-05-30 2001-12-20 Infineon Technologies Ag compensation component
US6635534B2 (en) 2000-06-05 2003-10-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy
US6391699B1 (en) 2000-06-05 2002-05-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy
US6472678B1 (en) 2000-06-16 2002-10-29 General Semiconductor, Inc. Trench MOSFET with double-diffused body profile
JP4984345B2 (en) 2000-06-21 2012-07-25 富士電機株式会社 Semiconductor device
US6545316B1 (en) 2000-06-23 2003-04-08 Silicon Wireless Corporation MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same
JP4127751B2 (en) 2000-06-29 2008-07-30 株式会社東芝 Semiconductor device and manufacturing method thereof
JP4528460B2 (en) 2000-06-30 2010-08-18 株式会社東芝 Semiconductor element
US6555895B1 (en) 2000-07-17 2003-04-29 General Semiconductor, Inc. Devices and methods for addressing optical edge effects in connection with etched trenches
US6472708B1 (en) 2000-08-31 2002-10-29 General Semiconductor, Inc. Trench MOSFET with structure having low gate charge
US6586833B2 (en) 2000-11-16 2003-07-01 Silicon Semiconductor Corporation Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines
US6608350B2 (en) 2000-12-07 2003-08-19 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
JP4785335B2 (en) 2001-02-21 2011-10-05 三菱電機株式会社 Semiconductor device and manufacturing method thereof
KR100393201B1 (en) 2001-04-16 2003-07-31 페어차일드코리아반도체 주식회사 High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage
US6635544B2 (en) * 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
US6465304B1 (en) 2001-10-04 2002-10-15 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6812525B2 (en) * 2002-06-25 2004-11-02 International Rectifier Corporation Trench fill process

Patent Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6168996A (en) * 2001-01-02
US3497777A (en) * 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) * 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US3660697A (en) * 1970-02-16 1972-05-02 Bell Telephone Labor Inc Monolithic semiconductor apparatus adapted for sequential charge transfer
US4003072A (en) * 1972-04-20 1977-01-11 Sony Corporation Semiconductor device with high voltage breakdown resistance
US4638344A (en) * 1979-10-09 1987-01-20 Cardwell Jr Walter T Junction field-effect transistor controlled by merged depletion regions
US4326332A (en) * 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4445202A (en) * 1980-11-12 1984-04-24 International Business Machines Corporation Electrically switchable permanent storage
US4579621A (en) * 1983-07-08 1986-04-01 Mitsubishi Denki Kabushiki Kaisha Selective epitaxial growth method
US4639761A (en) * 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
US4636281A (en) * 1984-06-14 1987-01-13 Commissariat A L'energie Atomique Process for the autopositioning of a local field oxide with respect to an insulating trench
US5906680A (en) * 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4746630A (en) * 1986-09-17 1988-05-24 Hewlett-Packard Company Method for producing recessed field oxide with improved sidewall characteristics
US5105243A (en) * 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US4821095A (en) * 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US4823176A (en) * 1987-04-03 1989-04-18 General Electric Company Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4801986A (en) * 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
US4990463A (en) * 1988-07-05 1991-02-05 Kabushiki Kaisha Toshiba Method of manufacturing capacitor
US5111253A (en) * 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5079608A (en) * 1990-11-06 1992-01-07 Harris Corporation Power MOSFET transistor circuit with active clamp
US5298761A (en) * 1991-06-17 1994-03-29 Nikon Corporation Method and apparatus for exposure process
US5389815A (en) * 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5605852A (en) * 1992-07-23 1997-02-25 Siliconix Incorporated Method for fabricating high voltage transistor having trenched termination
US5294824A (en) * 1992-07-31 1994-03-15 Motorola, Inc. High voltage transistor having reduced on-resistance
US5300447A (en) * 1992-09-29 1994-04-05 Texas Instruments Incorporated Method of manufacturing a minimum scaled transistor
US5275965A (en) * 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5418376A (en) * 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5710072A (en) * 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US6020250A (en) * 1994-08-11 2000-02-01 International Business Machines Corporation Stacked devices
US5895952A (en) * 1994-12-30 1999-04-20 Siliconix Incorporated Trench MOSFET with multi-resistivity drain to provide low on-resistance
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5623152A (en) * 1995-02-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US5595927A (en) * 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5592005A (en) * 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US6049108A (en) * 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US5629543A (en) * 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US5705409A (en) * 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5879971A (en) * 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation
US6037202A (en) * 1995-09-28 2000-03-14 Motorola, Inc. Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase
US5616945A (en) * 1995-10-13 1997-04-01 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US5895951A (en) * 1996-04-05 1999-04-20 Megamos Corporation MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US6368920B1 (en) * 1996-04-10 2002-04-09 Fairchild Semiconductor Corporation Trench MOS gate device
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
US6040600A (en) * 1997-02-10 2000-03-21 Mitsubishi Denki Kabushiki Kaisha Trenched high breakdown voltage semiconductor device
US5877528A (en) * 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US6037628A (en) * 1997-06-30 2000-03-14 Intersil Corporation Semiconductor structures with trench contacts
US6168996B1 (en) * 1997-08-28 2001-01-02 Hitachi, Ltd. Method of fabricating semiconductor device
US6184545B1 (en) * 1997-09-12 2001-02-06 Infineon Technologies Ag Semiconductor component with metal-semiconductor junction with low reverse current
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
US6376314B1 (en) * 1997-11-07 2002-04-23 Zetex Plc. Method of semiconductor device fabrication
US6066878A (en) * 1997-11-10 2000-05-23 Intersil Corporation High voltage semiconductor structure
US6225649B1 (en) * 1998-01-22 2001-05-01 Mitsubishi Denki Kabushiki Kaisha Insulated-gate bipolar semiconductor device
US6034415A (en) * 1998-02-07 2000-03-07 Xemod, Inc. Lateral RF MOS device having a combined source structure
US5900663A (en) * 1998-02-07 1999-05-04 Xemod, Inc. Quasi-mesh gate structure for lateral RF MOS devices
US5897343A (en) * 1998-03-30 1999-04-27 Motorola, Inc. Method of making a power switching trench MOSFET having aligned source regions
US6376890B1 (en) * 1998-04-08 2002-04-23 Siemens Aktiengesellschaft High-voltage edge termination for planar structures
US6174785B1 (en) * 1998-04-09 2001-01-16 Micron Technology, Inc. Method of forming trench isolation region for semiconductor device
US6190978B1 (en) * 1998-05-04 2001-02-20 Xemod, Inc. Method for fabricating lateral RF MOS devices with enhanced RF properties
US6063678A (en) * 1998-05-04 2000-05-16 Xemod, Inc. Fabrication of lateral RF MOS devices with enhanced RF properties
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6171935B1 (en) * 1998-05-06 2001-01-09 Siemens Aktiengesellschaft Process for producing an epitaxial layer with laterally varying doping
US6015727A (en) * 1998-06-08 2000-01-18 Wanlass; Frank M. Damascene formation of borderless contact MOS transistors
US6064088A (en) * 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
US6201279B1 (en) * 1998-10-22 2001-03-13 Infineon Technologies Ag Semiconductor component having a small forward voltage and high blocking ability
US6194741B1 (en) * 1998-11-03 2001-02-27 International Rectifier Corp. MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6351018B1 (en) * 1999-02-26 2002-02-26 Fairchild Semiconductor Corporation Monolithically integrated trench MOSFET and Schottky diode
US6204097B1 (en) * 1999-03-01 2001-03-20 Semiconductor Components Industries, Llc Semiconductor device and method of manufacture
US6188105B1 (en) * 1999-04-01 2001-02-13 Intersil Corporation High density MOS-gated power device and process for forming same
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6365462B2 (en) * 1999-05-28 2002-04-02 Micro-Ohm Corporation Methods of forming power semiconductor devices having tapered trench-based insulating regions therein
US6365930B1 (en) * 1999-06-03 2002-04-02 Stmicroelectronics S.R.L. Edge termination of semiconductor devices for high voltages with resistive voltage divider
US6346464B1 (en) * 1999-06-28 2002-02-12 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US6359308B1 (en) * 1999-07-22 2002-03-19 U.S. Philips Corporation Cellular trench-gate field-effect transistors
US6353252B1 (en) * 1999-07-29 2002-03-05 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device having trenched film connected to electrodes
US20030060013A1 (en) * 1999-09-24 2003-03-27 Bruce D. Marchant Method of manufacturing trench field effect transistors with trenched heavy body
US6368921B1 (en) * 1999-09-28 2002-04-09 U.S. Philips Corporation Manufacture of trench-gate semiconductor devices
US6222233B1 (en) * 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
US6346469B1 (en) * 2000-01-03 2002-02-12 Motorola, Inc. Semiconductor device and a process for forming the semiconductor device
US6376878B1 (en) * 2000-02-11 2002-04-23 Fairchild Semiconductor Corporation MOS-gated devices with alternating zones of conductivity
US20020009832A1 (en) * 2000-06-02 2002-01-24 Blanchard Richard A. Method of fabricating high voltage power mosfet having low on-resistance
US20020014658A1 (en) * 2000-06-02 2002-02-07 Blanchard Richard A. High voltage power mosfet having low on-resistance
US6362112B1 (en) * 2000-11-08 2002-03-26 Fabtech, Inc. Single step etched moat
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110014764A1 (en) * 2001-01-30 2011-01-20 Marchant Bruce D Method of forming a dual-trench field effect transistor
US8829641B2 (en) 2001-01-30 2014-09-09 Fairchild Semiconductor Corporation Method of forming a dual-trench field effect transistor
WO2008106235A1 (en) * 2007-03-01 2008-09-04 International Rectifier Corporation Trench mosgated device with deep trench between gate trenches
US20080211016A1 (en) * 2007-03-01 2008-09-04 Boden Milton J Trench mosgated device with deep trench between gate trenches
US8125024B2 (en) 2007-03-01 2012-02-28 International Rectifier Corporation Trench MOSgated device with deep trench between gate trenches
CN102751190A (en) * 2011-04-22 2012-10-24 科轩微电子股份有限公司 Channel type power metal oxide semi-conductor structure with fast switching capacity and manufacture method

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US8829641B2 (en) 2014-09-09 grant
US6818513B2 (en) 2004-11-16 grant
US20110014764A1 (en) 2011-01-20 application
US20040132252A1 (en) 2004-07-08 application

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