US5323355A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
US5323355A
US5323355A US07/923,998 US92399892A US5323355A US 5323355 A US5323355 A US 5323355A US 92399892 A US92399892 A US 92399892A US 5323355 A US5323355 A US 5323355A
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Prior art keywords
data
circuit
column address
control signal
output
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English (en)
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Yoshiharu Kato
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Fujitsu VLSI Ltd
Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Definitions

  • the present invention relates to a semiconductor memory device such as a dynamic RAM and, more particularly to a dynamic RAM capable of reading different data sequentially by changing an initial address in the same read cycle and of increasing a reading speed in a nibble mode.
  • DRAMs Dynamic RAMs
  • nibble mode type of DRAMs which are designed to simultaneously read data consisting of a plurality of bits of data to a plurality of pairs of bus lines, and to output the data read out to the respective pairs of bus lines one by one in order to increase a data reading speed.
  • extended nibble modes in the nibble mode type of DRAMs.
  • a DRAM of the conventional nibble mode type is shown in FIG. 14.
  • a memory cell array 11 includes a plurality of memory cells. To the array 11 are connected a row decoder 12, a sense amplifier and input/output (I/O) gate 13, and a column decoder 14. To the sense amplifier and I/O gate 13 is connected a gate circuit 15, to which is connected a data output buffer 16.
  • I/O input/output
  • a row address buffer 17 which feeds to a row decoder 12 an external address signal AD including a plurality of bits input from an unillustrated controller unit.
  • a row controller 18 controls the row decoder 12 and the row address buffer 17 based on the levels of a row address strobe signal RAS and a column address strobe signal CAS, both serving as address activating signals.
  • a column address buffer 19 which feeds to the column decoder 14 an external address signal AD including a plurality of bits input from the controller.
  • a column controller 20 controls the sense amplifier and I/O gate 13, the column decoder 14, and the column address buffer 19 based on the level of an output signal of an AND circuit 21 to which a control signal RASZ from the row controller 18 and the column address strobe signal CAS are input.
  • a clock generating circuit 22 including an odd number of inverter circuits receives the column address strobe signal CAS, and outputs to a nibble counter 23 a clock signal CLK having a negative phase to the signal CAS as shown in FIG. 17.
  • the nibble counter 23 counts the clock signal CLK input from the clock generating circuit 22, and outputs its counted result to a nibble decoder 24.
  • the nibble decoder 24 decodes a counted value of the nibble counter 23, and outputs to a gate control circuit 25 control signals ⁇ A to ⁇ D shown in FIG. 17.
  • the gate control circuit 25 takes an AND (logical product) of the control signals ⁇ A to ⁇ D from the nibble decoder 24 and the clock signal CLK from the clock generating circuit 22, and outputs control signals ⁇ 11 to ⁇ 14 shown in FIG. 17 to the gate circuit 15 so as to control the gate circuit 15.
  • a data input buffer 26 is connected to the sense amplifier and I/O gate 13, and receives a write data Din based on a control signal from an unillustrated write clock generator.
  • FIGS. 15 and 16 show in detail the memory cell array 11, the sense amplifier and I/O gate 13, the gate circuit 15, and the data output buffer 16.
  • a data bus 30 includes four pairs of data bus lines DB0, DB0 to DB3, DB3, to which pairs of bit lines BL0, BL0 to BL3, BL3 are connected, respectively.
  • the pairs of bit lines BL0, BL0 to BL3, BL3 are connected to memory cells 32 each having one end thereof connected to a word line WL through gate transistors T1 and a sense amplifier 31.
  • the control signal ⁇ 11 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB0, DB0.
  • the control signal ⁇ 12 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB1, DB1.
  • the control signal ⁇ 13 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB2, DB2.
  • the control signal ⁇ 14 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB3, DB3.
  • Each of the data bus lines DB0 to DB3 are connected to a common inverter circuit 34 after the transistors T2, while the data bus lines DB0 to DB3 are connected to a common inverter circuit 35 after the transistors T3.
  • the data output buffer 16 includes nMOS transistors T4, T5 connected in series between a power supply VCC and a ground GND.
  • the inverter circuit 34 is connected to a gate terminal of the transistor T4 while the inverter circuit 35 is connected to a gate terminal of the transistor T5.
  • the data output buffer 16 outputs an output signal Dout in the form of a logic value "1" or "0" in accordance with output signals of the inverter circuits 34, 35.
  • a read cycle is started if the column address strobe signal CAS is in the high level (H-level) when the row address strobe signal RAS is switched to a low level (L-level) as shown in FIG. 17.
  • a column address ADC is fed and a column selection signal CL0 turns to H-level.
  • data written in the specified memory cells 32 on the respective pairs of bit lines BL0, BL0 to BL3, BL3 are, via each gate transistor T1 output to the corresponding pairs of data bus lines DB0, DB0 to DB3, DB3, and each data is amplified by the amplifiers 33 respectively.
  • control signals ⁇ 11 to ⁇ 14 are generated by the gate control circuit 23 based on the clock signal CLK from the clock generating circuit 22 and the control signals ⁇ A to ⁇ D from the nibble decoder 24.
  • the transistors T2, T3 arranged on the pairs of data bus lines DB0, DB0 to DB3 are turned on, and thereby the data read out through the data bus lines DB0, BD0 to DB3, DB3 are output through the data output buffer 16 sequentially.
  • the column address ADC of the address signal latched at leading edges of the row address strobe signal RAS and the column address strobe signal CAS is set as an initial address of the nibble counter 23 in the same cycle defined between a fall of the row address strobe signal RAS and a rise thereof.
  • the column selection signal CL0 is maintained in the H-level so as to read out the data to the pairs of data bus lines DB0, DB0 to DB3, DB3. Accordingly, when the addresses corresponding to the number of bits constituting the nibble counter 23 (normally, four bits) are changed from an initial address, the address returns to the initial address, with the result that the output signal Dout outputs again the same data repeatedly.
  • the read cycle is started by changing the row address strobe signal RAS to the L-level immediately after changing the same to the H-level at the time when the addresses corresponding to the number of bits constituting the nibble counter 23 (normally, four bits) are changed.
  • RAS row address strobe signal
  • the present invention is made to overcome the above problems, and an object thereof is to read different data sequentially by changing an initial address in the same read cycle and to increase a reading speed in a nibble mode type DRAM.
  • FIG. 1 is a block diagram explaining a principle of the invention
  • FIG. 2 is a schematic block diagram showing a dynamic RAM as a first embodiment
  • FIG. 3 is an electric circuit diagram showing a data bus in the first embodiment
  • FIG. 4 is an electric circuit diagram showing a data latch unit of the first embodiment
  • FIG. 5 is an electric circuit diagram showing an amplifier
  • FIG. 6 is an electric circuit diagram showing a latch circuit
  • FIG. 7(A) and 7(B) is a block diagram showing a nibble counter
  • FIG. 8 is a timing chart showing an operation of the nibble counter
  • FIG. 9 is a logic circuit diagram showing a nibble decoder
  • FIG. 10 is a logic circuit diagram showing a first gate controller.
  • FIG. 11 is a logic circuit diagram showing a second gate controller
  • FIG. 12 is a timing chart showing an operation of the first embodiment
  • FIG. 13 is a timing chart showing an operation of a second embodiment
  • FIG. 14 is a schematic block diagram of a prior art DRAM
  • FIG. 15 is an electric circuit diagram showing a prior art data bus
  • FIG. 16 is an electric circuit diagram showing a prior art gate circuit
  • FIG. 17 is a timing chart showing a prior art operation
  • FIG. 18 is a timing chart showing a relationship between a signal used to fetch a column address of a second cycle and respective signals;
  • FIG. 19 is a specific electric circuit diagram showing an address fetch circuit 21 (FIG. 2);
  • FIG. 20 is an electric circuit diagram showing a specific example of a column address buffer
  • FIG. 21 is a table showing an example of list of characteristics of a memory according to the invention.
  • FIG. 22 is a chart showing timings for realizing a normal mode and a nibble mode of the DRAM beyond the scope of specifications;
  • FIG. 23 is a diagram explaining an operation of an output latch circuit including a selector.
  • FIG. 24 is a timing chart showing an example of a read cycle in the nibble mode.
  • FIG. 1 is a block diagram explaining a principle of the invention.
  • a data bus 1 includes a plurality of pairs of bus lines DB0, DB0; and DB1, DB1.
  • a plurality of latch circuit 3A to 3D are arranged on the respective pairs of bus lines DB0, DB0; and DB1, DB1.
  • a branch bus 2 includes pairs of bus lines PB0, PB0; and PB1, PB1 which are branched from the respective pairs of bus lines DB0, DB0, DB1 and DB1).
  • a plurality of latch circuits 4A to 4D are arranged on the respective bus lines PB0, PB0; and PB1, PB1.
  • a memory cell array 5 is provided with a plurality of mutually different pairs of bit lines BL0, BL0 to BL3, BL3 corresponding to the respective pairs of bus lines DB0, DB0 and DB1, DB1 of the data bus 1.
  • a first selector circuit 6 selects different bit line pairs from among a plurality of bit line pairs and connects the selected bit line pairs to the corresponding pairs of bus lines DB0, DB0 and DB1, DB1 each time the level of the column address signal is switched in a read cycle.
  • the first selector circuit 6 outputs data stored in the memory cells to the respective pairs of bus lines DB0, DB0 and DB1, DB1 through the selected bit line pairs.
  • a second selector circuit 7 alternately selects either the data bus 1 or the branch bus 2 in synchronization with the selecting operation of the first selector circuit 6, and at that time causes to latch the respective data read through a plurality of bit line pairs selected by the first selector circuit 6 to the respective latch circuits arranged on the selected bus.
  • a third selector circuit 8 alternately selects either the data bus or the branch bus in a sequence selected by the second selector circuit 7 based on a control signal input at a specified period, sequentially selects the respective latch circuits of the selected data bus or branch bus, and outputs the data latched by the selected latch circuits.
  • An output circuit 9 receives the data in a single latch circuit output through the third selector circuit 8 to output an output signal.
  • the different pairs of bit lines are selectively switched and connected to the respective pairs of bus lines by the first selector circuit 6 based on the column address signal in a read cycle.
  • the data stored in the memory cells are output to the respective pairs of bus lines DB0, DB0 and DB1, DB1 through the selected pairs of bit lines.
  • the data bus 1 is selected by the second selector circuit 7 in synchronization with the selecting operation of the first selector circuit 6, and the data read through a plurality of pairs of bit lines selected by the first selector circuit 6 are latched to the respective latch circuits 3A to 3D of the data bus 1.
  • the data bus 1 selected by the second selector circuit 7 is selected by the third selector circuit 8 based on the control signal input at the specified period.
  • the respective latch circuits 3A to 3D of the selected data bus 1 are sequentially selected, and the data latched by the selected latch circuit is output. This data is output as an output signal by the output circuit 9.
  • the branch bus 2 is selected by the second selector circuit 7, and the data read through a plurality of pairs of bit lines selected by the first selector circuit 6 are latched to the respective latch circuits 4A to 4D of the branch bus 2.
  • the branch bus 2 is selected next. Further, the respective latch circuits 4A to 4D arranged on the selected branch bus 2 are sequentially selected, and the data latched by the selected latch circuit is output.
  • a sense amplifier and I/O gate 13 is connected to a data latch unit 36, which is in turn connected to said data output buffer 16.
  • the data latch unit 36 is controlled by a gate control circuit 39, to which is connected a nibble decoder 38 for decoding a count result of a nibble counter 37.
  • a count output of the nibble counter 37 is sent together with a column address strobe signal CAS through an address fetching circuit 21 to a column controller 20, an output of which is sent to a column decoder 14.
  • a normal read operation, a normal write operation, and a read operation in a nibble mode will be described hereat, with reference to FIG. 2.
  • the signal RAS is activated from H-level to L-level.
  • a row controller 18 outputs a control signal to fetch a row address to a row address buffer 17. Thereupon, the row address buffer 17 latches an address input to an address terminal thereof as a row address.
  • the row address is sent to a row decoder 12, which in turn selects one word line.
  • the data stored in a memory cell connected to the selected word line is output to the respective pairs of bit lines for one word, and is amplified by the sense amplifier 13.
  • the signal CAS is activated from H-level to L-level after the operation 2.
  • the column controller 20 outputs the control signal to fetch the column address to the column address buffer 19.
  • the column address buffer 19 in turn latches the address input to an address terminal thereof as a column address.
  • the column address is sent to the column decoder 14, which in turn selects four gate transistors (I/O gate 13).
  • the four gate transistors selected by the column decoder 14 output the data to the four pairs of data buses.
  • the output data are then amplified by the amplifier, are latched by the data latch unit 36, and are output through four data output buffers 16.
  • a write enable signal (WE) is activated from H-level to L-level, thereby making the data output buffer 16 inactive.
  • the column controller 20 feeds the control signal to fetch the data to the data input buffer 26, which in turn latches the data input to a data terminal thereof.
  • the latched data is amplified by an unillustrated write amplifier, and is written in four memory cells selected by the row address and the column address through the pairs of bit lines.
  • the most significant bits of the row address and the column address are set as a nibble address in the nibble decoder 38.
  • the nibble counter 37 counts up each time an edge where the signal CAS changes from H-level to L-level is detected.
  • the nibble decoder 38 increments the set nibble address (the nibble address is returned to the original one upon fourth increment, and thereby a toggle operation is started).
  • the four gate transistors selected by the column decoder 14 deliver the data to the four pairs of data buses.
  • the data is amplified by the amplifier, and is latched by a first data latch unit in response to an output of a gate control circuit 39 for generating a control signal to control the gates upon receipt of the signal from the nibble decoder 38.
  • the address fetching circuit 21 executes the same operations as those of 5 to 6 of said normal read operation.
  • the four gate transistors selected by the column decoder 14 deliver data to the four pairs of data buses, the data is then amplified by the amplifier and is latched in a second data latch unit in response to the output of the gate control circuit 39.
  • the data latched in the first and the second data latch units are controlled by the control signal in the gate control circuit 39, and are output through the data output buffer 16 bit by bit as disclosed in the present specification.
  • FIG. 18 is a timing chart showing the relationship between a signal ⁇ L to fetch the column address in the second cycle and signals RAS, CAS, ⁇ A, N1, N2, N3, and N4.
  • FIG. 19 is a specific circuit diagram of the address fetching circuit 21 (see FIG. 2).
  • indicated at 19-a is a circuit for generating a pulse having a specified duration upon the first fall edge of the signal CAS
  • at 19-b a circuit which is reset when the signal RAS is in the H-level (when a node 195 is in the H-level) and keeps on storing that the signal CAS has fallen to the L-level first while the signal RAS is in the L-level.
  • Indicated at 19-c is a circuit for extracting only the signal CAS in the H-level coming immediately after the first fall edge of the signal CAS in accordance with the signal CAS and the signal ⁇ A output from the nibble decoder.
  • Indicated at 19-d is an OR circuit for taking a logical sum of the output of the circuit 19-b and that of the circuit 19-c to generate a signal ⁇ L.
  • FIG. 20 shows a column address buffer circuit
  • FIG. 21 shows an exemplary table showing a list of characteristics of the memory device according to the present invention.
  • FIG. 22 is a chart showing timings for realizing a normal mode and a nibble mode of the DRAM beyond the scope of the specifications.
  • a nibble mode of read/write cycle tNC is set at 50 ns for the fall of the row address strobe signal RAS and a waveform of the column address strobe signal CAS.
  • the second column address (access time tAA) to satisfy the condition of outputting the data at a fifth fall edge of the signal CAS. Accordingly, it can be guaranteed to output the data in tCAC (20 ns) if the second column address is fetched more than tAA before the fifth output. In other words, it is sufficient for the second column address to be fetched in a region A shown in FIG. 22. In this case, since the signal CAS serves as a fetch clock, the second column address may be fetched at the second, third, or fourth fall edge of the signal CAS.
  • An output latch circuit including a selector operates as shown in FIGS. 6 and 23. More specifically, a signal ⁇ 0 to switch an input to the output data latch circuit operates, while one latch is outputting, to feed the input to the other latch.
  • FIG. 24 is an exemplary timing chart of a read cycle in the nibble mode.
  • a data bus 30 in this embodiment includes four pairs of data bus lines DB0, DB0 to DB3, DB3, to which are connected eight pairs of bit lines. Specifically, two pairs of bit lines BL0, BL0; and BL4, BL4 are connected to the pair of bus lines DB0, DB0. Two pairs of bit lines BL1, BL1; and BL5, BL5 are connected to the pair of bus lines DB1, DB1. Two pairs of bit lines BL2, BL2; and BL6, BL6 are connected to the pair of bus lines DB2, DB2. Two pairs of bit lines BL3, BL3; and BL7, BL7 are connected to the pair of bus lines DB3, DB3.
  • bit lines BL0, BL0 to BL3, BL3 are connected to a memory cell 32 having one end thereof connected to a word line WL through gate transistors T6 serving as a first selector circuit 6 and a sense amplifier 31.
  • the respective pairs of bit lines BL4, BL4 to BL7, BL7 are connected through gate transistors T7 serving as a first selector circuit 6 and a sense amplifier (31' (hereinafter unillustrated)) to a memory cell having one end thereof connected to a word line.
  • a column selection signal CL1 is input to gate terminals of the respective gate transistors T6, while a column selection signal CL2 is input to gate terminals of the respective gate transistors T7.
  • the respective pairs of bit lines BL0, BL0 to BL3, BL3 are connected to the respective pairs of data buses DB0, DB0 to DB3, DB3.
  • the column selection signal CL2 becomes a logic "1”
  • the respective pairs of bit lines BL4, BL4 to BL7, BL7 are connected to the respective pairs of data buses DB0, DB0 to DB3, DB3.
  • the pairs of data bus lines DB0, DB0 to DB3, DB3 are each provided with an amplifier 33.
  • Each amplifier 33 includes inverter circuits INV1 and INV2 as shown in FIG. 5.
  • gate transistors T8 are connected to output sides of the respective amplifiers 33.
  • the gate transistors T8 are adapted to input control signals ⁇ X to gate terminals of the amplifiers 33.
  • Pairs of branch bus lines PB0, PB0 to PB3, PB3 are branched from the pairs of data bus lines DB0, DB0 to DB3, DB3 after the respective gate transistors T8. These pairs of branch bus lines PB0, PB0 to PB3, PB3 constitute a branch bus.
  • a gate transistor T9, a latch circuit 40, and a gate transistor T10 are provided in series on each of the data bus lines DB0, DB0 to DB3, DB3. Further, a gate transistor T11, a latch circuit 41, and a gate transistor T12 are provided in series on each of the branch bus lines PB0 to PB3.
  • the latch circuits 40, 41 are each a known latch circuit including four inverters INV3 to INV6, and adapted to latch the data read out through the data bus lines DB0 to DB3 by the gate transistor T9 or T11.
  • the gate transistors T9 and T11 constitute a second selector circuit 7.
  • the control signal ⁇ 0 is input to gate terminals of the gate transistors T9, while an inverted signal of the control signal ⁇ 0 is input to gate terminals of the gate transistors T11. Accordingly, only the gate transistors T9 turn ON in the case where the control signal ⁇ 0 is a logic "1", and therefore the data are latched by the respective latch circuits 40 provided on the data bus lines DB0, DB0 to DB3, DB3.
  • the gate transistors T10, T12 constitute a third selector circuit 8.
  • a control signal ⁇ 1 is input to gate terminal of the gate transistors T10 provided on the pair of data bus lines DB0, DB0
  • a control signal ⁇ 3 is input to gate terminals of the gate transistors T10 provided on the pair of data bus lines DB1, DB1
  • a control signal ⁇ 5 is input to gate terminals of the gate transistors T10 provided on the pair of data bus lines DB2, DB2
  • a control signal ⁇ 7 is input to gate terminals of the gate transistors T10 provided on the pair of data bus lines DB3, DB3.
  • a control signal ⁇ 2 is input to gate terminals of the gate transistors T12 provided on the pair of branch bus lines PB0, PB0; a control signal ⁇ 4 is input to gate terminals of the gate transistors T12 provided on the pair of branch bus lines PB1, PB1; a control signal ⁇ 6 is input to gate terminals of the gate transistors T12 provided on the pair of branch bus lines PB2, PB2; and a control signal ⁇ 8 is input to gate terminals of the gate transistors T12 provided on the pair of branch bus lines PB3, PB3.
  • the data bus lines DB0 to DB3 and the branch bus lines PB0 to PB3 are connected to a common inverter circuit 34 after the gate transistors T10, T12 thereof.
  • the data bus lines DB0 to DB3 and the branch bus lines PB0 to PB3 are connected to a common inverter circuit 35 after the gate transistors T10, T12 thereof.
  • the nibble counter 37 includes three master/slave type flip-flops (hereinafter abbreviated as FF) 43a to 43c.
  • FF master/slave type flip-flops
  • the FF 43a inverts a bit D0 upon receipt of each clock signal CLK input from the clock generating circuit 22; the FF 43b inverts a bit D1 upon receipt of every two clock signals CLK; and the FF 43c inverts a bit D2 upon receipt of every four clock signals CLK.
  • the FFs 43a to 43c output the bits D0 to D2 to the nibble decoder 38.
  • the nibble decoder 38 includes NAND circuits 44 to 47 and inverter circuits 48 to 53 as shown in FIG. 9, and is adapted to decode the bits D0, D1 from the nibble counter 37 and to output control signals ⁇ A to ⁇ D shown in FIG. 12 to the gate control circuit 39. More specifically, the NAND circuit 44 receives the bits D0 and D1, and outputs the control signal ⁇ A through the inverter circuit 50. The NAND circuit 45 receives the bits D0 and D1, and outputs the control signal ⁇ B through the inverter circuit 51. The NAND circuit 46 receives the bits D0 and D1, and outputs the control signal ⁇ C through the inverter circuit 52. The NAND circuit 47 receives the bits D0 and D1, and outputs the control signal ⁇ D through the inverter circuit 53.
  • the gate control circuit 39 includes a first gate control unit 54 shown in FIG. 10 and a second gate control unit 55 shown in FIG. 11.
  • the first gate control unit 54 is provided with a NOR circuit 56 to which the control signals ⁇ A and ⁇ B are input from the nibble decoder 38, and an inverter circuit 57, and outputs the control signal ⁇ X shown in FIG. 12 to said respective gate transistors T8 (see FIG. 4) based on the control signals ⁇ A, ⁇ B. Accordingly, the control signal ⁇ X is a logic "1" only during a period when either the control signal ⁇ A or ⁇ B is a logic "1", and the gate transistors T8 turn on at this time.
  • the second gate control unit 55 includes first and second control signal generators 58 and 59 as shown in FIG. 11.
  • the first control signal generator 58 includes NOR 60 to 62, a NAND circuit 63, and inverter circuits 64 to 66, and generates a control signal ⁇ Y upon receipt of the bits D0 to D2 input from the nibble counter 37.
  • the NOR circuit 60 receives the bits D0 and D1, and has an output terminal thereof connected to the inverter circuit 64.
  • the NOR circuit 61 receives a bit D2 and is connected to the inverter circuit 64. An output terminal of the NOR circuit 61 is connected to the NOR circuit 62.
  • the NAND circuit 63 receives a bit D2 and is connected to the inverter circuit 64. An output terminal of the NAND circuit 63 is connected to the NOR circuit 62 through the inverter circuit 65.
  • the control signal ⁇ Y is a logic "0".
  • the control signal ⁇ Y is a logic "1"
  • the second control signal generator 59 includes NAND circuits 67 to 74 and inverter circuits 75 to 83, and outputs control signals ⁇ 0 to ⁇ 8 shown in FIG. 12. More specifically, the inverter circuit 83 inverts said control signal ⁇ Y, and outputs the control signal ⁇ 0 to control said gate transistors T9 and T11.
  • the NAND circuit 67 receives the clock signal CLK and the control signals ⁇ 0 and ⁇ A, and outputs the control signal ⁇ through the inverter circuit 15.
  • the NAND circuit 69 receives the clock signal CLK and the control signals ⁇ 0 and ⁇ B, and outputs the control signal ⁇ 3 through the inverter circuit 77.
  • the NAND circuit 71 receives a clock signal CLK and the control signals ⁇ 0 and ⁇ C, and outputs the control signal ⁇ 5 through the inverter circuit 79.
  • the NAND circuit 73 receives the clock signal CLK and the control signals ⁇ 0, ⁇ D, and outputs the control signal ⁇ 7 through the inverter circuit 81.
  • the NAND circuit 68 receives the clock signal CLK and the control signals ⁇ Y, ⁇ A, and outputs the control signal ⁇ 2 through the inverter circuit 76.
  • the NAND circuit 70 receives the clock signal CLK and the control signals ⁇ Y and ⁇ B, and outputs the control signal ⁇ 4 through the inverter circuit 78.
  • the NAND circuit 72 receives the clock signal CLK and the control signals ⁇ Y and ⁇ C, and outputs the control signal ⁇ 6 through the inverter circuit 80.
  • the NAND circuit 74 receives the clock signal CLK and the control signal ⁇ 8 through the inverter circuit 82.
  • the read cycle is started if the column address strobe signal CAS is in the H-level.
  • the column address ADC is fed to switch the column selection signal CL1 to H-level.
  • the data written in the specified memory cells 22 on the pairs of bit lines BL0, BL0 to BL3 are output to the pairs of data bus lines DB0, DB0 to DB3, DB3 through the gate transistors T6, and are amplified by the amplifiers 33.
  • control signal ⁇ A Since the control signal ⁇ A is a logic "1" at this time, the control signal ⁇ 1 becomes a logic "1". Thereupon, only the gate transistors T10 provided on the pair of data bus lines DB0, DB0 are tuned on and the data read through the pairs of the data bus lines DB0, DB0 are output through the data output buffer 16.
  • the column selection signal CL2 switches to H-level while the column selection signal CL1 switches to L-level.
  • the data written in the specified memory cells 22 on the pairs of bit lines BL4, BL4 to BL7, BL7 are output to the pairs of data bus lines DB0, DB0 to DB3, DB3 through the gate transistors T7, and are amplified by the amplifiers 33. Since the control signal ⁇ X is a logic "0" at this time, the respective gate transistors T8 are turned off. Thus, the data in the amplifiers 33 are not transferred.
  • control signal ⁇ A Since the control signal ⁇ A is a logic "1" at this time, the control signal ⁇ 2 becomes a logic "1". Thereupon, only the gate transistors T12 provided on the pair of branched bus lines PB0 and PB0 are turned on and the data read through the branched bus lines PB0 and PB0 are output through the data output buffer 16.
  • a branched bus line is provided for a data bus including a plurality of pairs of data bus lines DB0, DB0 to DB3, DB3.
  • latch circuits 40, 41 are arranged on the pair of the bus lines DB0, DB0 to DB3, DB3 and the pairs of branched bus lines PB0, PB0 to PB3, PB3.
  • data to be output next are read up to immediately before the latch circuits 41 arranged on the pairs of the branched bus lines by switching a column address while data are first latched to the latch circuits 40 on the pairs of bus lines and are output in synchronization with a clock signal.
  • the read data that was read in the latch circuits 41 arranged on the pairs of the branched bus lines is latched, and is sequentially output in synchronization with the clock signal. Accordingly, different data can be sequentially output in one read cycle, and a data reading speed can be increased.
  • the invention is embodied by a DRAM in which a single data output buffer 16 is provided for a data bus 30 including pairs of data bus lines DB0, DB0 to DB3, DB3.
  • the invention may be embodied by a DRAM comprising a plurality of data buses each including a plurality of pairs of bus lines and a respective data output buffer provided for each data bus.
  • the invention has an excellent advantage of reading different data sequentially by changing an initial address in the same read cycle, and of increasing a data reading speed in a dynamic RAM of the nibble mode type.

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US07/923,998 1991-01-22 1992-01-22 Semiconductor memory device Expired - Fee Related US5323355A (en)

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PCT/JP1992/000048 WO1992013348A1 (en) 1991-01-22 1992-01-22 Semiconductor storing device

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US20050002233A1 (en) * 1997-08-07 2005-01-06 Guterman Daniel C. Novel multi-state memory
US20040246798A1 (en) * 1997-08-07 2004-12-09 Guterman Daniel C. Novel multi-state memory
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US7187592B2 (en) 1997-08-07 2007-03-06 Sandisk Corporation Multi-state memory
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US20030135693A1 (en) * 2001-12-31 2003-07-17 David Howard S. Distributed memory module cache command formatting
US6931505B2 (en) * 2001-12-31 2005-08-16 Intel Corporation Distributed memory module cache command formatting
US20030126373A1 (en) * 2001-12-31 2003-07-03 David Howard S. Distributed memory module cache writeback
CN100437824C (zh) * 2003-06-30 2008-11-26 海力士半导体有限公司 用于掩盖写入振荡的数据传送控制设备及其方法
US20060104152A1 (en) * 2004-10-07 2006-05-18 Martin Eric T Controlling an addressable array of circuits
US20160253228A1 (en) * 2015-02-27 2016-09-01 SK Hynix Inc. Error detection circuit and semiconductor apparatus using the same
US10204005B2 (en) * 2015-02-27 2019-02-12 SK Hynix Inc. Error detection circuit and semiconductor apparatus using the same

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WO1992013348A1 (en) 1992-08-06
EP0521165A1 (en) 1993-01-07
EP0521165A4 (enrdf_load_stackoverflow) 1995-05-24

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