US4829237A - Circuit device having a self-testing function and a testing method thereof - Google Patents

Circuit device having a self-testing function and a testing method thereof Download PDF

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US4829237A
US4829237A US07/195,636 US19563688A US4829237A US 4829237 A US4829237 A US 4829237A US 19563688 A US19563688 A US 19563688A US 4829237 A US4829237 A US 4829237A
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parallel
circuit
tested
serial
signal
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Hiroshi Segawa
Masahiko Yoshimoto
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SEGAWA, HIROSHI, YOSHIMOTO, MASAHIKO
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Definitions

  • the present invention relates to a circuit device having a self-testing function, and a testing method thereof. Particularly, it relates to a circuit device and a testing method thereof by which a plurality of circuits to be tested contained in the device can be tested for a short period of time.
  • tests for such verification are usually conducted at the time of debugging before manufacturing of semiconductor integrated circuits or at the time of verification of performance before shipment.
  • a circuit to be tested is operated after predetermined data has been inputted thereto and it is determined based on data outputted therefrom whether the circuit is normally operated or not.
  • FIG. 1 is a block diagram showing an example of connection in a conventional semiconductor integrated circuit including two circuits to be tested.
  • This semiconductor integrated circuit 8 includes as the two circuits to be tested a first circuit 2 and a second circuit 5.
  • a test is performed by using three scanning registers in the integrated circuit 8, i.e., a first scanning register 1, a second scanning register 4 and a third scanning register 6.
  • a serial input terminal 83 of the integrated circuit 8 is connected to a serial input terminal 13 of the first scanning register 1.
  • parallel input terminals 81 of the integrated circuit 8 are connected to parallel input terminals 1 of the first scanning register 1.
  • Parallel output terminal 12 of the first scanning register 1 are connected to parallel input terminals 21 of the first circuit 2 to be tested.
  • Parallel output terminals 22 of the first circuit 2 to be tested are connected to parallel input terminals 41 of the second scanning register 4.
  • a serial output terminal 14 of the first scanning register 1 is connected to a serial input terminal 43 of the second scanning register 4.
  • Parallel output terminals 42 of the second scanning register 4 are connected to parallel input terminals 51 of the second circuit 5 to be tested.
  • parallel output terminals 52 of the second circuit 5 to be tested are connected to parallel input terminals 61 of the third scanning register 6.
  • a serial output terminal 44 of the second scanning register 4 is connected to a serial input terminal 63 of the third scanning register 6.
  • Parallel output terminals 62 of the third scanning register 6 are connected to parallel output terminals 82 of the integrated circuit 8.
  • a serial output terminal 64 of the third scanning register 6 is connected to a serial output terminal 84 of the integrated circuit 8.
  • a selection signal generator 9 generates a selection signal Sc for selecting a mode of the scanning registers and supplies it to the first, second and third scanning registers 1, 4 and 6, respectively.
  • a clock generator 7 generates a clock signal ⁇ for synchronously operating all of the first, second and third scanning registers 1, 4 and 6 and the first and second circuits 2 and 5 to be tested. The clock signal ⁇ is supplied to each of those circuits.
  • FIG. 2 is a block diagram showing a scanning register (the first scanning register 1 as an example) used for testing of the integrated circuit of FIG. 1.
  • the scanning register 1 comprises registers SL1 to SLn each including a selector 15 and a master-slave latch 16 connected to the corresponding parallel input terminal 11 and the corresponding parallel output terminal 12, respectively.
  • the selector 15 of the register SL1 has two inputs i1 and i2, the one input i1 being connected to the serial input terminal 13 of the scanning register 1 and the other input i2 being connected to the corresponding one of the parallel input terminals 11 of the scanning register 1.
  • the selection signal Sc is supplied to the selector 15.
  • the master-slave latch 16 of the register SL1 has an input connected to an output of the selector 15 and an output connected to the corresponding one of the parallel output terminals 12 of the scanning register 1.
  • the clock signal ⁇ is supplied to the master-slave latch 16.
  • the output of the register SL1 is connected to one of the inputs of the selector 15 of the register SL2.
  • the registers SL2 to SLn are connected in the same manner as described above, except that the output of the last register SLn is connected to the serial output terminal 14 of the scanning register 1.
  • the scanning register 1 operates in a parallel mode (also called an operation mode) or a serial mode (also called a shift mode) in response to the selection signal Sc.
  • Each master-slave latch 16 receives data from the corresponding selector 15 in response to the clock signal ⁇ of high level and stores the data in response to the clock signal ⁇ of low level.
  • each selector 15 selectively receives data supplied to the corresponding input i2 in response to the selection signal Sc of low level instructing the parallel mode and outputs the data to the master-slave latch 16.
  • the master-slave latch 16 latches the data outputted from the selector 15 and outputs the latched data through one of the parallel output terminals 12.
  • the registers SL1 to SLn constitute parallel registers operating in response to the clock signal ⁇ .
  • the selector 14 of the register SL1 selectively receives data supplied to the input i1 in response to the selection signal Sc of high level instructing the serial mode and outputs the data to the master-slave latch 16.
  • the respective registers SL2 to SLn receive outputs of the master-slave latches connected at the respective preceding stages by the functioning of the respective selectors. Accordingly, in this case, the registers SL1 to SLn constitute shift registers having n master-slave latches connected serially and operating in response to the clock signal ⁇ .
  • FIG. 3 is a block diagram showing an example of a circuit to be tested (the first circuit 2 of FIG. 1).
  • the circuit 2 to be tested comprise an adder 23, a register 24 and a limiter 25 which are connected serially between the parallel input terminals 21 and the parallel output terminals 22.
  • data is inputted to the adder 23 through the parallel input terminals 21 in response to the clock signal ⁇ .
  • the data obtained through addition is supplied to the register 24 in response to the clock signal ⁇ and then limiting processing is applied to the data in the limiter 25.
  • the circuit to be tested processes the input data and outputs the data in a period of two cycles of the clock signal ⁇ .
  • the selection signal generator 9 generates a selection signal Sc of low level. All the scanning registers 1, 4 and 6 operate in the serial mode in response to the selection signal Sc. Predetermined test pattern data D1 for testing is supplied to the serial input terminal 83 of the integrated circuit 8. The first scanning register 1 stores the pattern data D1 through its serial input terminal 13 in response to the clock signal ⁇ . Then, a selection signal Sc of high level is outputted from the generator 9 and all the scanning registers 1, 4 and 6 operate in the parallel mode. The first scanning register 1 outputs the test pattern data converted to parallel data from the parallel output terminals 12 in response to the clock signal ⁇ .
  • the first circuit 2 to be tested performs predetermined operation upon receipt of the parallel test pattern data through the parallel input terminals 21 and outputs the processed data in parallel from the parallel outputs terminals 22.
  • the second scanning register 4 receives the processed data through the parallel input terminals 41 and then the generator 9 outputs a selection signal Sc of low level.
  • the second scanning register 4 converts the processed data to serial data in response to the signal Sc and outputs the serial data from the serial output terminal 44.
  • the third scanning register 6 receives the processed serial data through the serial input terminal 63 and outputs the data from the serial output terminal 64.
  • the data is outputted from the serial output terminal 84 of the integrated circuit 8.
  • the predetermined test pattern data D1 supplied to the serial input terminal 83 and the processed data outputted from the serial output terminal 84 are analyzed, so that it can be verified whether the first circuit 2 to be tested operates normally or not.
  • predetermined test pattern data D2 supplied through the serial input terminal 83 is supplied to the second scanning register 4 through the first scanning register 1.
  • the second scanning register 4 converts the data D2 to parallel data and then supplies it to the second circuit 5 to be tested.
  • the parallel data processed by the second circuit 5 is supplied to the scanning register 6, where it is converted to serial data.
  • the serial data thus converted and the predetermined test pattern data D2 are analyzed.
  • FIG. 4 is a flow chart for explaining operation procedures in the integrated circuit of FIG. 1.
  • This flow chart represents operation steps of the integrated shown in FIG. 1 for verifying operations of the first circuit 2 and the second circuit 5 to be tested as described above.
  • an operation delay time in the first circuit 2 to be tested corresponds to three clocks and that in the second circuit 5 to be tested corresponds to four clocks.
  • all the scanning registers 1, 4 and 6 have 8-bit input/output terminals.
  • the delay time in each operation step is indicated in the figure on the right side thereof by the count number of clock signals ⁇ .
  • step 201 all the scanning registers 1, 4 and 6 are set to the serial mode. (In other words, the selection signal generator 9 of FIG. 1 outputs the selection signal Sc of low level.)
  • step 202 the test pattern data D1 for the first circuit 2 to be tested is inputted serially to the first scanning register 1. The period of this procedure corresponds to eight clocks.
  • step 203 the scanning registers 1, 4 and 6 are set to the parallel mode. (In other words, the selection signal Sc of high level is outputted.)
  • step 204 the first circuit 2 to be tested is operated. This procedure takes three clocks.
  • step 205 the scanning registers 1, 4 and 6 are set to the serial mode.
  • the data processed by the first circuit 2 to be tested is outputted serially from the output terminal 84 through the second and third scanning registers 4 and 6. This procedure takes 15 clocks.
  • the data from the output terminal 84 and the test pattern data D1 supplied to the input terminal 83 are analyzed, whereby operation of the first circuit 2 is verified.
  • the test pattern data D2 for the second circuit to be tested is inputted serially to the second scanning register 4 through the first scanning register 1.
  • This step takes 16 clocks.
  • the scanning registers 1, 4 and 6 are set to the parallel mode. (The selection signal Sc of high level is outputted.)
  • the second circuit 5 to be tested is operated. This procedure corresponds to four clocks.
  • the scanning registers 1, 4 and 6 are set to the serial mode. (The selection signal Sc of low level is outputted.)
  • the data processed by the second circuit 5 to be tested is outputted to the output terminal 84 through the third scanning register 6. This takes seven clocks. The data from the output terminal 84 and the test pattern data D2 supplied to the input terminal 83 are analyzed, so that operation of the second circuit 5 is verified.
  • an object of the present invention is to provide a circuit device including a plurality of circuit means to be tested for verification of operation thereof, which makes it possible to reduce time required for the test.
  • Another object of the present invention is to provide a semiconductor integrated circuit including a plurality of circuit means to be tested for verification of operation thereof, which makes it possible to reduce time required for the test.
  • Still another object of the present invention is to provide an testing method of a circuit device including a plurality of circuit means to be tested for verification of operation thereof, which makes it possible to reduce time required for the test.
  • a further object of the present invention is to provide a testing method of a semiconductor integrated circuit including a plurality of circuit means to be tested for verification of operation thereof, which makes it possible to reduce time required for the test.
  • a circuit device in accordance with the present invention comprises: a plurality of circuits to be tested including at least one circuit operated for a different processing period; a plurality of scanning registers having parallel and serial inputs and parallel and serial outputs, and operated in response to a clock signal in either a parallel mode or a serial mode; and an output timing regulation circuit connected to the circuit to be tested operated for the different processing period to regulate output timing so that signals processed by the pairs each constituted by a circuit to be tested and a scanning register are outputted simultaneously.
  • a testing signal is applied externally to each of the scanning registers. All the circuits to be tested receive the testing signal and operate simultaneously. Although one or more circuits to be tested operated for the different processing periods exist, the testing signals processed are outputted simultaneously from all the pairs by the output timing regulation circuit connected thereto.
  • the present invention is applied to a semiconductor integrated circuit.
  • testing time for verifying operation of the semiconductor integrated circuit is reduced.
  • a method of operating a circuit device comprising a plurality of circuits to be tested including at least one circuit operated for a different processing period, and a plurality of scanning registers connected to the plurality of circuits to be tested to constitute pairs and operated in either a parallel mode or a serial mode, comprises the steps of: supplying a testing signal to each of the scanning registers; operating the circuits to be tested simultaneously in all the pairs upon receipt of the testing signals from the scanning registers; and regulating output timing to enable the processed testing signals to be outputted simultaneously from all the pairs.
  • the method according to the present invention is applied to a semiconductor integrated circuit. Consequently, testing time for verifying operation of the semiconductor integrated circuit is reduced.
  • FIG. 1 is a block diagram showing connection of a conventional semiconductor integrated circuit including two circuits to be tested.
  • FIG. 2 is a block diagram showing a scanning register in FIG. 1.
  • FIG. 3 is a block diagram showing an example of a circuit to be tested in FIG. 1.
  • FIG. 4 is a flow chart showing testing procedures in the semiconductor integrated circuit shown in FIG. 1.
  • FIG. 5 is a block diagram showing connection of a semiconductor integrated circuit including two circuits to be tested according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing an example of a register in FIG. 5.
  • FIG. 7 is a flow chart according to another embodiment of the present invention, showing testing procedures in the semiconductor integrated circuit shown in FIG. 5.
  • FIG. 8 is a block diagram showing simplified connection where the present invention is generally applied to a semiconductor integrated, including circuit more than two circuits to be tested.
  • FIG. 5 is a block diagram showing connection of a semiconductor integrated circuit including two circuits to be tested, according to an embodiment of the present invention.
  • the semiconductor integrated circuit 8 is the same as the integrated circuit of FIG. 1, except that the semiconductor integrated circuit 8 of FIG. 5 includes a register 3 for applying delay. More specifically, the integrated circuit 8 comprises first and second circuits 2 and 5 to be tested for verification of operation thereof and first, second and third scanning registers 1, 4 and 6.
  • the register 3 has parallel input terminals 31 and parallel output terminals 32 and it is connected between parallel output terminals 22 of the first circuit to be tested and parallel input terminals 41 of the second scanning register 4.
  • the register 3 is connected to receive a clock signal ⁇ .
  • FIG. 6 is a circuit diagram showing a concrete example of the register shown in FIG. 5.
  • the register 3 comprises a plurality of shift registers 33 connected between the parallel input terminals 31 and the parallel output terminals 32 respectively.
  • Each shift register 33 comprises a first storing circuit including a transistor 332 and two inverters 336 and 337, and a second storing circuit including a transistor 334 and two inverters 338 and 339, as well as transistors 331 and 333 and an inverter 335 for timing control connected to receive a clock signal ⁇ .
  • the transistors in each shift register 33 are all N channel MOS transistors.
  • the transistor 331 receives an input signal from an input terminal 31 in response to the clock signal ⁇ of high level. Then, the clock signal ⁇ changes to low level. Since the transistor 332 is turned on in response to the inverted clock signal, the input signal is stored in the first storing circuit. At the same time, the transistor 333 is also turned on and accordingly the input signal is supplied to the inverter 338 and then outputted from an output terminal 32 through the inverter 339.
  • testing operation for the first and second circuits 2 and 5 is described.
  • an operation delay time in the first circuit 2 to be tested corresponds to three clocks and that in the second circuit 5 to be tested corresponds to four clocks.
  • all the scanning registers 1, 4 and 6 have 8-bit input and output terminals.
  • the selection signal generator 9 outputs a selection signal Sc of low level and all the scanning registers 1, 4 and 6 are operated in the serial mode in response to the signal Sc.
  • the predetermined test pattern data D2 for the second circuit 5 to be tested and then the predetermined test pattern data D1 for the first circuit 1 to be tested are successively inputted serially to the serial input terminal 83 of the integrated circuit 8.
  • the test pattern data D2 is transferred serially to the second scanning register 4 through the first scanning register 1 and stored in the second scanning register 4.
  • the test pattern data D1 is stored in the first scanning register 1.
  • a selection signal Sc of high level is outputted from the generator 9 and all the scanning registers 1, 4 and 6 are operated in the parallel mode.
  • the scanning register 1 outputs parallel-converted test pattern data from the parallel output terminals 12 and supplies the data to the first circuit 2 to be tested.
  • the first circuit 2 to be tested performs predetermined operation in response to the clock signal ⁇ and outputs the processed data in parallel.
  • the register 3 receives the processed data through the parallel input terminals 31 and stores it for a predetermined period (corresponding to one clock in this example) and then it outputs the data in parallel from the parallel output terminals 32 to the second scanning register 4.
  • the second circuit 5 to be tested performs operation at the same time. More specifically, the second circuit 5 to be tested receives the parallel-converted test pattern data from the second scanning register 4 and performs predetermined operation in response to the clock signal ⁇ . The processed data outputted from the second circuit 5 to be tested is inputted in parallel to the third scanning register 6.
  • the selection signal generator 9 outputs a selection signal Sc of low level.
  • the second and third scanning registers 4 and 6 are both operated in the serial mode so that the stored data are outputted.
  • the data stored in the third scanning register 6 is outputted serially from the output terminal 84.
  • the data stored in the second scanning register 4 is outputted serially from the output terminal 84 through the third scanning register 6.
  • the data thus outputted serially and the test pattern data D1 and D2 are analyzed, whereby it is verified whether the first and second circuits 2 and 5 are operated normally or not.
  • FIG. 7 is a flow chart for explaining operation procedures of the integrated circuit of FIG. 5. Delay times in the respective steps are shown on the right side thereof by the count number of clock signals ⁇ in the same manner as in FIG. 4.
  • step 101 all the scanning registers 1, 4 and 6 are set to the serial mode. (A selection signal Sc of low level is outputted.) Then, in the step 102, the test pattern data D1 and D2 for the first and second circuits 2 and 5 to be tested, respectively, are inputted serially. This procedure takes 16 clocks. In the step 103, the scanning registers 1, 4 and 6 are set to the parallel mode. (A selection signal Sc of high level is outputted.) In the step 104, the first and second circuits 2 and 5 to be tested are operated at the same time. Three clocks are required for operation of the first circuit 2 to be tested, while four clocks are required for operation of the second circuit 5 to be tested.
  • the data processed by the first circuit 2 to be tested is stored in the register 3 for a period of one clock. Accordingly, the steps 104 and 105 take four clocks in total and the data processed simultaneously in the first and second circuits 2 and 5 are obtained simultaneously.
  • the scanning registers 1, 4 and 6 are set to the serial mode. (A selection signal Sc of low level is outputted.)
  • the two processed data are outputted serially from the output terminal 84. This procedure takes 15 clocks. The two data together with the test pattern data D1 and D2 supplied to the input terminal 83 are analyzed. The time required in all those steps is 35 clocks in total, which is decreased compared with the case of FIG. 4.
  • the time required for the test is reduced since the first and second circuits 2 and 5 to be tested are operated simultaneously.
  • the second and third scanning registers 4 and 6 receive the processed data simultaneously through the operation of the register 3 and accordingly those data can be synchronously handled and outputted in response to the clock signal ⁇ .
  • the register 3 may be connected between the first scanning register 1 and the first circuit 2 to be tested.
  • the present invention is not limited thereto. More specifically, the present invention is applicable to verify operation of a plurality of semiconductor integrated circuits (used in a print circuit board for example).
  • the present invention is applicable to other cases of using more than two circuits to be tested provided by suitable increase of the number of the registers 3.
  • FIG. 8 is a block diagram showing simplified connection by which the present invention is generally applied to the case of using more than two circuits to be tested in a semiconductor integrated circuit.
  • the semiconductor integrated circuit 8 comprises circuits 2A to 2Z to be tested having different processing periods, a plurality of scanning registers 1a to 1z connected thereto, and registers 3A, 3C and 3D connected to the circuits to be tested having shorter processing periods (for example, the circuits 2A, 2C and 2Z).
  • the parallel input and output terminals of the respective circuits are shown as a simplified manner and connections for the selection signal Sc and the clock signal ⁇ are omitted from the illustration. From FIG. 8, it is easily understood that the present invention is applicable to a semiconductor integrated circuit having more than two circuits to be tested.
  • the circuit device comprises: a plurality of circuits 2 and 5 to be tested including at least one circuit 2 operated for a different processing period; a plurality of scanning registers 1 and 4 having parallel and serial inputs and parallel and serial outputs and operating in either the parallel mode or the serial mode; and an output timing regulation circuit 3 connected to the circuits 2 and 5 to be tested operated for different processing periods to regulate output timing to output the processed signals simultaneously from the pairs each constituted by one of the circuits 2 and 5 to be tested and one of the scanning registers 1 and 4.
  • a testing signal is supplied externally to each of the scanning registers 1 and 4. All the circuits 2 and 5 to be tested are operated simultaneously upon receipt of the respective testing signals. Although the circuit 2 to be tested operated for the different processing period exists, the processed testing signals are outputted simultaneously from all the pairs through the output timing regulation circuit 3 connected thereto. Since all the circuits to be tested are operated simultaneously and in parallel, the time required for the test is saved.
  • the method of operating the circuit device 8 according to the present invention having the plurality of circuits 2 and 5 to be tested including the circuit 2 operated for the different processing period, and the plurality of scanning registers 1 and 4 connected to the circuits 2 and 5 to be tested to constitute pairs and operating in either the parallel mode or the serial mode comprises the steps of: applying the testing signals to all the scanning registers 1 and 4 (steps 101 and 102), operating simultaneously the circuits 2 and 5 to be tested in all the pairs upon receipt of the testing signals from the scanning registers (steps 103 and 104), and regulating output timing so that the processed testing signals are outputted simultaneously from all the pairs (step 105).
  • the present invention is applied to a semiconductor integrated circuit as the circuit device.
  • the testing time required for verifying operation of the semiconductor integrated circuit is reduced.

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US07/195,636 1987-05-19 1988-05-17 Circuit device having a self-testing function and a testing method thereof Expired - Lifetime US4829237A (en)

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US4975602A (en) * 1990-02-23 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Logic level data conversion system
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US4967142A (en) * 1988-05-27 1990-10-30 U.S. Philips Corporation Electronic module comprising a first substrate element with a functional part, and a second substrate element for testing an interconnection function, socket, substrate element and electronic apparatus therefor
US5113401A (en) * 1989-07-07 1992-05-12 International Business Machines Corporation Block coding scheme for fractional-bit transmission
US4975602A (en) * 1990-02-23 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Logic level data conversion system
US5295079A (en) * 1991-07-18 1994-03-15 National Semiconductor Corporation Digital testing techniques for very high frequency phase-locked loops
US5809039A (en) * 1992-09-24 1998-09-15 Hitachi, Ltd. Semiconductor integrated circuit device with diagnosis function
US8004298B2 (en) * 1997-11-03 2011-08-23 Texas Instruments Incorporated IC with first and second distributors collectors and scan paths
US20110068814A1 (en) * 1997-11-03 2011-03-24 Texas Instruments Incorporated Parallel scan distributors and collectors and process of testing integrated circuits
US20110102013A1 (en) * 1997-11-03 2011-05-05 Texas Instruments Incorporated Parallel scan distributors and collectors and process of testing integrated circuits
US8018241B2 (en) * 1997-11-03 2011-09-13 Texas Instruments Incorporated Logic applying different bit positions to respective scan paths
US20110273204A1 (en) * 1997-11-03 2011-11-10 Texas Instruments Incorporated Parallel scan distributors and collectors and process of testing integrated circuits
US8324917B2 (en) * 1997-11-03 2012-12-04 Texas Instruments Incorporated Logic applying serial test bits to scan paths in parallel
US20130043899A1 (en) * 1997-11-03 2013-02-21 Texas Instruments Incorporated Parallel scan distributors and collectors and process of testing integrated circuits
US8749258B2 (en) * 1997-11-03 2014-06-10 Texas Instruments Incorporated Parallel scan paths with three bond pads, distributors and collectors
US6134685A (en) * 1998-03-16 2000-10-17 Advanced Micro Devices, Inc. Package parallel test method and apparatus
US6196677B1 (en) * 1998-05-20 2001-03-06 Advanced Micro Devices, Inc. Parallel test method

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DE3817143A1 (de) 1988-12-08
JPS63286781A (ja) 1988-11-24

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