US4760459A - Binary data compression and expansion processing apparatus - Google Patents

Binary data compression and expansion processing apparatus Download PDF

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US4760459A
US4760459A US07/018,281 US1828187A US4760459A US 4760459 A US4760459 A US 4760459A US 1828187 A US1828187 A US 1828187A US 4760459 A US4760459 A US 4760459A
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data
image data
bit position
input
code
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Fumitaka Sato
Shigekazu Sumita
Masayoshi Murayama
Hiromichi Tome
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Toshiba Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction
    • H04N1/411—Bandwidth or redundancy reduction for the transmission or storage or reproduction of two-tone pictures, e.g. black and white pictures
    • H04N1/413—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information
    • H04N1/417—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information using predictive or differential encoding
    • H04N1/4175—Systems or arrangements allowing the picture to be reproduced without loss or modification of picture-information using predictive or differential encoding involving the encoding of tone transitions with respect to tone transitions in a reference line
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G06T9/005—Statistical coding, e.g. Huffman, run length coding

Definitions

  • the present invention relates to a binary data compression and expansion processing apparatus which can perform high-speed expansion processing of binary data and, more particularly, can perform parallel pipeline processing of the binary data by a two-dimensional coding method.
  • coding methods such as the MH method, the MR method, and the M 2 R method, recommended by the CCITT, are internationally standardized, and are widely adopted.
  • the M 2 R method has the highest image compression efficiency.
  • the M 2 R method is well known as a coding method for Group IV facsimile systems. In this method,
  • EOL End-Of-Line
  • a k parameter is set to be infinite
  • a data compression ratio can be improved over that of the MR method. If a transmission error, if any, occurs, the error is sequentially transmitted to subsequent scanning lines as a principal problem. In order to prevent this, one-dimensional coding scanning lines are inserted in compression processing.
  • the k parameter is the number of two-dimensional coding scanning lines between these one-dimensional coding scanning lines.
  • a conventional binary data compression and expansion processing apparatus was realized in software, using a general-purpose microcomputer in order to perform expansion processing of encoded data according to these methods.
  • this processing there is no problem when such an apparatus is applied to a facsimile system whose data transmission rate is limited to 9600 bps.
  • a good man-machine interface for example, a page response time of 1/2 sec or less, cannot be achieved. Therefore, when the sequential expansion processing is executed in accordance with the M 2 R method, the operating speed is considerably reduced, when compared with the MH method.
  • decoding and generation processing can be parallel-performed by separate hardware arrangements.
  • the next code is decoded, and the entire processing can be then pipelined.
  • the M 2 R method has the following problems.
  • the starting run of each line is always a white run and must be decoded to be white pixels.
  • an EOL code is used. Therefore, a decoding processing section which performs the advanced processing can detect the beginning of the next line due to the presence of an EOL code, regardless of progress of generation processing by a generation processing section.
  • a binary data compression and expansion processing apparatus which can efficiently execute image data generation processing, comprising:
  • counter means (42) for holding an input data corresponding to a run length data of the code, for counting down the held data by data corresponding to a first predetermined length for each generating step, for holding the counted-down data, and for outputting the held data;
  • generating means (46) for inputting the held data in the counter means (42) and control data, and for generating unicolor image data having the first predetermined length and a color designated by the control data, and for outputting the generated unicolor image data as combining image data;
  • holding loop means (50, 60, 62, 64) for generating image data by combining the combining image data, after a remained image data held therein in accordance with input generation bit position data in one generating step, for outputting the generated image data in a reagion for the second predetermined length beginning from a leading bit thereof as an interest block, when it is detected that the length of the generated inmage data is the first predtermined length or more, and for holding the remained image data for the next generating step, the generation bit position data indicating a bit position within the interest block where the next combining image data is to be combined; and
  • bit position detecting means (56, 100, 112, 114, 122) for determining a bit position where the next combining image data is to be combined in accordance with the held generation bit position data and the held data from the counter means (42), for holding the updated generation bit position data in accordance with the deetermined bit position, for outputting the generation bit position data held therein, and for detecting that the generated image data has the first predetermined length based on the determined bit position.
  • the position of point b1 is detected in image data on a reference line, and image data to be generated is processed in parallel therewith, thereby improving an expansion processing speed.
  • FIG. 1 is a block diagram of a binary data compression and expansion processing apparatus according to the present invention
  • FIG. 2 is a block diagram showing the arrangement of a decoding section and an encoding end processing section in a decoding processing section shown in FIG. 1;
  • FIG. 3 is a block diagram showing the arrangement of a counter section and a generation section in a generation processing section shown in FIG. 1;
  • FIG. 4 is a block diagram showing the arrangement of a reference line address generator and an EOL detector in the decoding processing section shown in FIG. 1;
  • FIG. 5 is a block diagram of an a1b1 detector in the generation processing section shown in FIG. 1;
  • FIG. 6 is a detailed diagram of a b1 detector shown in FIG. 5;
  • FIGS. 7A to 7D are views showing states of image data of a reference line and a generation processing line in expansion processing.
  • the apparatus of this embodiment comprises binary data processing controller 1 for controlling the operation of the entire apparatus, compression and expansion processing section 2 for generating binary image pattern data when input binary data is a code and for generating a code when input binary data is image pattern data, reference line data storage section 4 for storing reference line data, reference line address generator 3 for generating address data for storage section 4, and clock generator 5 for generating control clocks.
  • Controller 1 has flip-flop FBLKP (not shown) for designating a color of image data to be generated, and flip-flop FODRDY (not shown) for causing register RODT to output generated image data.
  • Flip-flop FBLKP designates a black pattern when it is set to "1", and designates a white pattern when it is set to "0".
  • Compression and expansion processing section 2 comprises decoding processing section 7 for generating run length data when input binary data is a code, and generation processing section 8 for generating binary image pattern data processed in accordance with the run length data.
  • Decoding processing section 7 comprises EOL detector 11 for checking if generation processing is completed to the end of a line and for detecting an EOL code under a given condition, encoding end processing section 12 used to generate an EOL code during compression processing, and decoding section 13.
  • Generation processing section 8 comprises counter section 14 for latching an output from decoding section 13 and counting the number of processed bytes, generation section 15 for generating binary data processed in accordance with data from counter section 14, and a1b1 detector 16 for detecting points a1 and b1.
  • Clock generator 5 for generating clocks is connected to controller 1. Controller 1 controls operation timings of decoding processing section 7, generation processing section 8, and reference line address generator 3 in accordance with the clocks from generator 5, and outputs a necessary instruction upon progress of processing.
  • FIG. 2 shows encoding end processing section 12 and decoding section 13 of decoding processing section 7.
  • EOL detector 11 will be described later with reference to FIG. 4 together with reference line address generator 3.
  • Decoding section 13 is constituted by a circuit shown in FIG. 2, excluding encoding end processing section 12.
  • One-byte data is input to and latched by latch 22 from an input data bus.
  • Binary data latched by latch 22 is inverted by inverter 24, and is then input to register 26 and EOL detector 11 as data K.
  • Register 26 shifts previously input byte data RDTI15-08 to be data RDTI07-00 in accordance with a control signal from controller 1, latches new input data as data RDTI15-08, and holds them as 16-bit data together with data RDTI07-00.
  • 16-bit register data RDTI15-00 is output to funnel shifter 30 via encoding end processing section 12.
  • Data RDTI07-00 is output to reference line data storage section 4 as byte data F.
  • Decoding pointer 36 indicates an LSB (Least Significant Bit) position of a code to be decoded or a part of the code to be extracted next from register data RDTI15-00 input to funnel shifter 30.
  • An indication value from decoding pointer 36 is supplied to funnel shifter 30 in accordance with a control signal from controller 1.
  • Funnel shifter 30 generates 9-bit output LSHT08-00 obtained by left-shifting data RDTI15-00 by the indication value from decoding pointer 36, and outputs it to selector 31.
  • data LSHT04-00 of output data LSHT08-00 is output to generation processing section 8 as data G.
  • Data LSHT08-00 is added to data X, corresponding to data LSHT10-09, from controller 1, and is output to selector 31 as 11-bit data.
  • Selector 31 receives data Y, corresponding to data LSHT08-06 or LSHT08-07, from controller 1. These input data are selected in response to a control signal from controller 1, and are output to decoder ROM 32 as 11-bit address data.
  • data X is supplied to decoder ROM 32.
  • Decoder ROM 32 outputs 16-bit data DROM15-00. More specifically, as data DROM07-00, input binary data is output in the case of compression processing, and run length data is output in the case of expansion processing. If data indicating an actual run length, i.e., a color change point is expressed by ⁇ in two-dincensional code, run length data output from decoder ROM 32 is given as ( ⁇ -4). Data I is supplied to processing section 8. As data DROM11-08, data indicating the significant data length, i.e., the length of processed data of input binary data, is output. As data DROM15-12, control data H for designating the next state, i.e., data associated with encoded data to be decoded next in an expansion processing is output.
  • Data DROMll-08 is output to adder 34.
  • adder 34 receives data of decoding pointer 36. Therefore, data DROM11-08 is added to the data from decoding pointer 36, and the summed data is output to selector 38.
  • Selector 38 also receives data D, which is used in compression processing and is not used in expansion processing, from a1b1 detector 16. Therefore, when expansion processing is performed in accordance with a control signal from controller 1, the summed data again becomes the content of decoding pointer 36. In this manner, pointer 36 indicates an LSB position of a code next to the decoded code.
  • Controller 1 outputs a control signal to register 26 in accordance with data J from adder 34.
  • Register 26 left-shifts data RDTI15-08 in units of bytes to be data RDTI07-00 in accordance with the control signal from controller 1.
  • New byte data latched by latch 22 is latched in the data RDTI15-08 portion of register 26 in accordance with a control signal from controller 1.
  • the lower 3 bits of the summed data of adder 34 are output to pointer 36, so that the LSB position of a code to be decoded is always present in data RDTI07-00 of register 26.
  • Counter section 14 and generation section 15 of generation processing section 3 will be described in detail with reference to FIG. 3.
  • Counter section 14 comprises selectors 40 and 44, and RL counter 42.
  • Generation section 15 is constituted by a circuit shown in FIG. 3 excluding counter section 14.
  • Decoding result I from decoder ROM 32 is input to selector 40.
  • Selector 40 also receives data L from controller 1. These data are selected in response to a control signal from controller 1, and are output to RL counter 42. Of the output data from selector 40, a 02-00-bit portion is also output to selector 44.
  • RL counter 42 is a counter having a 12-bit length, and latches data from selector 40 at a predetermined position in accordance with a control signal from controller 1. RL counter 42 counts down in accordance with count pulses from controller 1 using the output data from selector 40 as a preset value, and outputs the count, to selector 44 and a1b1 detector 16 as data B.
  • the output from RL counter 40 is also output to controller 1 as data M in order to certify if the number of processing operations determined by the decoded code is completed.
  • Selector 44 receives an output from counter 42, the output from selector 40, and data A from a1b1 detector 16, and selects one of them in response to a control signal from controller 1 to output the selected data to encoder ROM 46.
  • Encoder ROM 46 receives data N from controller 1, which includes data from flip-flop FBLKP for color designation and data indicating expansion or compression processing. Encoder ROM 46 receives data from selector 44 and data N from controller 1 as address data, and outputs 8-bit data EROM07-00 to selector 48. In data EROM07-00, data EROM07-05 is supplied to adder 52. A circuit constituted by adder 52, selector 54, and image pointer RBPQ 56 is operated in the same manner as the corresponding circuit of decoding processing section 7. More specifically, image pointer RBPQ 56 outputs an indication value which is added to data EROM07-05 by adder 52 upon completion of processing. The sum is then output to selector 54.
  • Selector 54 receives data C from detector 16, and selects it in accordance with a control signal from controller 1 to serve as the indication value of image pointer RBPQ 56. As a result of addition of adder 52, if 2 3 bits are "1", this is signaled to controller 1 by means of data O.
  • Selector 48 receives data EROM07-00 and data G from decoding processing section 7 via latch 58, and selects one of them in response to a control signal from controller 1. The selected result is output to barrel shifter 50. Barrel shifter 50 rotates input data in accordance with the indication value from image pointer RBPQ 56 and outputs it to selector 60. At the same time, shifter 50 outputs the processed data to register 62 as data RODT15-08. One of data RODT07-00 and data RODT15-08 is selected by selector RRSEL 64 in accordance with a control signal from controller 1, and the selected data is input to selector 60. Selector 60 generates an output in accordance with the indication value from image pointer RBPQ 68 as data RODT07-00.
  • Register 62 shifts data RODT15-08 to be data RODT07-00 in accordance with a control signal from controller 1.
  • Data RODT07-00 and data RODT15-08 are output to selector RRSEL 64.
  • Data RODT07-00 is output to reference line data storage section 4 as data P, and at the same time, is output to inverter 66 similar to inverter 24, and is finally output onto an output data bus.
  • reference line address generator 3 EOL detector 11 of decoding processing section 7, and reference line data storage section 4 will be described with reference to FIG. 4.
  • EOL detector 11 of decoding processing section 7 comprises stop address register 80, comparator 90, and EOL detector 81.
  • Reference line address generator 3 comprises address counter 82, adder 84, selector 86, and address register 88.
  • Reference line data storage section 4 comprises selector 92 and reference line buffer RAM 94.
  • Stop address register 80 latches, in advance, one-line run length data, and outputs upper 10-bit data to comparator 90.
  • Address counter 82 receives data Q from controller 1. Data Q is input to counter 82 each time one-byte binary data processing is completed, and counter 82 accumulates data Q until the one-line processing is completed. Therefore, an output from address counter 82 indicates the byte position to which binary data processing has progressed on the corresponding processing line.
  • Address counter 82 is reset in response to a control signal from controller 1 upon completion of one-line processing, and restarts counting when a new line's processing is started.
  • a count value of address counter 82 is output to comparator 90, selector 86, and adder 84.
  • Comparator 90 also receives run length data for one line from stop address register 80 in units of bytes, and compares it with the count value of address counter 82. When a coincidence is found therebetween, this means that image generation has reached a byte position before the end of the corresponding processing line. At this time, data T is output to controller 1.
  • Adder 84 receives data R from controller 1, and adds it to the count value from address counter 82 to output the sum to selector 86.
  • Selector 86 selects address data from address counter 82 and address data from adder 84 in response to a control signal from controller 1, and outputs the selection result to address register 88.
  • Address register 88 also receives data S from controller 1, and outputs it to reference line buffer RAM 94 together with the output from selector 86.
  • Reference line buffer RAM 94 stores image data on a reference line, and image data on the corresponding processing line for processing of the next line. Therefore, image data for two lines are stored in RAM 94, and data S is supplied to address register 88 from controller 1 in order to switch designation memory areas, i.e., to determine which area is to be selected.
  • Selector 92 receives input byte image data F, i.e., data RIDT07-00 via encoding end processing section 28, and byte data P, i.e., processed image data RODT07-00, and selects one of them in response to a control signal from controller 1, thereby storing the selection result in reference line buffer RAM 94.
  • selector 86 selects the output data from adder 84, and upon storage of reference line data, selects the output data from address counter 82 to output it.
  • EOL detector 81 detects an EOL code when an error occurs in, e.g., detector processing section 7 or generation processing section 8. Detector 81 receives data K from decoding processing section 7, and signals detection of an EOL code to controller 1 by means of data Z.
  • a1b1 detector 16 of generation processing section 8 The arrangement of a1b1 detector 16 of generation processing section 8 will now be described with reference to FIG. 5. a1b1 detector 16 is frequently used in a vertical mode and a pass mode in a two-dimensional mode.
  • Register 96 shifts data REF07-04 in data REF07-00 to be data REF-4--1 and data REF15-08 to be data REF07-00 in units of bytes, so as to latch data from reference line buffer RAM 94 as data REF15-08.
  • b1 detector 102 receives data U of reference line from register 96. Detector 102 also receives data A1 from controller 1 to detect a color change point. Delector 102 informs absence b1 point to controller 1 by data A2.
  • a1 detector 104 receives data F from encoding end processing section 28.
  • b1 and a1 detectors 102 and 104 receive an indication value from a0 pointer RBPA 100, and respectively detect positions a1 and b1 of pixels having changes on an encoding line and a reference line on the right side of point a0, i.e., ahead of point a0 in the processing direction, on register 96.
  • Position b1 detected by b1 detector 102 is supplied to subtractor 120 and selector 108. "+4" is added to position b1 in association with register 96.
  • Position a1 detected by a1 detector 104 is supplied to selectors 116 and 114.
  • Selector 116 selects output data from data from a1 detector 104 or data "+4" from controller 1, and outputs the selected data to subtractor 120.
  • Subtractor 120 outputs its calculation result to generation processing section 8 as data A.
  • Selector 108 receives the indication value from a0 pointer 100 and output b1 from b1 detector 102.
  • Selector 110 receives data "-4" from controller 1 and data B, as output RLCNT from RL counter 42, from generation processing section 8.
  • Selectors 108 and 110 respectively select their outputs in response to a control signal from controller 1, and output them to adder A01BP 112.
  • Adder A01BP 112 outputs the sum to selector 114.
  • Selector 114 also receives detection result a1 from a1 detector 104, the indication value from a0 pointer 100, and data W from controller 1, and selects its output in response to a control signal from controller 1.
  • the output from selector 114 is supplied to generation processing section 8 as data C and to decoding processing section 7 as data D.
  • the output from selector 114 is also latched by a0 pointer RBPA 100 as the indication value.
  • the indication value of a0 pointer 100 is compared with data E from address register 80 by comparator 106, and the comparison result is output to controller 1 as data V.
  • Comparator 122 also receives a value "8" indicating a data processing size from controller 1, and makes a comparison between the two inputs. The comparison result is supplied to controller 1 as signal SNAGR8 when the output from adder A01BP112 is 8 or more.
  • b1 detector 102 is configurated as shown in FIG. 6. This circuit checks a color change point and a white run is processed as "0" and a black run is processed as "1". For corresponding bits ahead of point of interest a0 in the processing direction, "1" is supplied as a mask pattern.
  • Reference line data -4-11 input to b1 detector 102 each is input to one terminal of exclusive OR gates 208, respectively. The other terminal of the exclusive gates 208 receives a color control signal. More specifically, the color control signal is "0" when a color change point from a white run to a black run iws checked and is "1" when a color change point from a black run to a white run is checked.
  • Data -4-11 from exclusive OR gates 208 is input to corresponding NAND gates 211 bit by bit.
  • Each of NAND gates 211 also receives the a mask pattern and data from a previous bit.
  • 2nd-bit data inverted by corresponding inverter 210 is input thereto.
  • Each of NAND gates 211 calculates a logical product of these inputs to detect a color change in pixel components at the corresponding bit position. Therefore, if all the associated bits are subjected to the same processing, a change color point of pixel components ca be easily and immediately detected.
  • inverted previous bit data is input to NAND gate 211 respectively is that points 201 and 202 must not detected as color change point b1 of a reference line in the case of a reference line and a processing line shown in FIG. 7A. That is, a condition that the color of dot on the left side of the corresponding bit is an opposite color is added. Thus, black dots 201 and 202 can be prevented from being detected as point b1.
  • control data including data for determining the MH, MR, or M 2 R method
  • the control data includes data indicating a run length for one line.
  • Stop address register 80 stores the run length data for one line.
  • all the bits of image data on the reference line at the beginning of a page are white or "0".
  • an EOL code is first detected by EOL detector 81 to start expansion processing.
  • a code encoded by the M 2 R method is input to decoding processing section 7 via an input data bus in units of 8 bits, i.e., 1 byte, after the aforementioned initialization is performed, and is latched by latch 22 in accordance with a control signal from controller 1.
  • a leftmost bit is bit "0".
  • a rightmost bit is bit "0". Therefore, the input binary data mus be inverted.
  • the input binary data is thus inverted by inverter 24, and is then output to register 26 and EOL detector 11.
  • register 26 previously input byte data RDTI15-08 is shifted to data RDTI07-00 in accordance with a control signal from controller 1, and new input data is latched as data RDTI15-08 and is held as 16-bit data together with data RDTI07-00. In this manner, at the beginning of a page, 2-byte binary data is input.
  • 16-bit register data RDTI15-00 is output to encoding end processing section 28. This circuit is operated only in compression processing, and simply allows data to pass therethrough in expansion processing. Therefore, 16-bit register data RDTI15-00 is output to funnel shifter 30 via processing section 28.
  • Decoding pointer 36 indicates the LSB position of a code, to be extracted next, from register data RDTI15-00 input to funnel shifter 30.
  • Funnel shifter 30 generates 9-bit output LSHT08-00 obtained by left-shifting data RDTI15-00 by the number of bits indicated by an indication value from pointer 36. For example, if the value of pointer 36 is "3", funnel shifter 30 selects data RDTI11-03 from input data RDTI15-00, and outputs it as data LSHT08-00.
  • Data LSHT08-00 is added to data corresponding to data LSHT10-09 from controller 1, and the result is output to selector 31.
  • Selector 31 also receives data corresponding to data LSHT06-08 or LSHT07-08 from controller 1. These input data are selected in accordance with a control signal from controller 1, and the selected data is output to decoder ROM 32 as 11-bit address data.
  • selector 31 awaits the completion of generation processing in a state that the data LSHT08-00 is supplied.
  • selector 31 does not await the completion, a white run cannot be set for a beginning code of the next line after processing progresses up to the end of the current processing line. In this case, if decoding for the beginning code is performed, the value of decoding pointer 36 must be reset and decoding must be restarted, resulting in inconvenience.
  • an EOFB code End of Facsimile Block: the EOFB code has double EOL codes
  • processing is stopped at the EOFB code. Therefore, when an EOL code in the EOFB code is detected by EOL detector 81, decoding is performed by advanced processing in the present invention.
  • MH and MR methods use an EOL code unlike the M 2 R method, a code data can be decoded by advanced processing without a waiting the completion of current generation processing.
  • decoding processing of the M 2 R method, and even that of the MH and MR methods, can be performed at a higher speed than in a conventional apparatus.
  • Data LSHT10-00 is output to decoder ROM 32 in response to a control signal from controller 1. If data Y08-06 is selected, the 08-06-bit portion or the 08-07-bit portion of data LSHT10-00 is selected as the corresponding portion of data LSHT, and the data LSHT08-00 portion is shifted toward the MSB direction by corresponding bits to be output to decoder ROM 32. Decoder ROM 32 outputs data associated with a run length as data DROM07-00, data indicating a decoded code length as data DROM11-08, and data indicating the next state as data DROM15-12. At this time, data in the two-dimensional vertical and pass modes are output in the form of run length data ( ⁇ -4).
  • Data DROM11-08 is output to adder 34.
  • adder 34 receives data from pointer 36.
  • data DROM11-08 is added to the content of pointer 36, and the summed data is output to selector 38.
  • Selector 38 receives signal D, which is used in compression processing and is not used in expansion processing, from a1b1 detector 16.
  • the output from adder 34 is selected in response to a control signal from controller 1. Therefore, the summed data again becomes the content of pointer 36.
  • Pointer 36 indicates the LSB position of a code next to a decoded code in this manner.
  • controller 1 When 2 3 -bit data becomes "1" as a result of addition of adder 34, this is signaled to controller 1 by means of data J. This means that decoding processing for one byte is completed. Therefore, controller 1 outputs a control signal to register 26, to left-shift data RDTI15-08 to data RDTI07-00 in units of bytes. New byte data is latched by latch 22 and latched as data RDTI15-08 in register 26 in accordance with a control signal from controller 1. Pointer 36 receives the lower 3 bits of the summed data from adder 34, so that the LSB position of a code to be decoded is always present in data RDTI07-00 of register 26.
  • Generation processing section 8 receives the decoding result, i.e., run length data, as described above.
  • a decoding result i.e., run length data
  • selector 40 receives data L from controller 1, this will be described later.
  • RL counter 42 is a counter having a 12-bit length, and stores the decoding result of the make-up code in 6-bit data portion 08-03.
  • 8-bit data "00000000” or "11111111” is output from encoder ROM 46.
  • the output data is supplied to barrel shifter 50 via selector 48.
  • Generation processing section 8 has a similar circuit to decoding pointer 36 of decoding section 13.
  • Barrel shifter 50 receives data from pointer 36, so that input data is rotated and output in accordance with the data from pointer 36. However, since all the bits are "0” or "1", there is no difference if the data is rotated or not. Thus, the value of image pointer RBPQ 56 is left unchanged.
  • Selector 60 selects data from selector RRSEL 64 as data from the LSB of image data to be generated to a bit position smaller by "1" from the indication value of image pointer RBPQ 56, and selects the output from barrel shifter 50 as data from the indication value of image pointer RBPQ 56 to the MSB of the image data, thus outputting the selected data as data RODT07-00 of register 62. For example, if the indication value of pointer RBPQ 56 is "3", data from selector RRSEL 64 is selected as data RODT02-00, and data from barrel shifter 50 is selected as data RODT07-03. The data selected by selector 60 is stored as data RODT07-00 of register 62.
  • the run length of the make-up code is 8 bytes or more, and is processed in units of bytes.
  • data RODT07-00 of register 62 is output onto the output data bus through inverter 66, similar to inverter 24, in accordance with a control signal from controller 1.
  • Data RODT07-00 is also supplied to reference line storage section 4 as data P, to be stored therein at an address corresponding to the current value of address counter 88.
  • one clock is applied to address counter 82 as data Q to increment it by "1".
  • the value of counter 82 is compared with that of stop address register 80 by comparator 90 to check if the processing has progressed up to the end of the line.
  • a code encoded by the MR or MH method there is no problem since EOL codes are used.
  • Data in register 96 is shifted toward the LSB in units of bytes.
  • New reference line data is read out from storage section 4 using the sum of the value of address counter 82 and data R as an address, and is latched in register 96 as data REF15-08.
  • data a0 of a0 pointer RBPA 100 is not changed. It is checked if data RLCNT of RL counter 42 is equal to "0". When data RLCNT is not equal to "0”, data RLCNT is decremented by "1”. Whe data RLCNT is equal to "0", data M is output to controller 1 to indicate that the generation processing of the input make-up code is completed. If not completed, data RLCNT from RL counter 42 is again supplied to encoder ROM 46 through selector 44. Processing is repeated in the same manner as described above until the output RLCNT from RL counter 42 becomes equal to "0 ".
  • controller 1 supplies to selector 40 the code of a run length of 2560 and the number of the repeated code. Whe selector 40 selects data L, the same processing as that for the make-up code is performed. When the generation processing for the run length of 2560 is completed once, the number of the repeated code is decrimented by "1", and the same processing is repeated until the content of RL counter 42 is equal to "0".
  • the decoding result is input to the 05-00 portion of RL counter 42 through selector 40.
  • the 05-03 poriton of RL counter 42 is processed in the same manner as that of byte data in the generation processing of the make-up code.
  • Upon completion of the processing of byte data remaining data 02-00, less than one byte, is processed.
  • Data 02-00, less than one byte, is output to selector 44, and is selected thereby to be input to encoder ROM 46.
  • Data 02-00 is also output to albl detector 16 as data B.
  • Image data is generated in the same manner as the generation processing for a one-byte run length.
  • data B is supplied from RL counter 42 to selector 110.
  • Data B is selected by selector 110 and is supplied to adder 112.
  • Selector 108 selects data a0 from a0 pointer RBPA 100, and supplies it to adder 112.
  • the sum from adder 112 is supplied to comparator 122 and image pointer RBPQ 56 through selectors 114 and 54. As a result, the value of image pointer RBPQ 56 is updated.
  • comparator 122 determines that the output from adder 112 is "8" or more, it is signaled to controller 1 by signal SNAGR8 that one-byte data processing is completed.
  • register 62 outputs data RODT07-00 onto the data bus in response to a control output signal from controller 1, and also outputs it to storage section 4 as data P.
  • next image data is awaited.
  • data RODT07-00 of register 62 is supplied to selector 60 through selector RRSEL 64.
  • the above operation can be attained for an MH code portion of a horizontal mode code among codes encoded by the MH method and those encoded by the MR and M 2 R methods.
  • Run length data from decoding section 13 is loaded to RL counter 42.
  • the content of RL counter 42 is also updated to ( ⁇ -4).
  • flip-flop FBLKP (not shown) in controller 1 for designating the color is reset or set in accordance with the color of a run associated with the run length data.
  • the data hold loop including register 62 one-byte image data including point a0 of a current processing line is fed back to the data 07-00 portion of register 62 through selector RRSEL 64 and selector 60. The bit position of point a0 in the byte data is loaded to al pointer RBPA 100 and image pointer RBPQ 56.
  • the 3rd bit of a0 pointer RBPA 100 is "0".
  • Image data on a reference line has been loaded to register REF 96.
  • Data REF00-07 of register 96 corresponds to data RODT07-00 of register 62 in which the bit position of point a0 is included.
  • the expansion processing of a VL(2) code will be described, wherein point a0 corresponds to the 2nd bit of data RODT07-00 and a reference line has image pattern data shown in FIG. 7A.
  • b1 detector 102 constituted as shown in FIG. 6.
  • Adder A01BP 112 receives output "12" from b1 detector 102 through selector 108 and output RLCNT “6” from RL counter 42 through selector 110, and calculates 12+(-6) and outputs the result "6". This output is selected by selector 114, and is set in a0 pointer RBPA 100.
  • Selector 60 selects data from register 62 as data from the LSB of image data to be generated to a bit position on the left side of a bit position indicated by a0 pointer RBPA 100, and selects data from barrel shifter 50 as data from the bit position indicated by the a0 pointer to the 7th bit.
  • data of a0 pointer RBPA 100 is latched in pointer 56 in this manner, an image pattern which is completed in the previous step from the hold loop formed by selector RRSEL 64 is fed back and loaded to a data portion on the left side of point a0, and new image data is loaded to a data portion from point a0 to the MSB (the 15th bit) of data RODT, regardless of the position of point a1, as shown in FIG.
  • the output of adder A01BP 112 is connected to comparator 122 for checking if the output from adder 112 is 8 or more.
  • signal SNAGR8 is generated from comparator 122. If this signal is not generated, this means the image data for the run length data to be currently processed is generated only in data RODT00-07 of register 62. Therefore, controller 1 operates to complete generation processing for this run length data within this step.
  • FIG. 7A illustrates the state when this machine cycle is completed.
  • points a0, a1, and b1 are indicated in view of the generated run.
  • This state corresponds to the initial state of the generation processing for the next black run.
  • point a1 in FIG. 7A serves as point a0, and point b1 falls outside the range of FIG. 7A.
  • Generation of a black run in the next machine cycle and thereafter will be described below.
  • point b1 is not detected. This is informed to controller 1 by data A2.
  • image generation is performed regardless of the presence/absence of point b1 detection in the same manner as in the previous cycle, and all the bits from the 6th bit to the 15th bit of data RODT15-00 of register 62 are set to "1".
  • a data portion consisting of all "1" bits is generated from a point indicated by a1 toward the right.
  • the content on the left side of a point indicated by a0 pointer RBPA 100, i.e., data portion RODT 06-00 of data RODT15-00 of data remains unchanged upon operation of the hold loop.
  • one-byte image data of data RODT07-00 is completed, one-byte image data on the right side thereof is generated in the next processing step. Preparation therefor is performed in this processing step. More specifically, the content of register 96 is left-shifted by one byte, so that the next image data (of the reference line) read out from reference line buffer 94 is loaded to data REF08-15. In other words, the content of data REF04-07 is loaded to data REF-4--1, and the content of data REF08-15 is loaded to data REF00-07, so as to realize the one-byte shift operation.
  • Selector 114 receives the content of a0 pointer RBPA 100, and calculates "a0-8". Selector 114 selectively supplies the calculated result to a0 pointer RBPA 100. In this, 8 yields -2, and -2 loaded to a0 pointer RBPA 100 is 6, 6-8 yields -2, and -2 is loaded to a0 pointer RBPA 100. The countent of image pointer RBPQ 56 is left unchanged until the generation processing for the corresponding run is completed.
  • FIG. 7C illustrates a state when this processing step is completed and control enters the next processing step. Since data REF is illustrated at the same position in the drawings, it can be understood that image pattern data is shifted by one byte, as compared to FIG. 7B. This is because register 62 holds an already-processed image byte in data RODT07-00. Selector RRSEL 64 is driven by control flip-flop FODRDY described above, so that data RODT15-08 is selected and supplied to the hold loop of selectors 64 and 60 thus compensating for a deviation between data REF and RODT.
  • byte data RODT08-15 in register 62 in FIG. 7C is used for this generation processing step.
  • the data RODT15-08 is input to selector 60 through selector 64.
  • the byte image data in this processing step is generated in the same manner as described above. That is, in the processing step starting from the state shown in FIG. 7C, point b1 is not detected, and image generation continues for one more byte.
  • the 6-bit "1" data portion i.e., data RODT13-08 of the left portion of 8 bits indicated by data RODT15-08 in FIG.
  • Data REF15-00 of register 96 is left-shifted by one byte, and -4 is input to a0 pointer RBPA 100, in the same manner as described above. This result is shown in FIG. 7D.
  • the output from adder A01BP 112, i.e., 6, is set in a0 pointer RBPA 100 and image pointer RBPQ 56. Although all the bits of data RODT15-00 are "1", since the output from adder A01BP 112 is 7 or less, control flip-flop FODRDY is reset, and this image byte is not output at this time, but used for generation processing of image data for the next run (white run).
  • generation processing of code data encoded by the vertical mode is performed parallel to detection of point b1 on the reference line, thus greatly increasing the generation processing speed.
  • the generation processing of image data from point a0 to b1, shown in FIG. 7A is performed in the same manner as in the case of a V(0) code.
  • a reference color for detecting white/black inversion of b1 detector 102 is inverted, and the same operation as for a V(0) code is performed while the color of an image pattern to be generated is left unchanged, thus generating image data from point b1, shown in FIG. 7A, to b1, shown in FIG. 7D.
  • Image pattern data is input to latch 22 from an input data bus and is latched thereby.
  • the input image data is input to register 26 through inverter 24.
  • register data RDTI07-00 is output to reference line storage section 4 as reference line data for the next processing line, and is stored therein in accordance with data from address register 88.
  • image data held in data portion RDTI 07-00 is output to a1 detector 104, and data 320(2560 ⁇ 8) is preset in RL counter 42.
  • the a1 point, detected by a1 detector 104, is output as data D to selector 38 via selector 114.
  • Controller 1 outputs data Q to address counter 82 in the same manner as in expansion processing to update address data. Also, the content of RL counter 42 is count down At the same time, the contents of register 96 is shifted to the left by one byte in the same manner as in expansion processing. New reference line data read out from storage section 4 is output to register 96 and latched as REF 15-08. The value of pointer 100 is not changed.
  • a count pulse is input to RL counter 42 from controller 1 in accordance with data DROM 15-12 from decoder ROM 32, upon completion of processing for one byte, thereby counting down RL counter 42 as shown in ⁇ 21 of FIG. 7.
  • a color change point a1 is detected by a1 detector 104, i.e., when the content of data LSHT08-00 is not "00000000" or "11111111"
  • the count result of RL counter 42 is supplied to encoder ROM 46 via selector 44.
  • Data N is also supplied to encoder ROM 46, thus generating a make-up code.
  • the generated make-up code is supplied via selector 48 to barrel shifter 50.
  • the generated make-up code is rotated in barrel shifter 50 in accordance with the indication data of image pointer 56.
  • the rotated code is supplied to data RODT 15-08 portion of register 62 and is also supplied to selector 60.
  • selector 60 the rotated code is combined with an output of selector 64 in the same manner as in the expansion processing, in accordance with the indication data of image pointer 56.
  • the length of the generated make-up code is output from encoder ROM 46 to adder 52 as data EROM07-05 to add it to the indication data. Again the sum is the indication data of pointer 56.
  • data RODT07-00 is output onto a output data bus.
  • the horizontal mode codes encoded by the MR and M 2 R methods are processed in the same manner as compression processing of the MH code, except that the identification code of the horizontal mode is added before the first make-up code in accordance with data N from controller 1.
  • Detected a1 and b1 are supplied to subtractor 120 and an output from subtractor 120 is output as data A to encoder ROM 46 via selector 44.
  • encoder ROM 46 the pass mode code or the vertical mode code is generated, and is processed in barrel shifter 50, selector 60, and image pointer 56, etc., in the same manner as in the horizontal mode code.
  • b1 is selected in selector 114 and is supplied to a0 pointer 100 and decoding pointer 36 via selector 38 as data D.
  • the following processing is the same as in expansion processing.

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US4839738A (en) * 1987-04-22 1989-06-13 Advanced Micro Devices, Inc. Apparatus for decoding facsimile coded data to image data with coding and reference line windowing and color change detection
US4860114A (en) * 1986-11-29 1989-08-22 Hitachi, Ltd. Method and apparatus for expanding two-dimensional compressional code
US5032838A (en) * 1989-04-06 1991-07-16 Kabushiki Kaisha Toshiba Variable length code parallel decoding apparatus and method
US5065445A (en) * 1987-07-20 1991-11-12 Dainippon Screen Mfg. Co., Ltd. Apparatus for expanding and formatting runlength data for multiple exposure beams
WO1996025010A2 (fr) * 1995-02-03 1996-08-15 Philips Electronics N.V. Codage des couleurs d'images video
US5812146A (en) * 1985-12-13 1998-09-22 Canon Kabushiki Kaisha Image processing apparatus using compressed data processing
US5912990A (en) * 1995-03-08 1999-06-15 Canon Kabushiki Kaisha Image generation method and apparatus
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US6574364B1 (en) 1998-03-31 2003-06-03 Koninklijke Philips Electronics N. V. Pixel color value encoding and decoding
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US5812146A (en) * 1985-12-13 1998-09-22 Canon Kabushiki Kaisha Image processing apparatus using compressed data processing
US5861892A (en) * 1985-12-13 1999-01-19 Canon Kabushiki Kaisha Image processing apparatus using compressed-data processing
US4800441A (en) * 1986-02-28 1989-01-24 Kabushiki Kaisha Toshiba Binary data compression and expansion processing apparatus
US4860114A (en) * 1986-11-29 1989-08-22 Hitachi, Ltd. Method and apparatus for expanding two-dimensional compressional code
US4839738A (en) * 1987-04-22 1989-06-13 Advanced Micro Devices, Inc. Apparatus for decoding facsimile coded data to image data with coding and reference line windowing and color change detection
US5065445A (en) * 1987-07-20 1991-11-12 Dainippon Screen Mfg. Co., Ltd. Apparatus for expanding and formatting runlength data for multiple exposure beams
US5032838A (en) * 1989-04-06 1991-07-16 Kabushiki Kaisha Toshiba Variable length code parallel decoding apparatus and method
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US5912990A (en) * 1995-03-08 1999-06-15 Canon Kabushiki Kaisha Image generation method and apparatus
US6097429A (en) * 1997-08-01 2000-08-01 Esco Electronics Corporation Site control unit for video security system
US6574364B1 (en) 1998-03-31 2003-06-03 Koninklijke Philips Electronics N. V. Pixel color value encoding and decoding
US20040218227A1 (en) * 2003-04-30 2004-11-04 Yamaha Corporation Storage device
US7483033B2 (en) * 2003-04-30 2009-01-27 Yamaha Corporation Storage device

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DE3744791C2 (fr) 1992-01-09
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KR880002075A (ko) 1988-04-29
KR910001072B1 (ko) 1991-02-23

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