US4593266A - Analog-to-digital converter/demodulator for FM signals - Google Patents

Analog-to-digital converter/demodulator for FM signals Download PDF

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US4593266A
US4593266A US06/521,453 US52145383A US4593266A US 4593266 A US4593266 A US 4593266A US 52145383 A US52145383 A US 52145383A US 4593266 A US4593266 A US 4593266A
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delay
pulses
pulse
period
set forth
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Richard C. Palmer
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RCA Licensing Corp
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RCA Corp
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Priority to US06/521,453 priority Critical patent/US4593266A/en
Priority to IT8422202A priority patent/IT1206461B/it
Priority to KR1019840004676A priority patent/KR930001747B1/ko
Priority to FR848412487A priority patent/FR2550671B1/fr
Priority to JP59164355A priority patent/JPS6057727A/ja
Priority to GB08420028A priority patent/GB2144936B/en
Priority to DE19843429061 priority patent/DE3429061A1/de
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Assigned to RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP. OF DE reassignment RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP. OF DE ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: RCA CORPORATION, A CORP. OF DE
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/006—Demodulation of angle-, frequency- or phase- modulated oscillations by sampling the oscillations and further processing the samples, e.g. by computing techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/502—Analogue/digital converters with intermediate conversion to time interval using tapped delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/005—Analog to digital conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0064—Detection of passages through null of a signal

Definitions

  • This application relates to apparatus for demodulation and analog-to-digital conversion of a phase frequency modulated waveform.
  • I.P. Breikss describes one such device in U.S. Pat. No. 3,548,328 entitled "Digital FM Discriminator".
  • the Breikss apparatus limits the FM signal and utilizes its period to operatively control a counter. Pulses from a clock signal of uniform frequency are counted during each period of the FM signal and interpreted relative to a fixed number of counts, to determine, in normalized form a PCM signal representative of the information contained in the FM input signal.
  • This type of FM discriminator nominally requires a clock signal having a frequency at least two orders of magnitude higher than the FM signal to be demodulated if reasonable resolution is to be attained.
  • Two disadvantages are immediately apparent: (a) the creation of localized RFI and (b) the required processing speed of the counters etc. is increased to that of the clock rate.
  • the present invention overcomes the limitations imposed by the high frequency clock.
  • the present invention is a flash type ADC for FM signals, which operates on the principle of comparing successive zero crossings of the FM waveform to fixed temporal references.
  • the apparatus consists of 2 n-1 delay elements having successively greater delay times, and 2 n-1 comparators.
  • the FM waveform is applied to a one-shot multivibrator that is triggered to produce a narrow output pulse of constant duration for both positive and negative zero crossings.
  • the pulses from the one-shot are applied to the delay elements and to one input of each of the comparators. Delayed output signal from the delay elements are applied to second input connections of respective comparators.
  • the incremental delays of the 2 n-1 delay lines and the width of the one-shot output pulse are arranged so that each successive zero crossing produces an output in only one of the comparator circuits.
  • the comparators are connected to a decoder e.g. a programmed logic array (PLA) which identifies the comparator outputting signal and produces an n-bit PCM codeword which corresponds to the frequency or period defined by the lastmost two zero crossings.
  • a decoder e.g. a programmed logic array (PLA) which identifies the comparator outputting signal and produces an n-bit PCM codeword which corresponds to the frequency or period defined by the lastmost two zero crossings.
  • PLA programmed logic array
  • FIGS. 1, 4 5a and 5b are partial block-partial schematic diagrams of FM-to-digital converters embodying the present invention.
  • FIGS. 2 and 3 are waveform diagrams showing the temporal response of different points in the FIG. 1 embodiment
  • FIG. 6 is a detailed drawing of a portion of the FIG. 5 converter realized in integrated circuit form.
  • the output of the AND gate therefore provides an indication that the lastmost two pulses were separated by a period defined by the fixed delay of the delay element.
  • the combination of delay element and AND gate is a detector for pulses of a defined period. Now consider a number, n, of delay element-AND gate combinations connected to the pulse generator with each delay element having an incrementally greater delay time.
  • n is for example 256 then 256 or 2 8 different pulse periods are detectable by the 2 8 AND circuits. Finally if the 2 8 outputs from the AND gates are applied to a decoder circuit an 8-bit PCM code can be generated, each successive output codeword therefrom representing the period between the lastmost two pulses. Finally consider that the pulse generator is a ONE-SHOT responsive to the zero crossings of an analog (e.g. limited) FM waveform. The output of the decoder will correspond to a binary manifestation of the instantaneous periods of the FM waveform.
  • an analog FM signal which may have been amplified and clipped is applied at connection 10 to the input of a monostable circuit depicted as ONE-SHOT 11.
  • ONE-SHOT 11 -generates a narrow pulse for each zero crossing of the FM waveform (or each transition of the clipped FM waveform).
  • the pulses from ONE-SHOT 11 are applied to delay elements 12 and to one input of respective AND gates 13.
  • the output connections from the delay elements 12 are connected to respective second input terminals of the AND gates 13 and the output terminals of the AND gates are coupled to respective input connections of the DECODER 14.
  • the output pulses from ONE-SHOT 11 may also be applied to a latching input C L of the DECODER. (Note it may be desirable to provide output latches in the DECODER to maintain the PCM output stable between zero crossings).
  • ⁇ min ⁇ 0
  • ⁇ 0 the delay period of the first delay element designated ⁇ 0 .
  • the next larger delay element ⁇ 1 has a delay of ⁇ 0 + ⁇ where ⁇ is an incremental delay generally significantly smaller than ⁇ 0 and which defines the resolution of the apparatus.
  • Each succeeding delay element includes an additional incremental delay of ⁇ with the nth delay element ⁇ n providing a delay of ⁇ 0 +n ⁇ equal to the maximum interval ⁇ max between zero crossings of the FM waveforms.
  • An alternative arrangement for the delay elements consists of arranging a delay element with delay ⁇ 0 in series with the ONE-SHOT output so that the parallel delay elements 12 need only provide the incremental delays R ⁇ where R corresponds to the Rth delay element.
  • the width of the pulses generated by the ONE-SHOT are designed according to the particular design of the DECODER apparatus. In general however the pulse duration must be at least equal to one half the incremental delay, ⁇ , or pulses may be missed by the AND gate detectors.
  • Particular detection signals from AND gate 13 which are input to the DECODER is related to the number, R, of incremental delays determined to exist between zero crossings and therefor related to time.
  • the actual period between zero crossings is ⁇ 0 +R ⁇ .
  • the minimum delay ⁇ 0 can also be represented by some number, S, of incremental delays so that the period between zero crossings is (S+R) ⁇ .
  • the modulating signal of an FM waveform however is related to the instantaneous frequency of the FM signal. Therefore it is the reciprocal of (S+R) that is related to the demodulated FM signal.
  • the DECODER must output signals associated with reciprocal values of (S+R) for the Rth AND gate producing a detection signal.
  • the reciprocals of (S+R) are the demodulated signal scaled by a factor 1/ ⁇ and offset by an amount related to 1/2 the differences between ⁇ max - ⁇ min .
  • the DECODER required to generate the reciprocals of (S+R) may be a device of the type known as a programmed logic array (PLA).
  • the DECODER 14 may include a priority encoder 16 and a ROM 17.
  • the priority encoder generates an n bit PCM output code for 2 n input connections and in the instant application produces the binary representation R.
  • the PCM output of the priority encoder is thereafter coupled to the ADDRESS inputs of the memory device 17 which is programmed to provide at its output, a binary manifestation corresponding to the reciprocal of the sum of the ADDRESS code and the value S.
  • the memory may be nonlinearly programmed to compensate for signal or certain system nonlinearities.
  • waveform A corresponds to a limited or clipped FM waveform in which level transitions correspond to zero crossings.
  • a maximum period ⁇ max and a minimum period ⁇ min between zero crossings are shown adjacent one another though in practice such a condition is unlikely to occur due to bandwidth limitations.
  • the signal of waveform A is applied to ONE-SHOT 11 which is responsive to the transitions thereof and produces pulses of constant duration indicated in waveform B.
  • the signal of waveform B is applied to each of the delay elements 12.
  • Waveforms C,D,E correspond to the output signals from delay elements ⁇ 0 , ⁇ 1 , ⁇ 2 respectively. It can be seen that each delay element delays the applied signals by successively greater periods.
  • Waveform K corresponds to the output of delay element ⁇ n and provides a signal delay of ⁇ 0 +n ⁇ .
  • the transition at time T 0 produces pulse P 1 which is applied to the delay elements and exits therefrom as pulses P 1R ' as shown.
  • the DECODER responsive to the signal from the ⁇ n AND gate would output a signal related to the number n. If the pulse P 2 occurred prior to time T 1 , as shown dotted in FIG. 2, it would have been in coincidence with a delayed pulse from an intermediate delay element e.g. pulse P 1R ' in waveform F etc.
  • Pulse P 2 applied to the respective delay elements exits as pulse P 2R ' from the respective delay elements.
  • Pulse P 3 occurs simultaneously with pulse P 21 ' exiting delay element ⁇ 0 .
  • the AND gate coupled to delay element ⁇ 0 will detect the coincidence and DECODER 14 will output a binary value related to the minimum delay period i.e. zero incremental delays. Note that when pulse P 3 occurs the pulses P 2 coursing through all succeeding delay stages will not yet have become available at their respective outputs.
  • double detection can be used to advantage.
  • adjacent detection circuits may simultaneously be enabled.
  • the pulses may be rectangular and of width 3 ⁇ /4. Pulses from successive delay elements will be separated by ⁇ /4. A later pulse from the ONE-SHOT may therefore straddle delayed pulses from adjacent delay elements.
  • the R th detection gate will only be uniquely enabled for the later pulse having a leading edge occurring over the incremental range of (0 to ⁇ /4). For the leading edge of the later pulse occurring between the range - ⁇ /4 and ⁇ /2 relative to the R th delay, both the R th and the (R-1) th detection gates will be enabled.
  • both the R th and the (R+1) th detection gates will be enabled.
  • the resolution of the n gate system can be enhanced to the resolution of a (2n-1) delay element system.
  • the upper waveform designated FM is an arbitrary FM waveform in which the period between zero crossings linearly increases and then decreases.
  • the first period designated ⁇ 0 is presumed to be a minimum period.
  • the modulating signal for an FM signal with symmetrical linearly increasing and decreasing periods is hyperbolic and proportional to 1/ ⁇ . This signal is illustrated by the dashed line designated modulating signal.
  • the PCM ANALOG signal is skewed slightly to the right because the values corresponding to a particular period are produced during the succeeding period.
  • there is a slight frequency distortion because the duration of a particular sample value is determined by the succeeding period. This latter distortion can be reduced by sampling the PCM output data at a constant rate and interpolating or "averaging" each value over several values.
  • FIG. 4 is a variation of the FIG. 1 converter which includes specific apparatus for creating the incremental delays.
  • the FM waveform to be converted is applied at connection 10 to ONE-SHOT pulse generator 11.
  • the output of the ONE-SHOT at connection 20 is applied to delay element 21, AND gate 23 and DECODER 25.
  • Delay element 21 provides a delay ⁇ 0 equivalent to the minimum period between zero crossings of the FM signal.
  • the output of element 21 is coupled to the input of a logic gate 22a which may be for example a simple buffer or an OR gate, or an AND gate with its input tied together etc., having a defined delay period between its input and its output connections (traditionally known as its propagation or gate delay).
  • Similar gates 22b to 22n are cascade connected with gate 22a each of which has similar gate delay periods.
  • the gate delay of the elements 22a, 22b . . . etc. in this arrangement is the incremental delay ⁇ which determines the resolution of the converter. Because of the cascade arrangements of gates 22 each successive gate adds an additional delay to the pulses applied to delay element 21.
  • the delay periods at the output connections of element 21, gates 22a, 22b and 22n are respectively ⁇ 0 , ⁇ 0 + ⁇ , ⁇ 0 +2 ⁇ and ⁇ 0 +n ⁇ .
  • Propagation or gate delays are related to the technology utilized in fabricating the devices.
  • bipolar emitter-coupled devices may have gate delays of less than a nanosecond.
  • gate delays of 10 ns (high speed technology) and 30ns (standard technology) are typical. In both cases the speeds can be varied by changing the supply potentials to the circuitry or varying internal or external capacitances associated with the gates affording some programmability or adaptive control to the circuit resolution.
  • the programmability of the gate delays is indicated by the variable gate supply source 28.
  • OR gates are interposed between the pulse coincidence detection AND gates 23 and the decoder 25.
  • the OR gates are included to prevent false readings where the total incremental delays produced by gates 22 is greater than the minimum time between zero crossings. If the total incremental delay is greater than the mimimum zero crossing interval, ⁇ min , it is possible for two successive pulses, produced by zero crossings defining a period close to ⁇ min , to be concurrently traversing the delay stages 22. On the occurrence of the next pulse, the two pulses present in the delay stages will cause two of the AND gates 23 to concurrently produce detection signals. However, since the lastmost pulse introduced into the delay stages produces the correct detection signal, means are provided to override the detection signal produced by the earlier introduced pulse which remained in the delay stages.
  • One method to accomplish the override is to cause all of the input signals to DECODER 25 representing delays equal to and greater than the delay of the AND gate located closest the ONE-SHOT to detect coincidence, to also produce detection signals.
  • the DECODER input signals from all detection circuits preceeding the first circuit which registers pulse coincidence will be held at a logic low level and DECODER input signals from all succeeding detection circuits will be forced to a logic high level.
  • each DECODER input signal is ORed with the succeeding detection signal. The detection signal of the uppermost AND gate (in the FIGURE) to register coincidence will thus be ORed into all succeeding DECODER inputs.
  • DECODER 25 will be designed to output PCM samples which correspond to the first (in position, not time) DECODER input signal registering a logic high. Note however that the condition of two pulses simultaneously traversing the delay elements cannot occur if the minimum period between zero crossings is greater than one half the maximum period between zero crossings of the FM signal. When these conditions exist it is not necessary to include the override circuitry in the converter.
  • the PCM output 26 of DECODER 25 is connected to an interpolator 27 which is clocked at a fixed rate by a clock signal ⁇ which rate may be greater than the frequency of the FM carrier.
  • Interpolator 27 weights and combines a number of samples, e.g. four, produced by the DECODER, and provides "averaged" samples, at the fixed rate, at its output 30.
  • the interpolation may be linear, cubic or some other polynominal function. (For detailed information on interpolation the reader is referred to R. E. Crochiere et al., "Interpolation and Decimation of Digital Signals--A tutorial Review", Proc. IEEE, Vol. 69, No. 3, March 1981, incorporated herein by reference).
  • the interpolator provides fixed rate samples for subsequent synchronous processing and tends to smooth the envelope defined by the DECODER output samples and linearize the output response.
  • FIG. 5 is a further embodiment of the invention wherein the incremental delays are generated by a resistor ladder network with capacitors connected to respective tap points 41, 42.
  • the delay per section is determined by the RC time constant. Note that if capacitors C are of the voltage variable type the incremental delay times can be adjusted by changing the DC bias, V bias , imposed across the capacitors.
  • the RC network is terminated in its characteristic impedance 43 to preclude reflections.
  • a delay element 40 having a delay ⁇ 0 is connected between ONE-SHOT 11 and the RC network and may consist of a number of similar cascaded connected RC networks.
  • delay element 40 may consist of a fixed delay multivibrator and second ONE-SHOT or of a voltage variable resistance-capacitance circuit as shown in FIG. 5b.
  • the channel resistance of a field effect transistor (FET), 49 which resistance is dependent upon the bias potentials between its gate, source and drain electrodes, is used as the voltage variable resistor. Resistance changes are effected by adjustment of the gate potential of the FET.
  • the voltage variable resistance provides for a variable delay ⁇ 0 which permits tuning of the converter-demodulator for different carriers or modulation conditions.
  • the pulse coincidence detectors in FIG. 5a are single FET's 44 having their gate electrodes connected to respective taps on the RC delay network and their source electrodes coupled in common to the ONE-SHOT 11 via an INVERTER 49.
  • the drain electrodes of the FET's are connected to the DECODER 47 input terminals and the DECODER 47 is designed to respond to input current detection signals in this instance.
  • the FET's are N-type enhancement devices which are conditioned to conduct drain-source current responsive to a positive gate-to-source potential.
  • the INVERTER 49 output potential is high. This high potential applied to the source electrodes of FET's 44 creates a negative gate-to-source potential on each transistor and prevents them from conducting drain current.
  • the output of the inverter goes low and the preceding pulse emerges from one of the delay elements providing a positive gate-to-source potential on the respective transistor which in turn provides a detection current signal to the DECODER 47.
  • the FET's 44 were coupled to the DECODER input connections and the ONE-SHOT coupled to the drain electrodes of the FET's, the INVERTER 49 is unnecessary.
  • the FET's have a drain bias for conduction of drain current only when a pulse is provided by the ONE-SHOT.
  • an FET having a gate pulse provided from its respective delay element coincidently with a pulse being generated by the ONE-SHOT will conduct and provide a detection signal to the DECODER.
  • FIG. 6 is a pictorial representation of the FIG. 5 RC network and detection FET's as they may be realized in integrated circuit form.
  • the resistors R are formed from a continuous polysilicon electrode 51 fabricated over a dielectric on a semiconductor die.
  • the polysilicon (or other appropriate refractory electrode) is lightly doped so that it is rendered only slightly conductive, i.e., it is highly resistive.
  • the electrode 51 has an inherent distributed capacitance 55 over its length associated with the dielectric and semiconductor die on which it is fabricated.
  • the resistance 56 over its length can be made uniform as can the distributed capacitance, thus over a unit length they can be assumed to be lumped elements of cascade connected series resistors with shunting capacitors between the cascade connections.
  • Drain 53 and source 52 diffusions are disposed in the silicon die adjacent the polysilicon electrode 51 such that it performs as a gate electrode for respective FET's. A number of pairs of source and drain diffusions are shown along the polysilicon electrode each forming an FET therewith.
  • the resistance of the delay elements are determined by the spacing of FET's along the gate (polysilicon 51) electrode.
  • the capacitance is determined primarily by the thickness of the dielectric and the width-length aspect ratio of electrode 51.
  • the respective source diffusions are coupled to the ONE-SHOT via a low impedance conductor 50 which also contacts one end of the polysilicon electrode 51.
  • the respective drain diffusions are connected to the DECODER by respective low impedance conductors 54.
  • a further approach to realizing the incremental delays is to use the surface acoustic wave (SAW) phenomena with the signal tapped from the transport medium at appropriate locations, and applied to signal coincidence detection circuitry.
  • SAW surface acoustic wave
  • This may be done in silicon as well as the more conventional SAW materials.
  • the detection and DECODER circuitry may be integrated on the same semiconductor substrate.

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US06/521,453 1983-08-08 1983-08-08 Analog-to-digital converter/demodulator for FM signals Expired - Fee Related US4593266A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US06/521,453 US4593266A (en) 1983-08-08 1983-08-08 Analog-to-digital converter/demodulator for FM signals
IT8422202A IT1206461B (it) 1983-08-08 1984-08-02 Demodulatore e convertitore analogico/digitale per segnali modulati d'angolo.
KR1019840004676A KR930001747B1 (ko) 1983-08-08 1984-08-06 각도 변조 신호용 복조기 및 아나로그-디지탈 변환기
JP59164355A JPS6057727A (ja) 1983-08-08 1984-08-07 角度変調されたアナログ信号を復調し、かつデイジタル信号に変換する装置
FR848412487A FR2550671B1 (fr) 1983-08-08 1984-08-07 Circuit convertisseur analogique-numerique et demodulateur de signaux video modules en argument
GB08420028A GB2144936B (en) 1983-08-08 1984-08-07 A demodulator and analog-to-digital converter for angle modulated signals
DE19843429061 DE3429061A1 (de) 1983-08-08 1984-08-07 Schaltungsanordnung zur demodulation und a/d-umwandlung winkelmodulierter signale

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US06/521,453 US4593266A (en) 1983-08-08 1983-08-08 Analog-to-digital converter/demodulator for FM signals

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US (1) US4593266A (ja)
JP (1) JPS6057727A (ja)
KR (1) KR930001747B1 (ja)
DE (1) DE3429061A1 (ja)
FR (1) FR2550671B1 (ja)
GB (1) GB2144936B (ja)
IT (1) IT1206461B (ja)

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US4887084A (en) * 1987-06-23 1989-12-12 Matsushita Electric Industrial Co., Ltd. Priority encoder
DE3902795A1 (de) * 1989-01-31 1990-08-02 Arno H Dipl Ing Taruttis Verfahren zur rueckgewinnung der datenbits aus frequenzumgetasteten signalen zur datenuebertragung
US5270666A (en) * 1989-12-22 1993-12-14 Nokia Mobile Phones, Ltd. Method and circuitry for demodulation of angle modulated signals by measuring cycle time
US5754130A (en) * 1994-02-21 1998-05-19 Teratec Corporation Analogue-to-digital converter using phase modulation
US6067363A (en) * 1996-06-03 2000-05-23 Ericsson Inc. Audio A/D convertor using frequency modulation
US7425915B1 (en) * 2004-05-20 2008-09-16 University Of Rochester Frequency modulation based flash ADC
RU2644070C1 (ru) * 2016-08-24 2018-02-07 федеральное государственное бюджетное образовательное учреждение высшего образования "Самарский государственный технический университет" Цифровой модулятор для преобразования частоты

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JPH01126809A (ja) * 1987-11-12 1989-05-18 Toshiba Corp アナログデジタル変換機能を有したｆｍ復調器
DE3816568A1 (de) * 1988-05-14 1989-11-16 Bodenseewerk Geraetetech Verfahren und vorrichtung zur demodulation eines wechselspannungs-signals
FI88559C (fi) * 1989-12-22 1993-05-25 Nokia Mobile Phones Ltd Anordning foer detektering av en FM- eller PM-modulerad signal
KR20000046596A (ko) * 1998-12-31 2000-07-25 권상문 우선순위 채널을 이용한 아날로그 다중 입력신호 처리장치

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US4887084A (en) * 1987-06-23 1989-12-12 Matsushita Electric Industrial Co., Ltd. Priority encoder
DE3902795A1 (de) * 1989-01-31 1990-08-02 Arno H Dipl Ing Taruttis Verfahren zur rueckgewinnung der datenbits aus frequenzumgetasteten signalen zur datenuebertragung
US5270666A (en) * 1989-12-22 1993-12-14 Nokia Mobile Phones, Ltd. Method and circuitry for demodulation of angle modulated signals by measuring cycle time
US5754130A (en) * 1994-02-21 1998-05-19 Teratec Corporation Analogue-to-digital converter using phase modulation
US6067363A (en) * 1996-06-03 2000-05-23 Ericsson Inc. Audio A/D convertor using frequency modulation
US6731763B1 (en) 1996-06-03 2004-05-04 Ericsson Inc. Audio A/D converter using frequency modulation
US7425915B1 (en) * 2004-05-20 2008-09-16 University Of Rochester Frequency modulation based flash ADC
RU2644070C1 (ru) * 2016-08-24 2018-02-07 федеральное государственное бюджетное образовательное учреждение высшего образования "Самарский государственный технический университет" Цифровой модулятор для преобразования частоты

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IT1206461B (it) 1989-04-27
JPS6057727A (ja) 1985-04-03
GB8420028D0 (en) 1984-09-12
JPH0588571B2 (ja) 1993-12-22
KR850002182A (ko) 1985-05-06
DE3429061A1 (de) 1985-02-28
GB2144936B (en) 1986-09-17
GB2144936A (en) 1985-03-13
IT8422202A0 (it) 1984-08-02
KR930001747B1 (ko) 1993-03-12
FR2550671B1 (fr) 1989-10-13
FR2550671A1 (fr) 1985-02-15

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