US4584669A - Memory cell with latent image capabilities - Google Patents

Memory cell with latent image capabilities Download PDF

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Publication number
US4584669A
US4584669A US06/584,033 US58403384A US4584669A US 4584669 A US4584669 A US 4584669A US 58403384 A US58403384 A US 58403384A US 4584669 A US4584669 A US 4584669A
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Prior art keywords
node
circuit
cell
latent image
drain
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Expired - Fee Related
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US06/584,033
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English (en)
Inventor
Martin D. Moynihan
Thomas A. Williams
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International Business Machines Corp
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International Business Machines Corp
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Priority to US06/584,033 priority Critical patent/US4584669A/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION A CORP. OF NY reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION A CORP. OF NY ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MOYNIHAN, MARTIN D., WILLIAMS, THOMAS A.
Priority to JP59250665A priority patent/JPS60182596A/ja
Priority to EP85101323A priority patent/EP0156135A3/en
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Publication of US4584669A publication Critical patent/US4584669A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Definitions

  • the invention disclosed broadly relates to integrated circuits and more particularly relates to memory type integrated circuits.
  • Latent image memory circuits have been disclosed in the prior art, which are capable of assuming a predetermined binary state when power is turned on to the circuit.
  • Prior art circuits employing bipolar transistor technology include U.S. Pat. Nos. 3,662,351; 3,801,967; and 3,820,086.
  • Another approach to latent image memory circuits is described in U.S. Pat. No. 3,755,793 which discloses the use of both FET devices and charge-coupled devices to obtain the latent image memory operation.
  • Still another approach to achieving latent image memory operation employing single conductivity type FET transistor technology is described in U.S. Pat. No.
  • a CMOS circuit which has a latent image feature for application in FET memory arrays.
  • a four device cross-coupled CMOS circuit is formed in a minimum layout configuration, which allows for metal wiring level programming into a preconditioned binary one or a binary zero state. The preconditioned binary state will be assumed by the circuit when power is turned on. Thereafter, the circuit can be accessed for normal binary one and zero selected storage without a significant diminution in its operating characteristics, when compared with conventional CMOS cross-coupled storage circuits.
  • the circuit includes two CMOS inverter circuits, each having a P channel FET and N channel FET connected in series between a positive voltage and ground potential.
  • each respective CMOS inverter is connected to the gate of the N channel FET device in the other inverter circuit.
  • Four selectively severable nodes are provided in the metallization interconnecting the four FET devices in the circuit so that the gate of the P channel FET device in the first one of the CMOS inverter circuits can be selectively connected to ground potential and the gate of the P channel FET device in the second one of the CMOS inverter circuits can be selectively connected to the output node of the first inverter circuit.
  • the first P channel FET device will be more conductive than the second P channel FET device when power to the circuit is turned on, so that the output node of the first inverter circuit will become more positive than will the output node of the second inverter circuit, thereby manifesting the initial storage state of the circuit.
  • This initial storage state is a permanently stored binary state which will always occur when the circuit is turned on.
  • the arrangement of the severable nodes in the interconnection metallurgy for the four FET devices can be selectively cut so that the output node of the second CMOS inverter circuit will be more positive when power is initially turned on to the circuit.
  • all storage sites in the memory array can be constructed with the same configuration and the programming of the initial storage states for each respective storage site need not take place until after the interconnection metallization lines have been applied to the circuit.
  • the resulting circuit is therefore more simple to fabricate, more simple to program, and more simple to operate than has been available in the prior art.
  • FIG. 1 is an overall circuit schematic diagram of two storage sites in a memory array, each storage site comprising the preconditioned storage circuit cell invention.
  • FIG. 2 is a circuit schematic diagram of the preconditioned storage circuit cell 10 of FIG. 1.
  • FIG. 3 is a circuit schematic diagram of the preconditioned storage circuit cell 20 of FIG. 1.
  • FIG. 4 is a layout diagram illustrating the arrangement of the diffusions and the polycrystalline silicon interconnection lines for the preconditioned storage circuit cell invention.
  • FIG. 5 is a layout diagram arranged in a similar manner to the diagram of FIG. 4, illustrating the arrangement of the metal interconnection lines which lie above the level of the diffusions and polycrystalline silicon gate interconnection lines of FIG. 4, in accordance with the preconditioned storage circuit cell invention.
  • FIG. 6 is a timing diagram for the circuit 10.
  • FIG. 7 is a timing diagram for the circuit 20.
  • FIG. 8 is a cross-sectional view along the section line 8--8' of FIG. 5, showing a detailed illustration of the severable node B.
  • FIG. 9 is a cross-sectional view along the section line 9--9' of FIG. 5, showing a detailed view of the severable node A.
  • the memory array shown in FIG. 1 depicts two storage sites with a first preconditioned storage circuit cell 10 having a first initial storage state, and a second preconditioned storage circuit cell 20 having a second, opposite initial storage state.
  • the memory array is arranged with pairs of bit lines BL and BL* oriented in the vertical direction which are connected to bit line driver circuits which will write a first binary state by raising the voltage of the bit line BL and lowering the voltage of the bit line BL*, as is common in the prior art.
  • the * symbol after a binary variable, such as BL* symbolizes the complement of the variable BL.
  • bit lines BL and BL* are also connected to a sense amplifier so that during a read stage, a first binary state which has been stored at a storage site, will raise the potential of one of the bit lines BL and lower the potential of the other bit line BL*, as is common in the prior art.
  • the memory array is organized into horizontal rows of the storage sites, with word lines WL which will selectively connect all of the storage cells along a particular row to the respective pairs of bit lines in each respective column occupied by the storage cells.
  • An example of a similar orthogonal arrangement of bit lines and word lines in an FET memory array can be found in U.S. Pat. No. 3,798,621 to Baitinger, et al which is assigned to the instant assignee.
  • the preconditioned storage circuit cell 10 in FIG. 1 is connected through the N channel isolation FET devices T5 and T6 to the respective bit lines BL and BL*, by means of applying a positive potential to the word line WL, which has the effect of connecting the node Q of the circuit 10 to the bit line BL and of connecting the node Q* of the circuit 10 to the bit line BL*.
  • the preconditioned storage circuit cell 10 is shown in FIG. 1 as it is arranged in its physical layout which is depicted in FIGS. 4 and 5.
  • the preconditioned storage circuit cell 10 of FIG. 1 is redrawn in FIG. 2 in a more conventional circuit schematic form, so as to facilitate the discussion of its topology and operation.
  • CMOS complementary metal oxide semiconductor
  • FET field effect transistor
  • the second CMOS FET inverter circuit 14 of the preconditioned storage circuit cell 10 is made up of the P channel FET device T3 and the N channel FET device T4 which are series-connected between positive potential VD and ground potential and are joined at the output node 15.
  • the output node 13 which is the Q node for the circuit is connected to the gate of the N channel FET device T4 and the output node 15 which is the Q* node for the circuit, is connected to the gate of the N channel FET device T2.
  • the circuit 10 in FIG. 2 is selectively programmed into a first initial storage state by selectively connecting the gate of the P channel FET device T1 to ground potential and also selectively connecting the gate of the P channel FET device T3 to the output node 13. This will cause the P channel FET device T1 to be more conductive than is the P channel FET device T3 when a positive potential VD is initially applied to the circuit. Since the P channel FET device is more conductive, the node 13 rises in potential faster than does the node 15 and thereby applies a positive potential to the gate of the N channel FET device T4 at a faster rate than would a positive potential be applied to the gate of the N channel FET device T2.
  • the N channel device T4 turns on faster than the N channel FET device T2, thereby connecting the output node 15 to ground potential when the positive voltage VD is initially applied to the circuit 10. This will cause the N channel FET device T2 to remain in its off state, thereby reinforcing the positive potential state of node 13 for the circuit.
  • the preconditioned storage circuit cell 10 of FIG. 2 will have a preprogrammed first initial storage state with the node 13 or the Q node having a higher potential than the potential of the node 15 or the Q* node of the circuit.
  • the preconditioned storage circuit cell 20 of FIG. 1 was physically identical to the cell 10 of FIG. 1 prior to the programming of its metallized interconnection layer to store its initial storage state. After the programming of its initial storage state, the preconditioned storage circuit cell 20 has the opposite binary state from that of the circuit 10 of FIG. 1. In order to distinguish the identity of the transistor devices in circuit 20 from those in circuit 10, corresponding FET devices in the circuit 20 will be designated with a prime such that the FET device T2 in circuit 10 will correspond to the FET device T2' in circuit 20.
  • the diagram of circuit 20 in FIG. 1 reflects its physical layout as is shown in FIGS. 4 and 5 for circuit 10. However, to facilitate the discussion of the topology and operation of circuit 20, it has been redrawn in a more conventional circuit schematic diagram of FIG. 3.
  • circuit 20 is composed of the first CMOS inverter 12' and a second CMOS inverter 14' which were originally fabricated in the identical manner to the fabrication of the first and second CMOS inverters 12 and 14 in the circuit 10, prior to the programming of the metallization layer for the two respective circuits.
  • Circuit 20 in FIG. 3 has the P channel FET device T1', which corresponds to T1 in circuit 10, selectively programmed so that its gate is connected to the output node 15' or Q*' and correspondingly, the gate of the P channel FET device T3' is selectively connected to ground potential.
  • the P channel FET device T3' when the positive potential VD is initially applied to the circuit, the P channel FET device T3' will be more conductive than is the P channel FET device T1'. Thus, the node 15' or the Q*' node will have a higher potential in the initial storage state than the potential of the node 13' or the Q' node.
  • the isolation transistors T5' and T6' will respectively connect the nodes Q' and Q*' to the bit lines BL and BL*, thereby outputting a more positive potential on the bit line BL* than the potential on the bit line BL. This is the opposite stored binary state to the stored binary state in circuit 10, for the initial storage states of the two circuits 10 and 20.
  • FIG. 4 shows the physical layout of the diffusions and polycrystalline silicon interconnection lines for the preconditioned storage circuit cell 10. If the reference numerals are primed in FIG. 4, the layout will also apply to the circuit 20 of FIG. 1 and FIG. 3. Overlying the diffusion and polycrystalline silicon interconnection line levels is the metallization level whose pattern is shown in FIG. 5. To more clearly illustrate the relative levels for the diffusions, polycrystalline silicon interconnection lines and metallization interconnection lines, cross-sectional views in FIGS. 8 and 9 are provided. The manner in which the initial storage state for the preconditioned storage circuit cell 10 can be selected is by selectively severing the B and the B' metallization nodes. The cross-sectional view 8--8' shown in FIG.
  • FIG. 8 illustrates the structure of the metallization node B which is shown in its layout in FIG. 5 and which is shown in its circuit diagram context in FIG. 1.
  • the metallized ground line 30 has a small spur 32 shown in FIG. 5 which connects to the necked-down portion A which is the A metallization node.
  • the A metallization node is selectively severable by means of laser scribing, wet chemical or dry etching, or other semiconductor cutting techniques well-known to the prior art.
  • the portion A is shown in FIG. 5 connected to the metallization 34 which connects to the contact portion 36 shown in cross-section in FIG. 8.
  • the contact 36 connects the upper metallization level with the intermediate polycrystalline silicon interconnection level and specifically to the polycrystalline conductor 38.
  • Polycrystalline silicon conductor 38 connects to the polycrystalline silicon gate 39 of the FET device T1.
  • the end of the diffusion 37 can be seen aligned with the gate 39 and the cross-section of diffusion 35 of the Q node can also be seen.
  • the metal contact 36 continues as a metallization line 40 to the severable metallized node B.
  • the metallized node B is the node which is selectively severed, along with the node B', in order to achieve the circuit 10 of FIG. 2 and FIG. 1.
  • the metallized and selectively severable node B is a necked-down portion of the metallized lines 40 and 42.
  • the metallized line 42 then continues onto the metal contact portion 44 which serves to contact the polycrystalline silicon interconnection line 46 on the intermediate level.
  • the polycrystalline silicon line 46 connects to the gate 48 of the FET device T2.
  • the end of the diffusion 47 is also seen in FIG. 8 aligned with the gate 48.
  • the metal contact 44 then continues onto the metal contact 50 which reaches down through the insulator layer 16 to the diffusion 52 in the semiconductor substrate 18.
  • FIG. 5 A technique for selectively severing the nodes B and B' or alternately the nodes A or A' in the metallization interconnection network shown in FIG. 5 can be found in U.S. Pat. No. 4,198,696 which is assigned to the instant assignee.
  • the physical layout of FIGS. 4 and 5 can be selectively programmed either to permanently store a first initial storage state corresponding to circuit 10 or a second permanent initial storage state as is shown for circuit 20, by selectively severing the appropriate pair of metallization nodes B and B' or alternately A and A', respectively, by rendering incident a laser beam to melt and separate the respective severed portions of the metallized line adjacent to the severable portion of the line.
  • the composition of the metallization layer is typically aluminum which can optionally be doped with small quantities of copper and/or silicon as is known to the prior art.
  • nodes B and B' are selectively severed and nodes A and A' are left intact.
  • the gate of the P channel FET device T1 will be connected to ground potential and the gate of the P channel FET device T3 will be connected to the node Q. Therefore, when the positive voltage VD is initially applied to the circuit, the node Q will have a high potential and the node Q* will have a low potential.
  • FIG. 4 and FIG. 5 can be selectively programmed to achieve the circuit 20 of FIG. 3 by selectively severing the A and the A' metallized nodes and leaving the B and B' nodes intact. This will connect the gate of the P channel FET device T3' to ground potential and the gate of the P channel FET device T1' to the node Q*'. Then when the positive potential VD is initially applied to the circuit, the node Q' will have a relatively low potential and the node Q*' will have a relatively high potential.
  • a reset circuit 22 of FIG. 1 is provided, which is a CMOS inverter with the gates of the P channel and N channel devices thereof connected to the reset signal and the output node thereof connected by line 24 as the VD positive potential to a circuit 10 and a circuit 20.
  • Pulsing the reset waveform in FIG. 6 illustrates the sequence of events when the positive potential to the circuit 10 is interrupted. As can be seen in FIG. 6, the potential of both the Q node and the Q* node falls to ground potential when the positive potential VD is off.
  • the P channel FET device T1 is more conductive than the P channel FET device T3 and therefore the node Q is higher in potential than the node Q* and this is shown in the timing diagram of FIG. 6. If this had been a power failure, for example, a start-up procedure could be carried out wherein the information permanently stored in the initial storage states of the storage cells in the memory array would be read out in order to provide the initial program load conditions for turning on an associated data processor. This reading of the preconditioned state is shown in the timing diagram of FIG.
  • the circuit 10 can be used as a conventional read/write random access memory storage site. This would begin with a write operation where the word line WL is positively pulsed and the respective states of the bit lines BL and BL* are then transferred through the isolation FET devices T5 and T6, respectively to the nodes Q and Q*, respectively. As is shown in FIG. 6, to change the state of the circuit 10, the state of the bit lines BL and BL* are transferred to the nodes Q and Q* of the circuit 10. Thereafter, if the current storage state of the circuit 10 is desired to be read out, the bit lines BL and BL* are both conditioned to be positive in the bit line precharge stage of FIG.
  • the word line WL is pulsed positive to render the devices T5 and T6 conductive. Then, the respective potentials at the nodes Q and Q* for the circuit 10 will be applied to the bit lines BL and BL*, respectively, and those two potentials can be sensed on the bit lines by a sense amplifier in the conventional manner.
  • circuit 20 as shown in the timing diagram of FIG. 7 is similar to the operation of circuit 10 as shown in the timing diagram of FIG. 6.

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  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
US06/584,033 1984-02-27 1984-02-27 Memory cell with latent image capabilities Expired - Fee Related US4584669A (en)

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US06/584,033 US4584669A (en) 1984-02-27 1984-02-27 Memory cell with latent image capabilities
JP59250665A JPS60182596A (ja) 1984-02-27 1984-11-29 半導体記憶回路
EP85101323A EP0156135A3 (en) 1984-02-27 1985-02-08 Preconditioned memory cell

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US06/584,033 US4584669A (en) 1984-02-27 1984-02-27 Memory cell with latent image capabilities

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855803A (en) * 1985-09-02 1989-08-08 Ricoh Company, Ltd. Selectively definable semiconductor device
US5426614A (en) * 1994-01-13 1995-06-20 Texas Instruments Incorporated Memory cell with programmable antifuse technology
US5455788A (en) * 1993-08-24 1995-10-03 Honeywell Inc. SRAM to ROM programming connections to avoid parasitic devices and electrical overstress sensitivity
US5517634A (en) * 1992-06-23 1996-05-14 Quantum Corporation Disk drive system including a DRAM array and associated method for programming initial information into the array
US5581505A (en) * 1989-05-15 1996-12-03 Dallas Semiconductor Corp. Ram/ROM hybrid memory architecture
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US6122216A (en) * 1998-12-09 2000-09-19 Compaq Computer Corporation Single package dual memory device
US20140314208A1 (en) * 2011-12-06 2014-10-23 Koninklijke Philips N.V. Balancing of a rotating anode

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2588936B2 (ja) * 1988-07-04 1997-03-12 沖電気工業株式会社 半導体記憶装置
JP4712679B2 (ja) * 2006-11-24 2011-06-29 三菱電機株式会社 ヒートポンプ装置
US9202554B2 (en) 2014-03-13 2015-12-01 International Business Machines Corporation Methods and circuits for generating physically unclonable function

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855803A (en) * 1985-09-02 1989-08-08 Ricoh Company, Ltd. Selectively definable semiconductor device
US5581505A (en) * 1989-05-15 1996-12-03 Dallas Semiconductor Corp. Ram/ROM hybrid memory architecture
US5517634A (en) * 1992-06-23 1996-05-14 Quantum Corporation Disk drive system including a DRAM array and associated method for programming initial information into the array
US5455788A (en) * 1993-08-24 1995-10-03 Honeywell Inc. SRAM to ROM programming connections to avoid parasitic devices and electrical overstress sensitivity
US5426614A (en) * 1994-01-13 1995-06-20 Texas Instruments Incorporated Memory cell with programmable antifuse technology
US5986962A (en) * 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US6122216A (en) * 1998-12-09 2000-09-19 Compaq Computer Corporation Single package dual memory device
US20140314208A1 (en) * 2011-12-06 2014-10-23 Koninklijke Philips N.V. Balancing of a rotating anode
US9368317B2 (en) * 2011-12-06 2016-06-14 Koninklijke Philips N.V. Balancing of a rotating anode

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JPS60182596A (ja) 1985-09-18
EP0156135A3 (en) 1987-09-23
EP0156135A2 (en) 1985-10-02
JPH0217875B2 (enrdf_load_stackoverflow) 1990-04-23

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