US4517552A - Method and apparatus for N-to-M encoding - Google Patents

Method and apparatus for N-to-M encoding Download PDF

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US4517552A
US4517552A US06/380,336 US38033682A US4517552A US 4517552 A US4517552 A US 4517552A US 38033682 A US38033682 A US 38033682A US 4517552 A US4517552 A US 4517552A
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bit
word
code words
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words
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Norihisa Shirota
Takao Abe
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Sony Corp
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Sony Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1438—8 to 10 modulation

Definitions

  • This invention relates to a method and apparatus for encoding a n-bit information word into a m-bit code word, the encoded code words exhibiting desirable characteristics, for example, for magnetic recording.
  • digital video tape recorders have been developed, wherein a composite color television signal in analog form is converted to a digital signal, and the digital video signal then is recorded directly on a record medium, such as magnetic tape.
  • a record medium such as magnetic tape.
  • One proposal for a digital VTR is described in, for example, copending application Ser. No. 192,358 now U.S. Pat. No. 4,329,708.
  • n-bit information words are represented by corresponding m-bit code words, wherein m>N, and the so-called “disparity" of each m-bit code word is equal to zero.
  • the word “disparity” as understood herein refers to the DC component of the code word. If a binary "1” is represented as the value +1 and a binary "0" is represented as the value -1, then the difference between all of the binary "1"s and "0"s which constitute a code word will represent a positive or negative number or zero, depending upon the difference between the number of "1"s and "0”s. This number is the disparity of the code word.
  • the sum of all of the disparities of a string, or series, of successive code words is the "digital sum variation" of those words.
  • the digital sum variation may be thought of as a running sum, or total, of the individual disparities of each code word, and represents the overall, or net, DC component of the successive code words that have been produced.
  • each code word is formed of a sufficient number of bits such that every n-bit information word can be represented by a respective m-bit code word having zero disparity.
  • a (4, 6; 0) coding technique operates to encode an original 4-bit information word into a 6-bit code word, each 6-bit code word exhibiting zero disparity. It will be appreciated that a 4-bit code word is capable of representing only sixteen different words, and that there are twenty zero disparity words available in 6-bit codes.
  • each of the four 8-bit information words which must be represented by a non-zero disparity code word is represented by one positive disparity code word and one negative disparity code word.
  • a non-zero disparity code word of, for example, positive disparity is selected, the next-selected non-zero disparity code word exhibits negative disparity.
  • the overall digital sum variation is minimized.
  • the wavelength of the recorded digital signal may become too short. That is, many of the code words which will be recorded include successive bit transitions, such as 101010 . . . , resulting in a high frequency of transitions and, thus, a short wavelength. This high transition density results in a reduction in the recording density, which is a disadvantage. It is desirable, therefore, to increase the minimum wavelength of the encoded digital signal to be recorded, as by increasing the minimum interval, or separation, between successive bit transitions.
  • the ratio of the maximum to minimum transition time intervals (T max /T min ) is equal to 10.
  • Such a large ratio may result in waveform interference and, moreover, may deleteriously influence the self-clocking of the reproduced 10-bit code word.
  • the detecting window during which each bit of the 10-bit code word must be detected, or sensed, in order to discriminate binary "1"s from "0"s is reduced to the bit interval of the 10-bit code word, or 0.8T.
  • there is less time to discriminate the bits of the 10-bit code word and this may result in erroneous decoding of the digital signals and re-conversion back to original analog form.
  • Another object of this invention is to provide an improved method and apparatus for encoding n-bit information words into m-bit code words.
  • a still further object of this invention is to provide a n, m encoding technique wherein the resultant code words exhibit minimal digital sum variation.
  • An additional object of this invention is to provide an improved n, m encoding technique wherein the interval between transitions of the n-bit code words is greater than a predetermined amount and, preferably, is greater than two bit cell intervals.
  • Yet another object of this invention is to provide an improved method and apparatus for encoding successive n-bit information words into successive m-bit code words, the latter being readily adapted for magnetic recording.
  • Another object of this invention is to provide an improved (n, m) encoding technique wherein the encoded digital signal, if magnetically recorded, exhibits a satisfactory wavelength.
  • a method and apparatus are provided for encoding successive n-bit information words into successive m-bit code words having no less than a predetermined interval between bit transitions.
  • Each n-bit information word is assigned with a respective set of m-bit code words. Some of these sets are formed of two code words, and the remaining sets are formed of four code words.
  • the two code words both exhibit zero disparity and commence with opposite binary bits (i.e. one commences with a binary "0" and the other commences with a binary "1").
  • the 4-code word sets two of the code words exhibit positive disparity and the other two exhibit negative disparity but of the same absolute magnitude.
  • the positive disparity code words commence with opposite bits, and the negative disparity code words likewise commence with opposite bits.
  • a particular set of code words is selected by the n-bit information word that is to be encoded, and the particular code word which is chosen from the selected set commences with the same bit as the last bit of the immediately preceding code word and, moreover, exhibits a disparity that, when combined with the digital sum variation of the preceding encoded code words, reduces the overall digital sum variation toward zero.
  • a 4-bit information word is converted into an 8-bit code word.
  • the minimum interval between bit transitions is no less than two bit intervals.
  • the maximum interval between bit transitions is no greater than nine bit intervals.
  • At least two consecutive "interior" bits of the code word are of the same logical sense.
  • the "interior” bits are those bits which lie between the first (or most significant bit) and last (or least significant bit) bits.
  • the "interior” bits are the second, third, fourth, fifth, sixth and seventh bits, and two consecutive ones of these bits exhibit the same logical sense. That is, at least two consecutive interior bits are binary "1"s or "0"s.
  • FIG. 1 is a chart which represents the various sets of, for example, 8-bit code words which may be used to represent each 4-bit information word;
  • FIG. 2 is a chart of those sets of 8-bit words selected from the chart of FIG. 1 which are used in the present invention to represent the 4-bit information words;
  • FIG. 3 is a block diagram of one embodiment of the present invention.
  • FIGS. 4A-4F are timing diagrams which are useful in understanding the operation of the embodiment shown in FIG. 3;
  • FIG. 5 is a chart showing those m-bit code words which satisfy the criteria of the encoding technique in accordance with the present invention.
  • FIG. 1 is a chart representing these thirty-one different sets, each set consisting of complementary 8-bit words. The two columns identified as "GP" list these complementary 8-bit words. For convenience, the words included in the left column all commence with a binary "0", and all the words in the right column are respective complements thereof and all commence with a binary "1".
  • “c” represents the disparity of the 8-bit word.
  • the 8-bit word included in sets Nos. 1-9 are identified as GP (4, 0, 0), wherein there are an equal number of binary "0”s and “1”s, each 8-bit word commences with a binary "0”, and the disparity of each word is equal to zero.
  • Sets Nos. 1-9 also include the binary words identified as GP (4, 1, 0), wherein there are an equal number of "0"s and "1”s, each 8-bit word commences with a binary "1", and the disparity of each word is equal to zero.
  • Sets Nos. 10-15 include the 8-bit words identified as GP (5, 0, 2), wherein there are five bits of one logic sense and three bits of the other, each 8-bit word commences with a binary "0", and the disparity of each 8-bit word is equal to +2 (thus indicating that there are five binary "1”s).
  • GP GP
  • -2 the 8-bit words identified as GP (5, 1, -2), wherein there are five binary "0"s in each word, each word commences with binary "1", and the disparity of each word is equal to -2.
  • Sets Nos. 16-23 are identified as the 8-bit words GP (5, 0, -2), wherein each word contains five binary "0”s, each word commences with a binary "0”, and each word exhibits a disparity equal to -2; and these sets also are identified by the 8-bit words GP (5, 1, 2), wherein each word contains five binary "1”s, each word commences with a binary "1” and each word exhibits a disparity equal to +2.
  • Sets Nos. 24 and 25 are identified by the 8-bit words GP (6, 0, 4), wherein each word contains six binary "1”s, each word commences with a binary "0” and each word has a disparity equal to +4. These sets also are identified by the 8-bit words GP (6, 1, -4), wherein each 8-bit word contains six binary "0”s, each word commences with a binary "1” and each word exhibits a disparity equal to -4.
  • sets Nos. 26-31 are identified by the 8-bit words GP (6, 0, -4), wherein each word contains six binary "0”s, each word commences with a binary "0” and each word exhibits a disparity equal to -4.
  • sets also are identified by the 8-bit words GP (6, 1, 4), wherein each word contains six binary "1”s, each word commences with a binary "1” and each word exhibits a disparity equal to +4.
  • each set of 8-bit words also includes a designation CC (d, e, f). In this designation,
  • d represents the number of consecutive bits, commencing with the first, or left-most bit, having the same logical sense
  • f represents the consecutive number of bits, commencing with the last, or right-most bit, of the same logical sense.
  • the first nine sets (sets Nos. 1-9) all are formed of zero disparity code words.
  • each set is formed of a pair of complementary code words, and each pair of code words is used to represent a respective 4-bit information word.
  • both words in set No. 1 that is, words [00001111] and [11110000] are used to represent the 4-bit information word [0000].
  • both words included in set No. 2 are used to represent the 4-bit information word [0001].
  • each of sets Nos. 1-9 is used to represent a respective one of the first nine 4-bit information words [0000], [0001], . . . [1000].
  • These sets of code words are seen to be the GP (4, 0, 0) and GP (4, 1, 0) code words.
  • the remaining sets Nos. 10-31 are formed of non-zero disparity code words.
  • each of the first nine 4-bit information word is represented by a pair of complementary zero disparity code words
  • the non-zero disparity code words representing the remaining 4-bit information words are grouped into sets of four words each.
  • Each set of four code words is used to represent a respective one of the remaining seven 4-bit information words.
  • one of these 4-bit information words may be represented by a code word having positive or negative disparity and may commence with a binary "0" or "1".
  • the 4-bit information word [1001] may be represented by the complementary pairs of code words included in set No. 10 and also by the complementary pairs of code words included in set No. 17.
  • These four code words constitute one set of code words which is assigned to, and thus representative of, the 4-bit information [1001].
  • the 4-bit information word [1010] is represented by the pair of complementary code words included in set No. 11 and also by the pair of complementary code words included in set No. 18.
  • the 4-bit information word [1011] is represented by the pair of complementary code words included in set No. 12 and also by the pair of complementary code words included in set No. 19.
  • the code words included in sets Nos. 13 and 21 are assigned to, and thus represent, the 4-bit information word [1100].
  • the code words included in sets Nos. 14 and 22 are assigned to represent the 4-bit information word [1101]; and the code words included in sets Nos.
  • the last 4-bit information word [1111] should be represented by one 8-bit code word from each of the groups GP (6, 0, 4), GP (6, 1, -4), GP (6, 0, -4) and GP (6, 1, 4). It is preferred to assign the complementary pairs of code words included in sets Nos. 24 and 28 to this information word.
  • one set of code words included in the groups GP (7, 0, -6), GP (7, 1, 6), GP (7, 0, 6) and GP (7, 1, -6) also may satisfy the aforementioend basic criteria.
  • this set of code words is less advantageous for magnetic recording and, therefore, is not used to represent a 4-bit information word.
  • the sixteen 4-bit information words 0, 1, 2, . . . 15, or [0000], [0001], [0010], . . . [1111] may be represented by the sets illustrated in the chart of FIG. 2.
  • the 4-bit information words having the numerical values 0-8 are represented by sets Nos.
  • each set is comprised of a pair of complementary zero disparity 8-bit code words.
  • the remaining 4-bit information words having the numerical values 9, 10, 11, 12, 13, 14 and 15 are represented by sets 10 and 17, 11 and 18, 12 and 19, 13 and 21, 14 and 22, 15 and 23, and 24 and 28, respectively.
  • Each of the sets which represent these 4-bit information words is formed of two pairs of non-zero disparity code words, each pair consisting of complementary code words.
  • successive information words are encoded into corresponding, successive code words, with the first or beginning bit of a code word being of the same logical sense as the last, or terminating bit of the immediately preceding code word.
  • an information word is to be represented by a non-zero disparity code word, then, as shown in FIG. 2, one of four code words must be selected to represent that information word. Therefore, in addition to the aforementioned requirement that the code word commence with a bit having the same logical sense as the terminating bit of the immediately preceding code word, the disparity of the selected code word must be such that the digital sum variation for all of the preceding code words be reduced toward zero.
  • each information word which is represented by a non-zero disparity code word is assigned with two code words having positive disparity and commencing with bits of opposite logical sense, and also with two words having negative disparity and also commencing with bits of opposite logical sense.
  • the information word having the numerical value "9” is represented by the two code words [00011111] and [10001111], both of which have positive disparity and commence with bits of opposite logical sense (binaly “0" and binary "1").
  • the information word having the numerical value "8 is represented by the additional code words [01110000] and [11100000] which have negative disparity and commence with bits of opposite logical sense.
  • the information word having the numerical value "9” is represented by two pairs of complementary code words, the words in each pair having equal but opposite disparities and commencing with bits of opposite logical sense.
  • the preceding code word terminates in, for example, a binary "0"
  • the next information word to be encoded has the numerical value "9”
  • either the code word [00011111] or the code word [01110000] is selected.
  • the particular one of these code words which is selected is a function of the digital sum variation. If the digital sum variation which has been accumulated from the preceding code words is positive, then the one code word having negative disparity, that is, code word [01110000] will be chosen. Alternatively, if the digital sum variation which has been accumulated from the preceding code words is negative, then the code word having positive disparity, that is, the code word [00011111] is chosen.
  • each information word is represented by at least one pair of complementary code words.
  • complementary code words to represent the same information word is advantageous, it is not an absolute necessity.
  • the advantage of using complementary code words is the ability to decode a reproduced code word even if the polarity of that reproduced word is reversed, as by inadvertently reversing the polarity of the reproducing head. For example, let it be assumed that the code word [00110011] is recorded. Let it be further assumed that, because of polarity reversal at the reproducing head, this code word is reproduced as [11001100]. From the chart shown in FIG. 2 it will be seen that, notwithstanding this polarity reversal of the reproducing head, the information word having the numerical value "4" is satisfactorily decoded.
  • FIG. 3 One embodiment of encoding apparatus for carrying out the present invention is illustrated in FIG. 3.
  • This apparatus includes a memory device, such as a read only memory (ROM) 12, which is adapted to store a "look-up" table corresponding to the chart shown in FIG. 2, another ROM 15, which is adapted to store a representation of the disparity of each of the code words stored in ROM 12, an adder 16, a temporary store, or latch circuit 17 and another ROM 18.
  • ROM 12 includes address terminals A 0 -A 3 which are adapted to receive the respective bits of an input 4-bit information word.
  • the information word D in is comprised of bits A 0 , A 1 , A 2 , A 3 and is temporarily stored in a latch circuit 11 in response to a latch pulse CKA supplied to the clock terminal of the latch circuit.
  • the temporarily stored 4-bit information word is used to select a respective one of the sixteen sets stored in ROM 12, which set contains the code words that represent the received information word.
  • ROM 12 includes two additional address terminals A 4 and A 5 which are coupled to ROM 18. These additional address terminals A 4 and A 5 received additional address bits which serve to select the particular code word included in the set of code words which has been initially selected, or addressed, by the input information word.
  • address bit A 4 is used to select, or address, the code word or words included in the initially selected set which commences with a bit having the same logical sense as the last bit of the previously selected code word.
  • Additional address bit A 5 is used to select, or address, the code word included in the selected set having proper disparity.
  • the 8-bit code word which is addressed by address bits A 0 -A 5 is read out from ROM 12, preferably in parallel, and temporarily stored in a latch circuit 13 in response to latch pulse CKA.
  • This 8-bit code word is supplied to ROM 15 and is used as an address to read out from ROM 15 the digital representation of the disparity of this temporarily stored 8-bit code word.
  • a disparity calculating circuit may be provided in place of ROM 15.
  • the disparity calculating circuit may include a counter whose count is incremented in response to each binary "1" and whose count is decremented in response to each binary "0". Such a counter may be used to provide a running total, or sum, of the digital sum variation of successively provided 8-bit code words.
  • Other examples of a disparity calculating circuit which may be used in place of ROM 15 are described in aforementioned copending application Ser. No. 201,781.
  • the last, or least significant, bit of the 8-bit code word read out of ROM 12 and temporarily stored in latch circuit 13 is supplied to ROM 18. This least significant bit is used to generate address bit A 4 and, alternatively, may be supplied directly to address bit terminal A 4 of ROM 12.
  • Adder 16 is coupled to ROM 15 to sum the disparity of the 8-bit code word temporarily stored in latch circuit 13 with the digital sum variation of the preceding, successive code words. It is seen that the digital sum variation thus is updated with the disparity of this code word.
  • the updated digital sum variation is provided at the output of adder 16 and is stored in latch circuit 17 in response to latch pulse CKA.
  • latch circuit 17 stores the digital sum variation derived from the preceding, successive code words, and this digital sum variation is summed in adder 16 with the disparity of the latest code word that is read out from ROM 12. It will be appreciated that, when the next input information word is supplied to ROM 12, latch circuit 17 is triggered to store the updated digital sum variation produced at the output of adder 16. This permits the disparity of the next-produced code word to be summed with the digital sum variation that has been derived from all of the preceding successive code words.
  • the updated digital sum variation produced at the output of adder 16 also is coupled to ROM 18. If the digital sum variation is, for example, positive, ROM 18 is responsive thereto to produce the address bit A 5 which addresses, or selects, a code word having negative disparity. Alternatively, if the updated digital sum variation is negative, ROM 18 produces address bit A 5 which calls for a code word having positive disparity. Since the digital sum variation is constrained within predetermined limits, all possible values of the digital sum variation within this range may be used as an address signal, and ROM 18 may store an appropriate binary "1" or "0" at each addressable location therein. Alternatively, the polarity of the updated digital sum variation provided at the output of adder 16 may be detected, and this detected polarity then may be used to produce a binary "1" or "0" address bit A 5 .
  • the temporarily stored 8-bit code word in latch circuit 13 also is supplied to a shift register 14 and is loaded therein in response to a negative-going load pulse LDP.
  • the code word stored in shift register 14 then is read out therefrom, serially-by-bit, in response to successive clock pulses CKC.
  • the serially read out code word D out then may be recorded.
  • FIG. 4A represents the clock pulses CKC which are supplied to shift register 14 and which are used to read out the stored 8-bit code word therefrom, serially-by-bit.
  • a suitable source (not shown) of clock pulses may be provided; and a frequency divider may be used to divide the frequency of those clock pulses to produce the latch pulse CKA shown in FIG. 4B.
  • latch circuit 11 may be triggered in response to the positive transition of latch pulse CKA to store the 4-bit input information word S i , as illustrated in FIG. 4C.
  • the first input information word S 1 is stored in latch circuit 11.
  • latch circuit 11 stores the input information word S 1
  • the 8-bit code word MPS which had been produced to represent the preceding information word is stored in latch circuit 13.
  • the updated digital sum variation that had been produced at the output of adder 16 is stored in latch circuit 17.
  • the disparity of the preceding code word stored in latch circuit 13 is determined by ROM 15. This disparity is summed in adder 16 with the digital sum variation derived from those code words which went before the preceding code word, which digital sum variation now is stored in latch circuit 17. The updated digital sum variation produced at the output of the adder is used by ROM 18 to produce the address bit A 5 . Furthermore, the updated digital sum variation is stored in latch circuit 17 in response to the next latch pulse CKA.
  • Suitable circuitry may be provided to produce the load pulse LDP shown in FIG. 4A.
  • the load pulse may be produced in response to the negative transition of latch pulse CKA.
  • a counter circuit may be provided to produce the load pulse LDP after, for example, eight successive clock pulses CKC are counted.
  • shift register 14 is loaded with the 8-bit code word stored in latch circuit 13 in response to the positive transition of the load pulse LDP shown in FIG. 4E. Thereafter, from time t 2 , for example, the code word loaded into shift register 14 is serially read out therefrom, as represented in FIG. 4F.
  • the code word MPS 1 which represents the information word S 1 is loaded into latch circuit 13.
  • the next-following input information word S 2 is loaded into latch circuit 11, as shown in FIG. 4C.
  • the respective bits of information word S 2 are used as the address bits A 0 -A 3 , respectively, for selecting the appropriate set of code words to represent information word S 2 .
  • the least significant bit of code word MPS 1 is used to produce address bit A 4 , thus designating the first, or most significant, bit of code word MPS 2 which will be used to represent information word S 2 .
  • ROM 15 determines the disparity of code word MPS 1 , now stored in latch circuit 13, and this disparity is summed with the digital sum variation derived from all of the preceding code words. The resultant updated digital sum variation is produced at the output of adder 16 and is used by ROM 18 to produce address bit A 5 . Hence, ROM 12 now is addressed to supply the appropriate code word MPS 2 to represent the information word S 2 . At the next latch pulse CKA, which is produced at time t 5 , this next code word MPS 2 is loaded into latch circuit 13.
  • Code word MPS 1 once loaded into shift register 14, is serially read out therefrom in response to each clock pulse CKC, as shown in FIG. 4F.
  • code word MPS 1 terminates in a binary "1”
  • information word S 2 has the numerical value "4".
  • ROM 12 is addressed by this information word to select set No. 5 which, as shown in FIG. 2, includes the code words [00110011] and [11001100]. Since the least significant bit of the preceding code word has been assumed to be a binary "1”, address bit A 4 selects the code word [11001100] from set No. 5.
  • the disparity of each of the code words included in set No. 5 is equal to zero. Hence, further discrimination of the code word included in this set is independent of the preceding digital sum variation.
  • ROM 12 is addressed by this information word to select sets Nos. 13 and 21. Since the preceding code word terminated in a binary "0", address bit A 4 now supplied to ROM 12 serves to select the code word [01100111] from set No. 13 and to select the code word [01100001] from set No. 21.
  • the left-most column represents the number of bits m included in the code word
  • the top-most row represents the number a of majority bits included in that m-bit code word.
  • the right-most column of FIG. 5 represents the total number of available sets for each of the m-bit code words. It is recognized that the number of available sets when the code word is formed of m bits must be equal to or greater than 2 n .
  • 6-bit code words may be used to represent 2-bit information words
  • 7-bit code words may be used to represent 3-bit information words
  • 8-bit and 9-bit code words may be used to represent 4-bit information words
  • 10-bit and 11-bit code words may be used to represent 5-bit information words
  • 12-bit code words may be used to represent 6-bit information words
  • 13-bit code words may be used to represent 7-bit information words
  • 14-bit and 15-bit code words may be used to represent 8-bit information words
  • 16-bit code words may be used to represent 9-bit information words.
  • each set of code words is formed of four individual code words, two of which exhibit positive disparity and the other two of which exhibit negative disparity. Furthermore, and in accordance with the aforementioned criteria, one of the positive disparity code words commences with a binary "0" and the other commences with a binary "1". Likewise, one of the negative disparity code words commences with a binary "0" and the other commences with a binary "1". From the chart shown in FIG. 5, it is seen that, from the available 9-bit code words, twelve sets of code words are available with five binary "0"s or "1"s.
  • each set of code words may be formed of four separate code words two of which commence with a binary "0" and exhibit disparities of equal but opposite polarities, and the other two of which commence with binary "1" and also exhibit disparities of equal magnitude but opposite polarities.
  • one set of 9-bit code words thus may be formed of:
  • the number of bits m included in the code word is less than 8
  • the number of bits n included in the information word must be less than one-half the number of code word bits.
  • the number of bits n included in the information word may be more than one-half the number of code-word bits. That is, when m ⁇ 12, 2n ⁇ m.
  • 13-bit code words may be used to represent 7-bit information words
  • 14-bit code words may be used to represent 8-bit information words
  • 16-bit code words may be used to represent 9-bit information words.
  • the use of the present invention to utilize a code word having less than twice the number of bits included in the information word is advantageous in that the wavelength of the recorded digital signal may be minimized and the bit-detecting window may be larger than when the code word contains twice the number of bits as the information word.
  • FIG. 3 One embodiment of apparatus which is used to carry out the encoding technique of the present invention is illustrated in FIG. 3.
  • the illustrated circuit may be modified, as described in the preceding discussion; and other equivalent encoding circuits may be used. It is intended that the appended claims be interpreted as including such changes and modifications.

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US06/380,336 1981-05-26 1982-05-20 Method and apparatus for N-to-M encoding Expired - Lifetime US4517552A (en)

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JP56079677A JPS57195308A (en) 1981-05-26 1981-05-26 Block coding method
JP56-79677 1981-05-26

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AU (1) AU548434B2 (enrdf_load_stackoverflow)
CA (1) CA1193016A (enrdf_load_stackoverflow)
DE (1) DE3219439A1 (enrdf_load_stackoverflow)
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GB (1) GB2099263B (enrdf_load_stackoverflow)
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US6232895B1 (en) * 1997-01-17 2001-05-15 Telefonaktiebolaget Lm Ericsson Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords
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US4730223A (en) * 1984-06-08 1988-03-08 Hitachi, Ltd Method of converting a digital data signal having a first length into a digital data signal having a second length
US4709227A (en) * 1985-04-04 1987-11-24 Societe Anonyme De Telecommunications Method and device for inserting a digital signal in a channel with higher flow rate
US4775985A (en) * 1987-04-06 1988-10-04 Sony Corporation Method of dc-free 8/9 nrz coding using a unique sync word pattern
US5192949A (en) * 1989-08-31 1993-03-09 Sony Corporation Digital data transmission system having error detecting and correcting function
WO1991005335A1 (en) * 1989-09-29 1991-04-18 Eastman Kodak Company Digital optical sound system
US5099237A (en) * 1990-07-10 1992-03-24 Research Corporation Technologies, Inc. Method and apparatus for providing maximum rate modulation or compression encoding and decoding
US5349349A (en) * 1991-09-30 1994-09-20 Sony Corporation Modulator circuit for a recording for a digital recording medium
US5625644A (en) * 1991-12-20 1997-04-29 Myers; David J. DC balanced 4B/8B binary block code for digital data communications
US5469162A (en) * 1992-03-31 1995-11-21 Sony Corporation Data modulation method
US5696505A (en) * 1994-02-15 1997-12-09 U.S. Philips Corporation Method of converting a series of m-bit information words to a modulated signal, method of producing a record carrier, coding device, decoding device, recording device, reading device, signal, as well as record carrier
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US5684479A (en) * 1994-07-29 1997-11-04 Okuma Corporation Communication device performing code conversion between binary data and serial data
US6054944A (en) * 1996-11-22 2000-04-25 Sony Corporation Data transmission method and device using 8-10 bit conversion and successive plus and minus running disparity synchronous data words
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US6232895B1 (en) * 1997-01-17 2001-05-15 Telefonaktiebolaget Lm Ericsson Method and apparatus for encoding/decoding n-bit data into 2n-bit codewords
US6642864B1 (en) 1997-01-17 2003-11-04 Telefonaktiebolaget Lm Ericsson Method and apparatus for encoding/decoding N-bit data into 2N-bit codewords
WO2000021198A1 (en) * 1998-10-01 2000-04-13 Koninklijke Philips Electronics N.V. Generation of a runlength limited digital information signal
US6639524B2 (en) * 2000-03-22 2003-10-28 Lg Electronics Inc. Method and apparatus for coding information, method and apparatus for decoding coded information, method of fabricating a recording medium, the recording medium and modulated signal
US20030048210A1 (en) * 2001-07-16 2003-03-13 Oliver Kiehl Transmission and reception interface and method of data transmission
US6927709B2 (en) * 2001-07-16 2005-08-09 Infineon Technologies Ag Transmission and reception interface and method of data transmission
US6563436B2 (en) * 2001-09-24 2003-05-13 Zenith Electronics Corporation Kerdock coding and decoding system for map data
US6985092B2 (en) 2001-09-24 2006-01-10 Zenith Electronics Corporation Robust system for transmitting and receiving map data
US20050046600A1 (en) * 2001-09-24 2005-03-03 Bretl Wayne E. Robust system for transmitting and receiving map data
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US20040160344A1 (en) * 2003-02-18 2004-08-19 Bretl Wayne E. Robust system for transmitting and receiving map data
US6861964B2 (en) 2003-02-18 2005-03-01 Zenith Research Corporation Robust system for transmitting and receiving map data
US6961010B2 (en) * 2003-08-13 2005-11-01 Seagate Technology Llc DC-free code design with increased distance between code words
US20050040976A1 (en) * 2003-08-13 2005-02-24 Seagate Technology Llc DC-free code design with increased distance between code words
US20050289261A1 (en) * 2004-06-28 2005-12-29 White Theodore C System and method for reading and writing data using storage controllers
US8166217B2 (en) * 2004-06-28 2012-04-24 Marvell International Ltd. System and method for reading and writing data using storage controllers
US20060267810A1 (en) * 2005-05-31 2006-11-30 International Business Machines Corporation Nb/mb coding apparatus and method using both disparity independent and disparity dependent encoded vectors
WO2006130467A1 (en) * 2005-05-31 2006-12-07 International Business Machines Corporation Nb/mb coding apparatus and method using both disparity independent and disparity dependent encoded vectors
US7292161B2 (en) 2005-05-31 2007-11-06 International Business Machines Corporation NB/MB coding apparatus and method using both disparity independent and disparity dependent encoded vectors
US7405679B1 (en) 2007-01-30 2008-07-29 International Business Machines Corporation Techniques for 9B10B and 7B8B coding and decoding
US20080180287A1 (en) * 2007-01-30 2008-07-31 International Business Machines Corporation Techniques for 9b10b and 7b8b coding and decoding
US7592933B2 (en) 2007-01-30 2009-09-22 International Business Machines Corporation Techniques for 9B10B and 7B8B coding and decoding

Also Published As

Publication number Publication date
DE3219439C2 (enrdf_load_stackoverflow) 1991-09-12
NL8202159A (nl) 1982-12-16
GB2099263B (en) 1985-03-20
AT384695B (de) 1987-12-28
CA1193016A (en) 1985-09-03
JPS57195308A (en) 1982-12-01
AU8316382A (en) 1982-12-02
FR2507029B1 (fr) 1986-02-28
ATA207682A (de) 1987-05-15
FR2507029A1 (fr) 1982-12-03
AU548434B2 (en) 1985-12-12
JPH0544206B2 (enrdf_load_stackoverflow) 1993-07-05
GB2099263A (en) 1982-12-01
DE3219439A1 (de) 1982-12-16

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