US4507621A - Generating quasi-random sequences in AMI code - Google Patents

Generating quasi-random sequences in AMI code Download PDF

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Publication number
US4507621A
US4507621A US06/500,947 US50094783A US4507621A US 4507621 A US4507621 A US 4507621A US 50094783 A US50094783 A US 50094783A US 4507621 A US4507621 A US 4507621A
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differential amplifier
input
transistor
collector
output
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US06/500,947
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Fritz Meyer
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Siemens AG
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Siemens AG
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Assigned to SIEMENS AKTIENGESELLSCHAFT BERLIN AND MUNICH A GERMAN CORP reassignment SIEMENS AKTIENGESELLSCHAFT BERLIN AND MUNICH A GERMAN CORP ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MEYER, FRITZ
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • H04L1/244—Testing correct operation by comparing a transmitted test signal with a locally generated replica test sequence generators

Definitions

  • the invention relates to an arrangement for generating quasi-random sequences in AMI code by use of a generator for binary quasi-random sequences.
  • a code frequently employed in the transmission of digital signals is the so-called AMI code which is a pseudoternary code in which successive one characters are transmitted by means of pulses having alternating polarity, whereas zero characters are allocated to the zero level.
  • a problem in the surveillance of transmission circuits for digital signals through investigation of such signals for coding rule infractions or violations is the occasional check of the coding rule infraction test units contained at specific locations in the transmission circuit. For this check, for example, AMI-coded test signals are required which are locally generated in response to an additionally transmitted signal. The AMI-coded test signals are also required in a final check after a manufacture of regenerators having code infraction test units.
  • AMI-coded signals usually occurs by connecting a spur line in parallel to the output of a generator for test signals present in the differential binary code.
  • a spur line is short-circuited at the end and its single signal transit time corresponds to half the bit duration of the signals to be reshaped.
  • a negative pulse which appears at the input of the spur line one bit duration after the positive pulse, is generated by means of reflection of a positive pulse, for example, at the short-circuited end of the spur line.
  • Such a technique for generating AMI-coded signals is not suitable for generating test signals since the observation of the AMI coding rule is induced by the employment of a spur line whereas the test signals must contain a specific plurality of coding rule infractions.
  • An object of the present invention is to discover a possibility for generating AMI-coded test signals with a specific plurality of coding rule infractions so that the test signals should exist in the form of quasi-random sequences for the execution of an optimum test.
  • the differential amplifier arrangement contains two emitter-coupled differential amplifiers.
  • the first of the differential amplifiers has two npn transistors whose emitters are connected to one another and, over a first current source, are connected to a terminal for the negative operating voltage.
  • the base terminal of the first transistor is connected to the first input of the differential amplifier arrangement and the base terminal of the second transistor is connected to a reference voltage source.
  • the collector terminal of the first transistor is connected to an output for the inverse output signal and, over a first resistor, is connected to a reference potential.
  • the collector terminal of the second transistor is connected to a signal output and, over a second resistor, is connected to the reference potential.
  • the second differential amplifier has a third and a fourth npn transistor whose emitter terminals are connected to one another and, over a second current source, are connected to the negative operating voltage.
  • the collector terminal of the third transistor is connected to the collector terminal of the second transistor and the collector terminal of the fourth transistor is connected to the collector terminal of the first transistor.
  • the base terminal of the fourth transistor is connected to the base terminal of the second transistor and the base terminal of the third transistor is connected to the second input of the differential amplifier arrangement.
  • the invention offers a series of advantages.
  • the arrangement is easy to integrate overall.
  • the system also has a low power requirement given a simple structure.
  • the two load resistors are replaced by a single load resistor having a preceding line transformer.
  • the line transformer comprises two two-wire lines of equal length.
  • the first two-wire line is wound on a highly permeable core and a first lead of the first two-wire line is connected at one side to the output terminal for the complementary output signal and, at the other side, is connected to the reference potential.
  • the second lead of the first two-wire line is connected to the reference potential over a first terminal adjacent to the first terminal of the first lead and is connected over a second terminal to the shared load resistor as well as to a second terminal of the first lead of the second two-wire line.
  • the first terminal of the first lead of the second two-wire line is connected to the output terminal for the output signal.
  • the two terminals of the second lead of the second two-wire line are connected to the reference potential.
  • the terminals of the individual leads are respectively provided at the ends of the two-wire lines.
  • a modification of the invention is suited for employment with low frequencies, the time-delay element being realized by means of an electrical circuit arrangement, particularly by a clocked shift register.
  • FIG. 1 illustrates the circuit diagram of an inventive arrangement for generating quasi-random sequences in AMI code with a modification in FIG. 1a for generating higher power output pulses;
  • FIG. 2 shows a pulse diagram referring to the arrangement according to FIG. 1.
  • the arrangement for generating quasi-random sequences in AMI code according to FIG. 1 contains a generator PNG for generating binary quasi-random sequences which receives a clock signal over a terminal C1.
  • the one terminal of an exclusive OR element EXOR as well as a first input E1 of a differential amplifier arrangement are connected to the output E of the generator PNG.
  • the differential amplifier arrangement contains two emitter-coupled differential amplifiers, whereby the first differential amplifier contains a first and a second npn transistor T1, T2 whose emitter terminals are connected to one another and, over a current source I1 in the form of a resistor, is connected to a terminal for the operating voltage -Ub.
  • the collector terminal of the first transistor T1 is connected to an output terminal A for the inverse output signal and, over a first resistor R1, is connected to the reference potential.
  • the collector terminal of the second transistor T2 is connected to an output terminal A for the non-inverted output signal and, over a second resistor R2, is connected to the reference potential.
  • the second differential amplifier of the differential amplifier arrangement contains a third and a fourth npn transistor T3, T4 whose emitter terminals are likewise connected to one another and, via a current source for the current I2, are connected to a terminal for the operating voltage -Ub.
  • the collector terminal of the third transistor T3 is connected to the collector terminal of the second transistor T2, and the collector terminal of the fourth transistor T4 is connected to the collector terminal of the first transistor T1.
  • the base terminals of the second transistor T2 and of the fourth transistor T4 are connected to one another and to a source for a reference voltage Ur, whereby said reference voltage lies between the two logical levels of the input signal.
  • the other terminal of the exclusive OR element EXOR is connected to an input P to which external signals are supplied by means of which the coding rule infractions are to be triggered in the generated AMI-coded quasi-random sequence.
  • the second input E2 of the differential amplifier arrangement which corresponds to the base terminal of the third transistor T3 is connected to the output terminal of the exclusive OR element over a time-delay element V.
  • the time-delay element V is realized by an electronic delay unit.
  • a line matched in terms of its characteristic impedance is provided as the time-delay element V.
  • the function of the circuit arrangement according to FIG. 1 is as follows.
  • the quasi-random sequence generator PNG generates a binary quasi-random pulse sequence which is supplied to the differential amplifier arrangement.
  • the sequence is supplied directly on the one hand and delayed on the other hand by the exclusive OR element and the time-delay element.
  • the overall time-delay in the exclusive OR element and in the time-delay element thereby corresponds to a bit duration of the binary signals generated by the generator PNG.
  • the conversion of the binary quasi-random sequence into an AMI-coded quasi-random sequence ensues in the differential amplifier arrangement, said AMI-coded quasi-random sequence being taken directly at the output terminal A or, in inverse form, at the output terminal A.
  • the signals at the inputs E1 and E2 of the differential amplifier arrangement can assume the logical statuses 0 and 1, whereby the status 1 is allocated to the higher potential.
  • the signals at the input terminals E1 and E2 can form four different combinations which produce three different logical statuses at the signal output A. Capable of occurring as the first combination of the binary signals is the case where the logical level at the first input E1 is at the value 1, whereas the 0 level is present at the other input E2. This leads to a positive 1 level at the output terminal A.
  • the logical 1 level can be adjacent to the second input E2 whereas the 0 level corresponds to the lowest and the positive 1 level corresponds to the highest potential.
  • the transistors T1 and T4 are conductive. Consequently, both the current I1 as well as the current I2 flow through the first resistor R1, whereas the second resistor R2 remains nearly current-free and the highest potential and thus the status +1 therefore occurs at this resistor.
  • the transistors T2 and T3 are correspondingly conductive so that both currents then flow through the second resistor R2 and the lowest potential corresponding to the -1 level occurs at it and thus at the signal output A.
  • the time-delay element V has a delay corresponding to a bit duration of the binary signals.
  • a signal in the differential binary code appears at the output terminal E of the pseudo-random sequence generator PNG, then this signal appears practically simultaneously at the first input E1 and appears one bit duration later at the second input E2.
  • a change of potential for example from 0 to 1 at the terminal E, thus leads directly to a positive one level at the output terminal A and leads to a signal with negative one level at this terminal one bit duration later.
  • binary quasi-random sequences are generated by the pseudo-random sequence or number generator PNG, then quasi-random sequences which exist in AMI code also result at the output terminal A.
  • An interchange of the two input terminals E1 and E2 just like the interchange of the two output terminals A and A, leads to an inverse output signal.
  • the upper line in FIG. 2 illustrates a binary pulse sequence in NRZ format which is emitted by the pseudo-random sequence generator PNG at the terminal E.
  • the center line of FIG. 2 illustrates the signal present at the second input E2 of the differential amplifier arrangement. It turns out that this signal corresponds to the output signal of the pseudo-random sequence generator, however shifted by one bit duration. Illustrated in the lower line is the pseudo-ternary signal appearing at the output terminal A.
  • An inversion In is illustrated with broken lines in the center line, said inversion In having been generated in the signal at the input terminal E2 by means of an input pulse at the terminal P. Without this inversion, the logical 1 level would be present at the two inputs E1 and E2 of the differential amplifier arrangement and thus the logical 0 level would have been generated at the output terminal A. If the logical 0 level is generated due to the inversion at the input terminal E2, then the logical 1 level is thus generated at the output terminal A, said logical 1 level following a logical 1 pulse and thus representing a coding rule infraction CRV. It thus turns out that a coding rule infraction appears at the output side due to the inversion of a single bit in the exclusive OR element.
  • the number of coding rule infractions can be less than the number of mixed-in inversions.
  • the number of coding rule infractions becomes lower because, among other things, the inversion has also converted two successive statuses in the AMI code, for example +1/-1 or -1/+1 into the status 0/0.
  • the errors contained in the quasi-random sequence emitted at the output side are not effective as coding rule infractions in this case.
  • the relative proportion with which these errors appear as coding rule infractions further decreases.
  • FIG. 1a a modification of the sample embodiment is illustrated in FIG. 1a, this modification containing a line transformer.
  • This line transformer known per se is designed as a symmetrical/asymmetrical 4:1 line transformer.
  • the line transformer contains two two-wire lines Lt1 and Lt2 of equal length, whereby the first two-wire line Lt1 is wound on a highly permeable core.
  • the first lead of the first two-wire line Lt1 has a first terminal at one end which is connected to the terminal A for the inverse output signal, whereas the other terminal of the first lead is connected to reference potential.
  • the first terminal of the second lead of the first two-wire line Lt1 which is adjacent to the first terminal of the first lead is connected to the reference potential, whereas the second terminal of the lead is connected to the first lead of the second two-wire line Lt2 and, over a shared load resistor RV, is connected to reference potential.
  • the second terminal of the first lead of the second two-wire line Lt2 is connected to the terminal A for the output signal, whereas the second lead of the second two-wire line Lt2 is connected to reference potential at its two end points.
  • the inputs of the lines lie in series at that side of the line transformer facing the differential amplifier arrangement, whereas the outputs of the lines are connected in parallel at the asymmetrical side facing the load resistor.
  • a further increase of the output power given an improvement of the edge steepness of the generated signals is possible since the two differential amplifiers of the differential amplifier arrangement are driven push-pull upon elimination of the reference voltage source.
  • An improvement of the edge steepness is further possible since the collector capacitance of the transistors--increased in the present case due to the parallel connection of two collectors--is compensated by a series inductance in the collector circuit.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Stereo-Broadcasting Methods (AREA)
US06/500,947 1982-06-30 1983-06-03 Generating quasi-random sequences in AMI code Expired - Fee Related US4507621A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823224442 DE3224442A1 (de) 1982-06-30 1982-06-30 Anordnung zur erzeugung von quasizufallsfolgen im ami-code
DE3224442 1982-06-30

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US4507621A true US4507621A (en) 1985-03-26

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US (1) US4507621A (de)
EP (1) EP0097947B1 (de)
JP (1) JPS5910057A (de)
AT (1) ATE37641T1 (de)
DE (2) DE3224442A1 (de)
NO (1) NO832373L (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665531A (en) * 1985-10-01 1987-05-12 Northern Telecom Limited Alternate mark inversion (AMI) receiver
US4745603A (en) * 1986-05-27 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Code sequence generator for a digital transmission line fault location system
US4829541A (en) * 1988-01-22 1989-05-09 Advanced Micro Devices, Inc. Pseudo-ternary code transmitter
US4885545A (en) * 1988-08-08 1989-12-05 Tektronix, Inc. High speed circuit with supporting auxiliary circuit
US4928289A (en) * 1988-12-19 1990-05-22 Systran Corporation Apparatus and method for binary data transmission
US6687632B1 (en) * 1998-01-23 2004-02-03 Trilithic, Inc. Testing of CATV systems

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4960718A (en) * 1985-12-13 1990-10-02 Allied-Signal Inc. MESFET device having a semiconductor surface barrier layer
DE19655110C2 (de) * 1995-12-21 2001-02-15 Advantest Corp Schaltung zum Erzeugen einer Zufalls-Impulsfolge

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965294A (en) * 1974-04-23 1976-06-22 Wandel U. Goltermann Method of and apparatus for testing transmission line carrying bipolar PCM signals
US4071692A (en) * 1975-10-23 1978-01-31 International Standard Electric Corporation Data transmission systems
US4423518A (en) * 1981-05-19 1983-12-27 Nippon Electric Co., Ltd. Timing recovery circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787613A (en) * 1972-06-27 1974-01-22 Bell Telephone Labor Inc Pulse transmission system for conveying data and control words by means of alternating polarity pulses and violations thereof
US3906174A (en) * 1973-11-16 1975-09-16 Gte Automatic Electric Lab Inc Cable pair testing arrangement
FR2350005A1 (fr) * 1976-04-30 1977-11-25 Cit Alcatel Dispositif de generation de suite binaire pseudo-aleatoire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965294A (en) * 1974-04-23 1976-06-22 Wandel U. Goltermann Method of and apparatus for testing transmission line carrying bipolar PCM signals
US4071692A (en) * 1975-10-23 1978-01-31 International Standard Electric Corporation Data transmission systems
US4423518A (en) * 1981-05-19 1983-12-27 Nippon Electric Co., Ltd. Timing recovery circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665531A (en) * 1985-10-01 1987-05-12 Northern Telecom Limited Alternate mark inversion (AMI) receiver
US4745603A (en) * 1986-05-27 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Code sequence generator for a digital transmission line fault location system
US4829541A (en) * 1988-01-22 1989-05-09 Advanced Micro Devices, Inc. Pseudo-ternary code transmitter
US4885545A (en) * 1988-08-08 1989-12-05 Tektronix, Inc. High speed circuit with supporting auxiliary circuit
US4928289A (en) * 1988-12-19 1990-05-22 Systran Corporation Apparatus and method for binary data transmission
WO1990007242A1 (en) * 1988-12-19 1990-06-28 Systran Corporation Apparatus and method for binary data transmission
US6687632B1 (en) * 1998-01-23 2004-02-03 Trilithic, Inc. Testing of CATV systems

Also Published As

Publication number Publication date
ATE37641T1 (de) 1988-10-15
EP0097947A3 (en) 1986-02-19
NO832373L (no) 1984-01-02
DE3378151D1 (en) 1988-11-03
DE3224442A1 (de) 1984-01-05
JPS5910057A (ja) 1984-01-19
EP0097947A2 (de) 1984-01-11
EP0097947B1 (de) 1988-09-28

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