US4485392A - Lateral junction field effect transistor device - Google Patents

Lateral junction field effect transistor device Download PDF

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Publication number
US4485392A
US4485392A US06/334,997 US33499781A US4485392A US 4485392 A US4485392 A US 4485392A US 33499781 A US33499781 A US 33499781A US 4485392 A US4485392 A US 4485392A
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layer
semiconductor layer
gate
buried
source
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US06/334,997
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Barry M. Singer
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Philips North America LLC
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North American Philips Corp
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Priority to US06/334,997 priority Critical patent/US4485392A/en
Assigned to NORTH AMERICAN PHILIP CORPORATION, reassignment NORTH AMERICAN PHILIP CORPORATION, ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SINGER, BARRY M.
Priority to EP82201617A priority patent/EP0083815B1/en
Priority to DE8282201617T priority patent/DE3277159D1/de
Priority to CA000418649A priority patent/CA1193757A/en
Priority to JP57235074A priority patent/JPS58116776A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs

Definitions

  • the invention is in the field of field effect transistor (FET) devices, and relates specifically to lateral junction field effect transistor (JFET) devices.
  • FET field effect transistor
  • JFET lateral junction field effect transistor
  • Such transistors are well-known in the art, and one such device is shown in Japanese Kokai No. 55-153378.
  • This device includes a semiconductor substrate of a first conductivity type (p-type), a first semiconductor layer of a second conductivity type (n-type), and source, gate and drain contact regions located at the surface of the first semiconductor layer, with the gate region being of the first conductivity type and located between the source and drain contact regions, which are of the second conductivity type.
  • This device is electrically isolated from adjacent portions of the first semiconductor layer by isolation zones of the first conductivity type.
  • this device includes a buried semiconductor layer of the second conductivity type which has a doping level less than that of the first semiconductor layer, the buried layer being located between the first layer and the substrate so as to form a p-n junction with the substrate and extend beneath the source, gate and drain contact regions of the device.
  • This lightly-doped buried semiconductor layer has a graduated doping concentration and is included for the purpose of reducing the back gate capacitance of the device.
  • RESURF REduced SURface Field
  • Appels et al Application of the RESURF technique to bipolar transistors, junction field effect transistors and insulated-gate field effect transistors is shown in U.S. Pat. No. 4,292,642 to Appels et al and U.S. Pat. No. 4,300,150 to Colak.
  • the RESURF technique used in these references serves to improve high-voltage device breakdown characteristics by reducing surface field levels through the use of modified thickness and doping characteristics in the semiconductor layers of the device.
  • junction field effect transistors have suffered from several drawbacks which have limited their utility in high-voltage applications.
  • prior-art high-voltage junction field effect transistors using the RESURF technique are not capable of operating effectively in the source-follower mode, due to the high gate potentials and resultant punch-through breakdown associated with this mode of operation.
  • prior-art JFET devices are not normally operated with a forward gate bias in the "on” state because this would be of no advantage in conventional devices, where the injected carriers would simply diffuse into the substrate.
  • the use of forward gate bias in the "on” state would be a potentially valuable technique for enhancing device conductivity in a device configuration in which such forward gate bias could effectively modulate channel resistivity.
  • junction field effect transistor devices are not capable of operating in the source-follower mode and also providing relatively high breakdown voltage levels and a relatively low on-resistance.
  • these objects are achieved by a lateral junction field effect transistor device of the general type described above in which the buried semiconductor layer of the second conductivity type has a doping level greater than that of the first semiconductor layer, and in which a surface semiconductor layer of the first conductivity type is provided at the surface of the first layer and between the gate and drain contact regions of the device.
  • the doping level of the surface layer is on the same order of magnitude as that of the substrate.
  • the buried semiconductor layer extends beneath the drain contact region and the surface layer, although this buried semiconductor layer may additionally extend beneath the gate and source regions, and the buried layer may also be made up of two buried layer portions, one portion extending beneath the drain contact region and the surface layer, while the second portion, which is spaced apart from the first, extends beneath the source region.
  • transistors in accordance with the present invention are theoretically capable of providing a ten-times improvement in on-resistance for a constant breakdown voltage, as compared to prior-art devices using the RESURF technique but not capable of operating with the gate region foward biased in the "on" state.
  • FIG. 1 is a cross-sectional view of a prior art lateral junction field effect transistor device
  • FIG. 2 is a cross-sectional view of a lateral JFET device in accordance with a first embodiment of the invention
  • FIG. 3 is a cross-sectional view of a lateral JFET device in accordance with a second embodiment of the invention.
  • FIG. 4 is a cross-sectional view of a laterial JFET device in accordance with a third embodiment of the invention.
  • FIG. 1 of the drawing shows a prior-art junction field effect transistor as disclosed in Japanese Kokai No. 55-153378. It should be noted that FIG. 1, as well as the remaining figures of the drawing, are not drawn to scale, and in particular the vertical dimensions are exaggerated for improved clarity. Additionally, like parts of FIGS. 2-4 are designated with like reference numerals, and semiconductor regions of the same conductivity type are generally shown hatched in the same direction.
  • a JFET device 1 has a semiconductor substrate 2 of the first (p) conductivity type and a relatively high (p+) doping level.
  • a buried semiconductor layer 3 of the second (n) conductivity type is lightly doped (n-) and located on the substate 2.
  • a first semiconductor layer 4 of the second conductivity type has a higher doping level than that of the buried layer, is located immediately above the buried layer and contains the source region 5, gate region 6 and drain contact region 7 of the device adjacent its upper surface. Source region 5 and drain contact region 7 are of heavily-doped (n+) semiconductor material, while gate region 6 is of p+ semiconductor material.
  • the JFET device is laterally isolated from other elements on the same substrate by p+ regions 8, which form isolating junctions with n-type layers 3 and 4.
  • the purpose of buried layer 3, which is of graduated and higher resistivity (e.g. lower doping level) than that of its overlying layer 4, is simply to reduce the back gate capacitance of the device, and this structure is not particularly adapted for operation in the source follower mode, high voltage operation or operation with a forward-biased gate region to enhance conductivity.
  • FIG. 2 An improved lateral junction field effect transistor device in accordance with the invention is shown in FIG. 2.
  • This device includes a p- semiconductor substrate 11 which has a doping level of about 4 ⁇ 10 14 acceptors/cm 3 .
  • An n-first semiconductor layer 12 is located on the substrate.
  • This first semiconductor layer may typically be an epitaxial layer having a doping concentration of about 5 ⁇ 10 14 donors/cm 3 and a thickness of about 6 microns.
  • Source, gate, and drain contact regions (18, 17/19, and 15/21, respectively) are located at the surface of the first semiconductor layer, with the gate region being of p-type material and having a doping concentration in the order of 10 18 acceptors/cm 3 , while the source and drain contact regions are of n-type material and have a doping level of about 10 20 donors/cm 3 .
  • the device shown in FIG. 2 is symmetrical about the centrally-located source region 18, with the gate and drain contact regions forming concentric annular (in this case rectangular) regions about the source when viewed from above.
  • the two segments of the gate region (17/19) represent a cross-section through a single annular gate region which is located between the source and drain contact regions of the device, while the drain contact region segments (15/21) similarly represent a cross-sectional view through a unitary, annular drain contact region. Since the devices shown in FIGS. 2, 3 and 4 are of the "extended drain” type, the entire drain region includes both the drain contact region 15/21 and that part of the first semiconductor layer 12 which is located adjacent to the drain contact region and extends towards the gate region 17/19. Electrical connections to the source, gate and drain contact regions are made by metallization layer portions 24, 25, and 26/23, respectively, with the connections being made through apertures in an oxide insulating layer 22.
  • the metallization layer portions may typically be of aluminum or polysilicon, while the oxide layer may typically be a silicon oxide layer of one micron thickness.
  • the lateral JFET device 10 is electrically isolated from adjacent portions of the first semiconductor layer 12 by annular isolation region 27 of p-type semiconductor material.
  • This isolation region has a doping concentration of 10 17 -10 18 acceptors/cm 3 , with its p-type semiconductor material forming a vertical p-n isolation junction with the n-type first semiconductor layer 12.
  • isolation region 27 may comprise a sunken oxide region to electrically insulate the device from adjacent portions of the first semiconductor layer.
  • the device also includes an annular p- surface semiconductor layer 16/20 having a doping level on the same order of magnitude as that of the substrate, or about 4 ⁇ 10 14 acceptors/cm 3 , and a thickness of about 1-2 microns.
  • This surface layer is located at the surface of the first semiconductor layer 12 between the gate and drain contact regions.
  • the surface semiconductor layer is shaped in the form of a continuous annular layer when viewed from above, so that layer portions 16 and 20 represent two portions of the same surface layer as seen in cross-section.
  • device 10 includes an n-type buried semiconductor layer 13 which has a doping level greater than that of the first semiconductor layer (typically 10 12 donors/cm 2 with a thickness of 1 micron).
  • This buried layer is located between the first semiconductor layer and the substrate so as to form a lateral p-n isolation junction 14 with the substrate.
  • isolation between the n-type first semiconductor layer 12 and p-type substrate 11 is provided by lateral p-n junction portions 14A located on either side of the buried layer, which extend to meet vertical p-n junction portions 28 and thus complete the electrical isolation of the device.
  • the buried layer extends beneath the surface layer, as well as the source, gate, and drain contact regions of the device.
  • FIGS. 3 and 4 Two further embodiments of the invention are shown in FIGS. 3 and 4. With the exception of the configuration of buried semiconductor layer 14, these embodiments are similar to the configuration shown in FIG. 2. However, while the buried semiconductor layer 14 of FIG. 2 extends continuously beneath the gate, source and drain contact regions, as well as the surface semiconductor layer 16/20, the buried semiconductor layer 14 in FIG. 3 is formed in an annular configuration so as to extend only beneath the drain contact region and the surface layer. Beneath the source and gate regions of the device shown in FIG. 3, electrical isolation is provided by a central portion of the p-n junction 14A formed by the intersection of the first semiconductor layer and the substrate. In FIG.
  • the buried semiconductor layer comprises first and second buried layer portions 13A and 13B, with the first buried layer portion 13A corresponding to the annular configuration of layer 13 in FIG. 3, while the second buried layer portion 13B is a centrally-located portion beneath source region 18 and spaced apart from the first buried layer portion 13A.
  • devices in accordance with the present invention can be operated in the source-follower mode at high voltages.
  • these devices can be operated as switches with both positive and negative gate voltages, with the positive gate voltage serving to forward-bias the gate in order to reduce channel on-resistance during conduction.
  • the use of positive gate voltages during the "on" state would not serve to decrease channel resistivity.
  • devices in accordance with the invention combine these features with improved high voltage capability through the use of a sophisticated "2-stage" RESURF technique which provides effective field control at both intermediate and high voltage levels.
  • this buried semiconductor layer may be provided in several different configurations.
  • a simple, continuous buried layer 13 is provided beneath the source region 18, the gate region 17/19 and the drain contact region 15/21, as well as beneath the surface semiconductor layer 16/20.
  • certain additional advantages can be obtained with further refinements.
  • the buried semiconductor layer 13 is provided in annular form, so that it extends only beneath the drain contact region 15/21 and the surface semiconductor layer 16/20.
  • FIG. 4 A further refinement of this configuration is shown in FIG. 4, where the buried layer includes an annular buried layer portion 13A beneath the drain contact region and the surface semiconductor layer, as previously described, as well as a central buried layer portion 13B.
  • This central buried layer portion is located beneath the source region and spaced apart from the annular layer portion so as to provide a gap in the buried layer beneath the gate region of the device.
  • This configuration permits the cutoff voltage of the device to be selected, as described above, and is particularly advantageous when used in a device having an extended or wide source region to enhance operation in the injection (i.e. forward-biased gate) mode.
  • buried semiconductor layer 13 which serves to improve device performance by preventing punch-through from gate to substrate, presents a potential disadvantage in another area of device performance.
  • devices in accordance with the invention use the RESURF principle in order to operate at high voltages without breakdown, with lightly-doped substrate 11 contributing to the RESURF effect.
  • the use of moderately-doped buried layer 13 substantially reduces the RESURF effect of the lightly-doped substrate, particularly at intermediate drain-to-source voltages (e.g. 150-300 volts for a 400 volt maximum device) where the device would frequently be operated.
  • devices in accordance with the invention are provided with the surface semiconductor layer 16/20 as shown in FIGS. 2-4 and described above.
  • This lightly-doped layer of p-type material located between the gate and the drain contact regions of the device, serves to provide the RESURF effect in the medium operating voltage range by reducing the surface field in first semiconductor layer 12, thus preventing breakdown.
  • buried semiconductor layer 13 becomes depleted, so that the RESURF action of the lightly-doped substrate is no longer prevented.
  • the present invention thus provides a sophisticated "2-stage" RESURF technique, in which "RESURFing” is provided by surface semiconductor layer 16/20 in the medium-voltage range, where buried semiconductor layer 13 blocks the “RESURFing" action of the lightly-doped substrate. Then, as the maximum operating voltage of the device is approached, the buried semiconductor layer becomes depleted and the "RESURFing" effect of the lightly-doped substrate becomes effective. Additionally, the surface layer serves to enhance device operation by collecting minority carriers when the device is switched “off", thus improving turn-off time.
  • gate voltage in the "on" state is normally zero volts. Positive voltages are not normally used on the gate for enhanced conductivity because the additional holes generated would simply diffuse into the substrate and would not decrease channel resistivity.
  • the n-type buried layer 13 serves to trap the additional holes in the device channel and ajoining regions, rather than permit them to diffuse into the substrate as in prior-art devices.
  • devices in accordance with the present invention can advantageously operate with a forwardbiased gate in the "on” state, with the on-resistance of the device substantially reduced because the injected carriers remain in the channel and adjacent regions of the device, rather than simply diffusing into the substrate.
  • junction field effect transistor with both buried and surface semiconductor layers in accordance with the invention, a device having improved high-voltage breakdown characteristics, enhanced channel conductivity in the "on" state, and the capability of operating in the source-follower mode is obtained.
  • the invention may be used to obtain JFET devices with characteristics comparable to those of prior art devices, but which occupy a substantially smaller area and are thus less expensive to manufacture, while still offering the capability of source-follower mode operation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US06/334,997 1981-12-28 1981-12-28 Lateral junction field effect transistor device Expired - Lifetime US4485392A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US06/334,997 US4485392A (en) 1981-12-28 1981-12-28 Lateral junction field effect transistor device
EP82201617A EP0083815B1 (en) 1981-12-28 1982-12-17 Lateral junction field effect transistor device
DE8282201617T DE3277159D1 (en) 1981-12-28 1982-12-17 Lateral junction field effect transistor device
CA000418649A CA1193757A (en) 1981-12-28 1982-12-24 Lateral junction field effect transistor device
JP57235074A JPS58116776A (ja) 1981-12-28 1982-12-27 横方向接合形電界効果トランジスタを具える半導体装置

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US06/334,997 US4485392A (en) 1981-12-28 1981-12-28 Lateral junction field effect transistor device

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US (1) US4485392A (en, 2012)
EP (1) EP0083815B1 (en, 2012)
JP (1) JPS58116776A (en, 2012)
CA (1) CA1193757A (en, 2012)
DE (1) DE3277159D1 (en, 2012)

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642674A (en) * 1983-06-13 1987-02-10 U.S. Philips Corporation Field effect semiconductor device having improved voltage breakdown characteristics
US4684992A (en) * 1984-11-21 1987-08-04 Olympus Optical Co., Ltd. Solid state image sensor having means to reset and clear static induction transistor photoelements
US4733286A (en) * 1983-12-28 1988-03-22 Olympus Optical Co., Ltd. Semiconductor photoelectric converting device
US4800172A (en) * 1987-02-09 1989-01-24 Kabushiki Kaisha Toshiba Manufacturing method for cascaded junction field effect transistor
US4823173A (en) * 1986-01-07 1989-04-18 Harris Corporation High voltage lateral MOS structure with depleted top gate region
US4868620A (en) * 1988-07-14 1989-09-19 Pacific Bell High-voltage pull-up device
US4942440A (en) * 1982-10-25 1990-07-17 General Electric Company High voltage semiconductor devices with reduced on-resistance
US4945392A (en) * 1987-04-28 1990-07-31 Olympus Optical Co., Ltd. Static induction transistor and manufacturing method of the same
EP0623951A1 (en) * 1993-01-25 1994-11-09 Telefonaktiebolaget Lm Ericsson A semiconductor device in a thin active layer with high breakdown voltage
EP0623949A1 (en) * 1993-01-25 1994-11-09 Telefonaktiebolaget Lm Ericsson A dielectrically isolated semiconductor device and a method for its manufacture
US5488241A (en) * 1993-07-22 1996-01-30 U.S. Philips Corporation Integrated device combining a bipolar transistor and a field effect transistor
US5861657A (en) * 1996-01-18 1999-01-19 International Rectifier Corporation Graded concentration epitaxial substrate for semiconductor device having resurf diffusion
US6278143B1 (en) * 1997-09-02 2001-08-21 Sony Corporation Semiconductor device with bipolar and J-FET transistors
US20020060341A1 (en) * 2000-11-21 2002-05-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20030168704A1 (en) * 2001-06-14 2003-09-11 Shin Harada Lateral junction type field effect transistor
US20040238840A1 (en) * 2003-05-30 2004-12-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing it
US20060163675A1 (en) * 2005-01-19 2006-07-27 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20070262793A1 (en) * 2006-05-11 2007-11-15 Ashok Kumar Kapoor Circuit configurations having four terminal JFET devices
US20080099796A1 (en) * 2006-11-01 2008-05-01 Vora Madhukar B Device with patterned semiconductor electrode structure and method of manufacture
US20080237657A1 (en) * 2007-03-26 2008-10-02 Dsm Solution, Inc. Signaling circuit and method for integrated circuit devices and systems
US20080265936A1 (en) * 2007-04-27 2008-10-30 Dsm Solutions, Inc. Integrated circuit switching device, structure and method of manufacture
US20080273398A1 (en) * 2007-05-01 2008-11-06 Dsm Solutions, Inc. Semiconductor device storage cell structure, method of operation, and method of manufacture
US20080272414A1 (en) * 2007-05-01 2008-11-06 Dsm Solutions, Inc. Image sensing cell, device, method of operation, and method of manufacture
US20090033361A1 (en) * 2007-08-03 2009-02-05 Dsm Solutions, Inc. Switching circuits and methods for programmable logic devices
US20090168508A1 (en) * 2007-12-31 2009-07-02 Dsm Solutions, Inc. Static random access memory having cells with junction field effect and bipolar junction transistors
US20090295427A1 (en) * 2008-06-02 2009-12-03 Dsm Solutions, Inc. Programmable switch circuit and method, method of manufacture, and devices and systems including the same
US20100090259A1 (en) * 2006-12-18 2010-04-15 Sumitomo Electric Industries, Ltd. Lateral junction field-effect transistor
US20130056801A1 (en) * 2010-05-17 2013-03-07 Panasonic Corporation Junction field effect transistor and analog circuit
JP2016167613A (ja) * 2007-03-28 2016-09-15 アドバンスト・アナロジック・テクノロジーズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ａｎａｌｏｇｉｃ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 絶縁分離された集積回路装置
CN109728100A (zh) * 2017-10-30 2019-05-07 亚德诺半导体无限责任公司 低栅极电流结型场效应晶体管器件架构
CN114156345A (zh) * 2020-09-08 2022-03-08 新唐科技股份有限公司 接面场效应晶体管

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8400612A (nl) * 1984-02-28 1985-09-16 Cordis Europ Chemisch gevoelige fet-component.
EP0167813A1 (en) * 1984-06-08 1986-01-15 Eaton Corporation Multi-channel power JFET
US4633281A (en) * 1984-06-08 1986-12-30 Eaton Corporation Dual stack power JFET with buried field shaping depletion regions
US4670764A (en) * 1984-06-08 1987-06-02 Eaton Corporation Multi-channel power JFET with buried field shaping regions
US4635084A (en) * 1984-06-08 1987-01-06 Eaton Corporation Split row power JFET
EP0167810A1 (en) * 1984-06-08 1986-01-15 Eaton Corporation Power JFET with plural lateral pinching
US7026669B2 (en) * 2004-06-03 2006-04-11 Ranbir Singh Lateral channel transistor
JP5168773B2 (ja) * 2005-11-14 2013-03-27 住友電気工業株式会社 横型接合型電界効果トランジスタ
JP2009043923A (ja) * 2007-08-08 2009-02-26 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066917A (en) * 1976-05-03 1978-01-03 National Semiconductor Corporation Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic
JPS5367368A (en) * 1976-11-29 1978-06-15 Sony Corp Semiconductor device
US4143392A (en) * 1977-08-30 1979-03-06 Signetics Corporation Composite jfet-bipolar structure
US4185291A (en) * 1977-06-30 1980-01-22 Matsushita Electric Industrial Co., Ltd. Junction-type field effect transistor and method of making the same
JPS55153378A (en) * 1979-05-18 1980-11-29 Matsushita Electronics Corp Field effect transistor
US4292642A (en) * 1978-01-18 1981-09-29 U.S. Philips Corporation Semiconductor device
US4300150A (en) * 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
US4314267A (en) * 1978-06-13 1982-02-02 Ibm Corporation Dense high performance JFET compatible with NPN transistor formation and merged BIFET
US4374389A (en) * 1978-06-06 1983-02-15 General Electric Company High breakdown voltage semiconductor device
US4379726A (en) * 1979-05-17 1983-04-12 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5123432B2 (en, 2012) * 1971-08-26 1976-07-16
NL184552C (nl) * 1978-07-24 1989-08-16 Philips Nv Halfgeleiderinrichting voor hoge spanningen.

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066917A (en) * 1976-05-03 1978-01-03 National Semiconductor Corporation Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic
JPS5367368A (en) * 1976-11-29 1978-06-15 Sony Corp Semiconductor device
US4185291A (en) * 1977-06-30 1980-01-22 Matsushita Electric Industrial Co., Ltd. Junction-type field effect transistor and method of making the same
US4143392A (en) * 1977-08-30 1979-03-06 Signetics Corporation Composite jfet-bipolar structure
US4292642A (en) * 1978-01-18 1981-09-29 U.S. Philips Corporation Semiconductor device
US4374389A (en) * 1978-06-06 1983-02-15 General Electric Company High breakdown voltage semiconductor device
US4314267A (en) * 1978-06-13 1982-02-02 Ibm Corporation Dense high performance JFET compatible with NPN transistor formation and merged BIFET
US4379726A (en) * 1979-05-17 1983-04-12 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition
JPS55153378A (en) * 1979-05-18 1980-11-29 Matsushita Electronics Corp Field effect transistor
US4300150A (en) * 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEDM High Voltage Thin Layer Devices (Resurf Devices) Appels et al. 1979, pp. 238 241. *
IEDM"High Voltage Thin Layer Devices (Resurf Devices)" Appels et al. 1979, pp. 238-241.

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US4733286A (en) * 1983-12-28 1988-03-22 Olympus Optical Co., Ltd. Semiconductor photoelectric converting device
US4684992A (en) * 1984-11-21 1987-08-04 Olympus Optical Co., Ltd. Solid state image sensor having means to reset and clear static induction transistor photoelements
US4823173A (en) * 1986-01-07 1989-04-18 Harris Corporation High voltage lateral MOS structure with depleted top gate region
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US4945392A (en) * 1987-04-28 1990-07-31 Olympus Optical Co., Ltd. Static induction transistor and manufacturing method of the same
US4868620A (en) * 1988-07-14 1989-09-19 Pacific Bell High-voltage pull-up device
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US5659190A (en) * 1993-01-25 1997-08-19 Telefonaktiebolaget Lm Ericsson Semiconductor device in a thin active layer with high breakdown voltage
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US5488241A (en) * 1993-07-22 1996-01-30 U.S. Philips Corporation Integrated device combining a bipolar transistor and a field effect transistor
US5861657A (en) * 1996-01-18 1999-01-19 International Rectifier Corporation Graded concentration epitaxial substrate for semiconductor device having resurf diffusion
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US20040238840A1 (en) * 2003-05-30 2004-12-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing it
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US20100090259A1 (en) * 2006-12-18 2010-04-15 Sumitomo Electric Industries, Ltd. Lateral junction field-effect transistor
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EP0083815A2 (en) 1983-07-20
CA1193757A (en) 1985-09-17
EP0083815A3 (en) 1985-04-03
JPS58116776A (ja) 1983-07-12
DE3277159D1 (en) 1987-10-08
JPH0357614B2 (en, 2012) 1991-09-02

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