US4447823A - SOS p--n Junction device with a thick oxide wiring insulation layer - Google Patents

SOS p--n Junction device with a thick oxide wiring insulation layer Download PDF

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Publication number
US4447823A
US4447823A US06/240,850 US24085081A US4447823A US 4447823 A US4447823 A US 4447823A US 24085081 A US24085081 A US 24085081A US 4447823 A US4447823 A US 4447823A
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semiconductor region
region
silicon layer
semiconductor
insulation
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US06/240,850
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Kenji Maeguchi
Hiroyuki Tango
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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Assigned to TOKYO SHIBAURA DENKI KABUSHIKI KAISHA reassignment TOKYO SHIBAURA DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MAEGUCHI KENJI, TANGO HIROYUKI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Definitions

  • the present invention relates to a semiconductor device having a silicon semiconductor structure formed on an insulation substrate and a method for manufacturing the same.
  • FIG. 1 shows a circuit diagram of a memory cell of E/R type.
  • the memory cell includes enhancement type drive MOS transistors 2 and 4 whose sources are grounded, load resistors 6 and 8 connected respectively between a power supply terminal V D and drains of MOS transistors 2, 4, an enhancement type transfer MOS transistor 10, with one end of the current path of which is connected to the drain of MOS transistor 2 and to the gate of MOS transistor 4, and an enhancement type transfer MOS transistor 12, with one end of the current path of which is connected to the gate of MOS transistor 2 and to the drain of MOS transistor 4.
  • the other ends of the current paths of MOS transistors 10 and 12 are connected to bit lines BL1 and BL2, respectively while their gates are both connected to a word line WL.
  • Load resistors 6 and 8 usually employed in the E/R type memory cell are formed from polycrystalline silicon so as to have high resistance values ranging from 1 M ⁇ to 100 m ⁇ .
  • resistance elements having such high resistance values are made of polycrystalline silicon, some problems are caused in that the resistance value of such resistance elements varies depending on the crystallographic property of the polycrystalline silicon (such as the radius of crystal particles) and depending on the difference of growth condition.
  • the formation of ohmic contact between high resistance polycrystalline silicon regions and conductive regions is difficult. Ohmic contact can be attained by making high the impurity concentration in a region adjacent to contacted areas.
  • impurities in the high impurity concentration region abnormally diffuse (along the boundaries of the crystal particles, for example) into a low impurity concentration region, thus causing the resistance value of the high resistance region to be lowered.
  • diodes 14 and 16 are used as load elements, as shown in FIG. 2, instead of load resistors 6 and 8.
  • load resistors 6 and 8 In order to set the reverse resistance value of diodes 14 and 16 to a several tens M ⁇ or more, it is necessary that the reverse current density of these diodes be set over several nA/ ⁇ m. However, it is difficult to gain such property from these diodes using the usual silicon substrate.
  • diodes formed using a silicon substrate need a larger area as compared with load resistors formed of polycrystalline silicon.
  • An object of the present invention is to provide a semiconductor device having pn junction regions whose electric properties render these regions suitable for use as load elements in the memory cell, and a method of manufacturing such a semiconductor device.
  • a semiconductor device comprising an insulation body, a silicon layer formed on the insulation body, a first semiconductor region of one conductivity type formed in part of a silicon layer extending from the surface of the silicon layer to the insulation body, and a second semiconductor region of conductivity type opposite to that of the first semiconductor region, the second semiconductor region being formed in a region adjacent to the first semiconductor region and cooperating with the first semiconductor region to form a pn junction element.
  • the pn junction element of this semiconductor device includes p-type and n-type regions formed on the insulation layer so that the p-type and n-type regions may be formed with a bad crystallinity, thus enabling reverse current to be made large.
  • the insulation layer is formed thick in the surface area of one of the p-type and n-type regions which form the pn junction element, thus making it possible to form a wiring layer on the insulation layer and to enhance the integration density of elements.
  • FIGS. 1 and 2 are circuit diagrams showing conventional memory cells
  • FIGS. 3A through 3F show a process of making a semiconductor device according to one embodiment of this invention which includes a pn junction element which can be used in the memory cell shown in FIG. 2;
  • FIG. 4 shows the electrical property of the pn junction element shown in FIG. 3F;
  • FIG. 5 is a modification of the semiconductor structure shown in FIG. 3B.
  • FIGS. 6 and 7 show modifications of the semiconductor structure shown in FIG. 3E.
  • FIGS. 3A through 3F show a process of making a semiconductor device which includes a pn junction element which is effectively used as a diode 14 or 16 for the memory cell shown in FIG. 2.
  • silicon is deposited on the surface of an insulating or sapphire substrate 22 to form a p-type silicon layer 20 whose thickness is about 0.8 ⁇ m.
  • a silicon dioxide (SiO 2 ) film 24 having a thickness of about 1,000 ⁇ is formed on the surface of the silicon layer 20 and a silicon nitride (Si 3 N 4 ) film 26 having a thickness of about 1,000 ⁇ is further formed on the surface of SiO 2 film 24.
  • SiO 2 and Si 3 N 4 films 24 and 26 are then selectively removed to leave a predetermined element region.
  • the silicon layer 20 not present under the element region is etched to a depth of about 4,000 ⁇ (or to have a thickness half the original one).
  • SiO 2 and Si 3 N 4 films 24 and 26 are further selectively etched to form a hole or gap 28 dividing the respective SiO 2 and Si 3 N 4 films 24 and 26 into two portions.
  • p-type impurity such as boron, for example, is injected through the hole 28 into the silicon layer 20 in a concentration of 5 ⁇ 10 11 atoms/cm 2 using ion-injection technique and an injection voltage of 50 KeV.
  • the exposed surface of the semiconductor substrate thus formed is wet-oxidized at a temperature of 1,000° C. to form oxide layers 30, 32 and 34 as shown in FIG. 3D. This oxidizing step is continued until oxide layers 30 and 32 reach the sapphire substrate 22.
  • the p-type silicon layer 20 in the element region is therefore separated from other regions by these SiO 2 layers 30 and 32.
  • the SiO 2 layer 34 is so formed that the distance between the under surface of the layer 34 and the upper surface of the insulation body 22 may be made about 4,000 ⁇ .
  • Boron impurity ion-injected into the silicon layer 20 during the preceding step is annealed in the oxidizing step to form a p-type region 35 under the oxide layer 34, and the p-type region 35 cooperates with the SiO 2 layer 34 to divide the silicon layer 20 into two regions 20-1 and 20-2.
  • SiO 2 and Si 3 N 4 films 24 and 26 are removed by etching after the oxidizing step.
  • a gate region 36 including the SiO 2 film of 1,000 ⁇ and a polycrystalline silicon layer formed on the SiO 2 film is formed on part of the surface of silicon layer 20-1 while a wiring layer 38 of polycrystalline silicon is formed on the SiO 2 film 34.
  • a phosphosilicate glass (PSG) layer (not shown) is then formed on the surface of thus formed semiconductor structure and phosphorus in the glass layer is diffused into the p-type silicon layer 20 at a temperature of about 1,000° C. The PSG layer is then removed by etching.
  • PSG phosphosilicate glass
  • n + -type regions 40 and 42 which serve as source and drain of a MOS transistor are formed in the silicon layer 20-1, and the silicon layer 20-2 is transformed to an n + -type region 44 which cooperates with the p-type region 35 to form a pn junction element.
  • SiO 2 layer 46 and PSG layer 48 are successively deposited, as shown in FIG. 3F, on SiO 2 layers 30, 32, 34 and gate region 36 by the CVD method. Thereafter, SiO 2 layer 46 and PSG layer 48 are selectively removed by etching to partially expose surfaces of n + -type regions 40, 42 and 44. Aluminum is then vapor-deposited on the exposed portions of n + -type regions 40, 42 and 44, and PSG layer 48, and an aluminum layer thus formed is selectively removed by etching to form electrode patterns 50, 52 and 54 relative to the n + -type regions 40, 42 and 44.
  • the pn junction element capable of being used as the diode 14 or 16 for the memory shown in FIG. 2 is formed of p-type region 35 and n + -type region 44.
  • This pn junction element is formed in this case to have a width of 5 ⁇ m and a thickness of 4,000 ⁇ , for example.
  • FIG. 4 shows voltage and current characteristics of pn junction device thus obtained.
  • reverse current IR of 5 ⁇ 10 -9 A flows through the diode when a reverse voltage VR of 5 V is applied to this diode.
  • the diode having these IR-VR characteristics can be effectively used as the diode 14 or 16 in the memory cell shown in FIG. 2.
  • forward current IF exponentially increases in accordance with a forward voltage VF of higher than 0.5 V, showing the usual diode forward characteristic.
  • pn junction device formed on the insulating substrate such as of silicon-on-sapphire (SOS) type
  • SOS silicon-on-sapphire
  • the SiO 2 layer 34 can be formed thick enough on the p-type layer 35 enabling the wiring layer 38 to be formed on the SiO 2 layer 34 enhancing the integration density of the elements.
  • the present invention has been described with reference to one embodiment, it should be understood that the present invention is not limited to that one embodiment.
  • the silicon layer 20 not present under the element region is removed by etching to the thickness of 4,000 ⁇ in the embodiment, but an island region 21 of silicon may be formed, as shown in FIG. 5, by completely removing that part of the silicon layer 20 which is not present in the element region.
  • the same steps as those used in the aforementioned embodiment may be carried out to manufacture a semiconductor device which has the same effect as that of the semiconductor device explained with reference to FIGS. 3A to 3F.
  • the p-type region 35 is formed adjacent to the n + -type region 42 in the embodiment, as shown in FIG. 3E, by doping part of silicon layer 20 with boron using the ion injection technique, but a p + -type region 56, which serves as an electrode region, may be formed, as shown in FIG. 6, in the n + -type region 42 adjacent to the p-type region 35 using the usual CMOS process.
  • Boron is doped by the ion injection method to form the p-type region 35 in the above-described embodiment, but boron and phosphorus may be doped instead by the ion injection method into their corresponding regions, as shown in FIG.
  • a p-type region 58 which cooperates with the n + -type region 44 to form the pn junction element, as well as an n-type region 60 between the p-type region 58 and the n + -type region 42.
  • the regions 44 and 56 are formed at high impurity concentration, but they may be formed of n-type and p-type regions, respectively.
  • the p - -type silicon layer 20 is used in the embodiment, but an n - -type silicon layer may be used instead with conductivity types of other regions reversed, thus enabling the same effect as that attained by the embodiment to be achieved.
  • Polycrystalline silicon is used in the embodiment to form gate electrode and wiring layer, but high-melting-poing metal such as molybdenum and tungsten may be used instead. It may be silicide such as molybdenum silicide, tungsten silicide, titanic silicide and tantalic silicide, or aluminum.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
US06/240,850 1980-03-12 1981-03-05 SOS p--n Junction device with a thick oxide wiring insulation layer Expired - Lifetime US4447823A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP55-31291 1980-03-12
JP3129180A JPS56126936A (en) 1980-03-12 1980-03-12 Semiconductor device and production thereof

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654959A (en) * 1981-07-15 1987-04-07 Sharp Kabushiki Kaisha Method for the manufacture of thin film transistors
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
US4735917A (en) * 1986-04-28 1988-04-05 General Electric Company Silicon-on-sapphire integrated circuits
US4751554A (en) * 1985-09-27 1988-06-14 Rca Corporation Silicon-on-sapphire integrated circuit and method of making the same
US4755481A (en) * 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
US4897698A (en) * 1984-10-31 1990-01-30 Texas Instruments Incorporated Horizontal structure thin film transistor
US4954871A (en) * 1981-06-26 1990-09-04 Yoshihisa Mizutani Semiconductor device with composite electrode
US4989061A (en) * 1986-09-05 1991-01-29 General Electric Company Radiation hard memory cell structure with drain shielding
US5019525A (en) * 1987-08-18 1991-05-28 Texas Instruments Incorporated Method for forming a horizontal self-aligned transistor
WO1997024765A1 (en) * 1995-12-29 1997-07-10 Intel Corporation A method and apparatus for fast self-destruction of a cmos integrated circuit
US5886385A (en) * 1996-08-22 1999-03-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6225666B1 (en) * 1999-10-29 2001-05-01 National Semiconductor Corporation Low stress active area silicon island structure with a non-rectangular cross-section profile and method for its formation
US6794717B2 (en) * 2001-02-13 2004-09-21 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20050253148A1 (en) * 1999-01-11 2005-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

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US4087902A (en) * 1976-06-23 1978-05-09 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Field effect transistor and method of construction thereof
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US4395726A (en) * 1979-03-30 1983-07-26 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device of silicon on sapphire structure having FETs with different thickness polycrystalline silicon films

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JPS5327278A (en) * 1976-08-27 1978-03-14 Hitachi Ltd Device for energizing electric discharge lamp
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JPS54130883A (en) * 1978-04-01 1979-10-11 Agency Of Ind Science & Technol Production of semiconductor device
US4320312A (en) * 1978-10-02 1982-03-16 Hewlett-Packard Company Smaller memory cells and logic circuits
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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954871A (en) * 1981-06-26 1990-09-04 Yoshihisa Mizutani Semiconductor device with composite electrode
US4654959A (en) * 1981-07-15 1987-04-07 Sharp Kabushiki Kaisha Method for the manufacture of thin film transistors
US4897698A (en) * 1984-10-31 1990-01-30 Texas Instruments Incorporated Horizontal structure thin film transistor
US4751554A (en) * 1985-09-27 1988-06-14 Rca Corporation Silicon-on-sapphire integrated circuit and method of making the same
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
US4735917A (en) * 1986-04-28 1988-04-05 General Electric Company Silicon-on-sapphire integrated circuits
US4755481A (en) * 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
US4989061A (en) * 1986-09-05 1991-01-29 General Electric Company Radiation hard memory cell structure with drain shielding
US5019525A (en) * 1987-08-18 1991-05-28 Texas Instruments Incorporated Method for forming a horizontal self-aligned transistor
WO1997024765A1 (en) * 1995-12-29 1997-07-10 Intel Corporation A method and apparatus for fast self-destruction of a cmos integrated circuit
US5736777A (en) * 1995-12-29 1998-04-07 Intel Corporation Method and apparatus for fast self-destruction of a CMOS integrated circuit
US5886385A (en) * 1996-08-22 1999-03-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US20050253148A1 (en) * 1999-01-11 2005-11-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7473968B2 (en) * 1999-01-11 2009-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including a thin film transistor and a storage capacitor
US6225666B1 (en) * 1999-10-29 2001-05-01 National Semiconductor Corporation Low stress active area silicon island structure with a non-rectangular cross-section profile and method for its formation
US6794717B2 (en) * 2001-02-13 2004-09-21 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20040207017A1 (en) * 2001-02-13 2004-10-21 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US7256463B2 (en) 2001-02-13 2007-08-14 Renesas Technology Corp. Semiconductor device having SOI structure including a load resistor of an sram memory cell
US20080017924A1 (en) * 2001-02-13 2008-01-24 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
DE3109074A1 (de) 1982-02-25
JPS56126936A (en) 1981-10-05
FR2478376A1 (fr) 1981-09-18
FR2478376B1 (ro) 1983-12-23
DE3109074C2 (ro) 1989-04-06

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