US4429388A - Field programmable device with internal dynamic test circuit - Google Patents

Field programmable device with internal dynamic test circuit Download PDF

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US4429388A
US4429388A US06/214,210 US21421080A US4429388A US 4429388 A US4429388 A US 4429388A US 21421080 A US21421080 A US 21421080A US 4429388 A US4429388 A US 4429388A
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test
rows
bit
ratio
row
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Toshitaka Fukushima
Kazumi Koyama
Kouji Ueno
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Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

Definitions

  • the present invention relates generally to field programmable devices, and more particularly to a field programmable device, such as a ROM (Read Only Memory), PROM (Programmable Read Only Memory), FPLA (Field Programmable Logic Array) and the like, capable of being functionally tested before information is written in the device.
  • a field programmable device such as a ROM (Read Only Memory), PROM (Programmable Read Only Memory), FPLA (Field Programmable Logic Array) and the like, capable of being functionally tested before information is written in the device.
  • a field programmable device such as a PROM or ROM
  • PROM programmable read-only memory
  • ROM read-only memory
  • An example of a conventional memory device of the above type comprises X and Y address inverters a X-decoder driver, a Y-decoder, a memory cell part, a multiplexer, and an output circuit.
  • X and Y address inverters a X-decoder driver, a Y-decoder, a memory cell part, a multiplexer, and an output circuit.
  • the data read-out of the memory cells is all the same. Accordingly, it is impossible to know whether the cells are in normal or abnormal states. Even assuming that there are abnormalities, it is not possible to know where the abnormalities exist.
  • the word line capacity is affected by the manufacturing process, and thus computation of the word line capacity is difficult, and is preferably obtained by actual measurements.
  • the write-in ratio of both the test bit row and of the test word is 50%, hence capable of being subjected to a speed check of a 50% write-in ratio, but incapable of performing speed checks in the remaining parts. Therefore, when the user performs a 100% write-in (this is done quite often), the access time can become much higher than that of the nominal value.
  • a general object of the present invention is to provide a novel and useful field programmable device in which the above described problems have been overcome.
  • Another and more specific object of the present invention is to provide a field programmable device in which a plurality of test bit rows are provided along bit lines and/or a plurality of test word rows are provided along word lines in a memory cell part, so that at least one of the above rows has a differing write-in ratio from that of the other rows. According, with the present invention it is possible to completely test the DC and AC characteristics of the field programmable device before the shipment of the device.
  • FIG. 1 is a block diagram of the construction of a PROM device embodying the present invention
  • FIG. 2 is an equivalent circuit diagram of a pn-junction type memory cell part having test bit and test word rows;
  • FIGS. 3A through 3C are respectively, equivalent circuit diagram and cross-sectional diagrams of a memory cell part in the unprogrammed state
  • FIG. 4 is a diagram of a memory cell part, showing the programming state of a memory cell part according to FIG. 2;
  • FIGS. 5 and 6 are circuit diagrams showing the construction of the address inverters, decoder driver, and memory cell part of the PROM device of FIG. 1;
  • FIG. 7 is a diagram showing the information to be written into the test bits for performing the DC test.
  • FIGS. 8A, 8B, 9A, and 9B are diagrams illustrating the actual test bit arrangement for performing the DC test
  • FIG. 10 is a circuit diagram of a multiplexer test circuit
  • FIGS. 11A, 11B, and 12A, 12B are, respectively, simplified cross-sectional diagrams of a cell and its equivalent circuit diagrams
  • FIG. 13 illustrates an embodiment of a memory device of the present invention
  • FIGS. 14A, 14B, 15A, 15B, 16A, and 16B are, respectively, equivalent circuit diagrams and cross-sectional diagrams showing different types of memory cells.
  • FIG. 1 is an example of the construction of a PROM device of the previously proposed system, which comprises X and Y address inverters 10 and 12, an X-decoder driver 11, a Y-decoder 13, a memory cell part 14, a multiplexer 15, an output circuit 16, and test bit and test word groups 17 and 18.
  • FIG. 2 is an equivalent circuit diagram of a memory cell part of the above proposed system.
  • two test bit rows TB 1 and TB 2 are provided parallel to lines b 1 through b 4
  • two test word rows TW 1 and TW 2 are provided parallel to lines l 1 through l 4 .
  • the above code pattern is obtained by setting address signal bit A 0 of the address signal to a logic high level "1", then forming a code beginning with A 0 A 0 , concatenated with an inverted code A 0 A 0 yielding a code A 0 A 0 A 0 A 0 , which is then concatenated with an inverted code A 0 A 0 A 0 A 0 yielding a code A 0 A 0 A 0 A 0 A 0 A 0 and so on.
  • the inversion of the code patterns written into the first test bit row TB 1 is written into the second test bit row TB 2 .
  • predetermined code patterns are written into both the test word rows TW 1 and TW 2 . Therefore, the states of corresponding test bit positions of the test bit rows TB 1 and TB 2 are complementary. The same is true for the test word rows TW 1 and TW 2 .
  • Transistors TR 1 are transistors to the output stages of a decoder driver 11, and are connected to corresponding word lines l 1 , l 2 , . . . . Transistors TR 2 represent memory cells not yet written into.
  • Diodes D 1 represent diodes which short-circuit the emitter and base junctions, to show memory cells written-in with information "1" indicated by a logic high level.
  • FIGS. 3A through 3C are an equivalent circuit diagram of the memory cell part not yet written into, the respective cross-sectional diagrams of the memory cell part out, respectively along dotted lines I and II of FIG. 3A.
  • an n-type semiconductor layer 20, which is to be the collector is epitaxially grown on a p - -type silicon semiconductor base 19.
  • a plurality of p + -type regions 21 that are to be the bases, are formed in the n-type semiconductor layer 20, and n + -type regions 22 are formed in the p + -type regions 21.
  • the word lines l 1 and l 2 formed by the n + -type region 23 are embedded below the n-type layer 20, while the bit lines b 1 through b 3 are constructed of metal wirings 24 formed on the surface of the bit lines b 1 through b 3 .
  • Layer 25 is an insulating layer, and p + -type isolation regions 26 separate each of the word lines.
  • FIG. 4 illustrates the memory cell part shown in FIG. 2.
  • none of the memory cells of the memory cell part 14 have information written therein, but information is written selectively in the test bits and the test words.
  • the cells in which information is written, are shown by the cross-hatched squares, the remaining cells are shown by unmarked squares.
  • the memory cells are selected by Y-address inverter 12, Y-decoder 13, and multiplexer 15 along the bit line, and by X-address inverter 10, X-decoder driver 11 along the word line.
  • Y-address inverter 12 Y-decoder 13
  • multiplexer 15 Y-decoder 13
  • X-address inverter 10 X-decoder driver 11 along the word line.
  • FIGS. 5 and 6 which showing the outlines of the word line side.
  • address inverter 10 comprises a plurality of rows each with two inverters connected in series, namely, I 1 and I 2 , I 3 and I 4 , and so on.
  • Decoder driver 11 comprises a plurality of parallel connected NAND-gates, namely, NG 1 , NG 2 , and so on.
  • the address signal bits A 0 , A 1 , A 2 . . . of the address signal are respectively and correspondingly applied to the input terminals of the plurality of two series connected inverters. Accordingly, the inverted and non-inverted signals, namely, A 0 , A 0 , A 1 , A 1 , . . . are generated.
  • a decoder driver for address signal bits A 0 and A 1 is shown in this example by which one of four word lines is selected by the two bits. However, if the address signal has five address signal bits, namely A 0 through A 4 , then it is possible to select one from 2 5 , or 32 word lines. But, ten inverters, I 1 through I 10 , and 32 NAND-gates are required.
  • FIG. 6 shows a word line side selection system, and a portion of the memory cell part 14.
  • memory cells M 11 , M 12 , . . . M 21 , M 22 , . . . are respectively located at the intersection points of the word lines l 1 , l 2 , . . . and bit lines b 1 , b 2 , . . . .
  • address signal bit A 0 of the address signal is shown.
  • the memory cells of a PROM are constructed of fuses or p-n junctions. But, in this example, the latter is used and the writing of information is performed by destroying the base emitter junction of an npn-transistor.
  • the write-in of information is performed by the user, and is not performed before shipment. Therefore, because of the write-in of information is not performed, current does not flow toward the NAND-gate through the bit and word lines when the output of the NAND-gate is a logic low level. Accordingly, it is impossible to detect whether or not a word line has been selected or a defect such as a break in the wiring exists. Also, since a word line is selected only when the address inverters, decoder driver, and the wiring thereof, are normal, if a word line is not selected because of abnormalites, it is impossible to detect the location of the defect.
  • Test bits can be provided in the memory cell part to overcome the above problem. If the memory cells M 11 , M 12 , . . . of FIG. 6 are test bits inserted in the additional bit line of the memory cell part, and a code "1,0,1,0, . . . , is written into these test bits, then a current flows and the line l 1 is selected when address signal bit A 0 is "0", and a current flows and line l 2 is selected when address signal bit A 0 is "1". Therefore, inverter I 1 , NAND-gate NG 1 and the wiring thereof can be assumed to be normal.
  • Abnormalities are not detected in inverter I 2 and NAND-gate NG 2 , when both inverter I 2 and NAND-gate NG 2 are in the abnormal states. That is, in when the output of inverter I 2 constantly produces low-level output and the output of NAND-gate NG 2 is at a constant high-level, or when there is a break in the wiring. Abnormalities are not detected because no current flows in either of these cases. Therefore it cannot be concluded from the above test alone that the inverter I 2 and NAND-gate NG 2 system is in a normal state.
  • cases (1) through (7) in Table 1 the only normal state is case (1), and all other cases (2) through (7) are abnormal states (cases (2) and (3) are partially normal and partially abnormal, and thus abnormal when considered as a whole).
  • the object is to detect the above abnormal cases by use of the test bits, but differences occur according to the contents stored in the test bits, as shown in Table 2.
  • FIG. 7 shows that test bits b 11 and b 21 , corresponding to the above memory cells M 11 and M 21 , are respectively "0" and “1” as described above, and that succeeding test bits b 31 and b 41 should contain the inverse code of that formed by the test bits b 11 and b 21 , namely, "1" and "0", respectively.
  • Succeeding test bits b 51 , b 61 , b 71 , and b 81 should contain the inverse code of that formed by the test bits b 11 , b 21 , b 31 , and b 41 , namely, "1,0,0,1".
  • the rest of the code can be obtained as shown in FIG. 7, and the same code pattern should be inserted into the test word TW 1 to obtain the above described valid test results.
  • the address inverters and the decoder driver can be tested for their normal and abnormal state.
  • the write-in of information is performed by selecting a word line, and applying a large voltage to the bit line so that a large current of about 200 mA flows through the bit line, memory cell, word line, and NAND-gate.
  • this large current cannot be passed through to the NAND-gates connected to the OFF state test bits, and the current absorbing capacity of these NAND-gates cannot be checked.
  • the object of the invention disclosed in the U.S. Pat. No. 4,312,067 issued to Shirosaka is to compensate for the above described problems.
  • an additional bit line and word line are provided and a test bit TB 2 and test word TW 2 are connected to these additional lines.
  • the information written-in these test bit cells are the inverse of those written-in the first test bit line and first test word line, namely, "1,0,0,1,0, . . . ".
  • FIGS. 8A and 8B show the above described test bit arrangement for a two-bit address signal and four word lines.
  • FIG. 8A shows the case where the code "0,1,1,0” is stored in the test bits
  • FIG. 8B shows a case where the code "0,1,0,1,” is stored in the test bits.
  • the test bits b 11 , b 21 , b 31 , and b 41 selected by the two-bit address signals "00", "01", 10", and "11” are written-in with the information "0,1,1,0", respectively, but the geographical arrangement of the bits in the memory cell part in the case shown by FIG. 8B is "0,1,0,1". Accordingly, with the arrangement shown in FIG. 8B, a different result is obtained when a short-circuit exists in adjacent wires of the word line that when in the normal state, and the abnormality can be detected immediately.
  • FIGS. 9A and 9B respectively show test bit arrangements for a six-bit address signal and sixty-four memory cells.
  • FIG. 9A shows a test bit arrangement considering a counter-measure against short-circuits in the wiring, while the arrangement of FIG. 9B does not.
  • the cross-hatched squares (bits) indicate bits containing the information "1”
  • the unmarked squares (bits) indicate bits containing the information "0”.
  • the position of the test bits are arranged so that their addresses are arranged in an order S32, S0, S1, S33, S35, . . . .
  • FIG. 10 A detection circuit for detecting the defect in the multiplexer is shown in FIG. 10.
  • memory cell part 14 of FIG. 1 is divided into a plurality of memory cell groups.
  • Each memory cell group is selectively connected to output circuit 16 by use of multiplexer 15 connected between the output circuit 16 and the memory cell groups.
  • this multiplexer 15 must also be tested to determine whether or not it is operating normally.
  • a test word is provided which generates an output representing the output of each of the memory cell groups, and an output is obtained by switching over these outputs by a switching signal.
  • Output circuits of each of the memory cell groups are designated by g 1 through g 8
  • selection signals bits for selecting the AND-gates G 1 through G 8 are designated by A 6 through A 8 .
  • the output of one of the AND-gates is selected to be high ("1") by the selection signal formed by the three selection signal bits A 6 through A 8 .
  • the abnormalities can be checked by setting the test word to contain "0,1,1,0,1,0,0,1,", and considering a possibility of breaks in the wiring, it is desirable to set the arrangement of the test word row to contain "0,1,0,1, . . . ".
  • Normal or abnormal operating states can be determined in the above cases (1) through (7), a test of the current absorbing capability of the decoder driver, and a check for short-circuits in the wiring can be performed in the improved field programmable device described above practically a complete set of tests can be performed on the field programmable device in its manufacturing stage before its shipment. Moreover, the test word and the test bit are used in a similar manner, enabling DC tests on the output voltage and output short current, as well as AC tests. Therefore the write-in current absorption, multiplexer system, and output voltages can be tested for normal operation.
  • FIGS. 11A and 11B A memory cell having no information written-in, is shown by FIGS. 11A and 11B, where FIG. 11B is an equivalent circuit diagram of the memory cell shown in FIG. 11A.
  • FIGS. 12A and 12B A memory cell having information written-in, is shown by FIGS. 12A and 12B, where FIG. 12B is an equivalent circuit diagram of the memory cell shown in FIG. 12B.
  • the memory cell of FIG. 11A has a junction capacitance C 1 between the emitter E and base B when reverse-biased, and a junction capacitance C 2 between the base B and collector C when forward-biased. These capabilities, are connected in series.
  • FIGS. 11A A memory cell having information written-in, FIGS.
  • a pnp-type transistor is formed by the base B, collector C (the collector region n and the buried layer n + b), and the base plate 19.
  • a current flows through this pnp-type transistor upon selection, as can be clearly seen from the diagram of FIG. 12A.
  • the base current of pnp-type transistor is cut-off, and the pnp-type transistor accordingly is turned OFF.
  • a charge due to the current which had been flowing remains, and thus, until this charge dissipates, the word line voltage does not rise to the high ("1") level of non-selection.
  • Capacitance C 2 is much larger than the capacitance of a non-written cell which is approximately equal to the capacitance C 1 . Accordingly, the word line or bit line capacitance may become larger than that when test bits TB 1 and TB 2 or test words TW 1 and TW 2 having a 50% write-in ratio are selected. That is, in a pn-junction type PROM, the word line or bit line having a 100% write-in ratio has the highest capacitance, hence the heaviest load. Therefore, when the AC characteristic of the memory device including its internal peripheral circuits is not tested under such a condition before its shipment, the access time of the memory device under maximum load cannot be guaranteed.
  • FIG. 13 A sectional diagram of a memory cell part of an embodiment of a field programmable device of the present invention is shown in FIG. 13.
  • the embodiment shown in FIG. 13 differs from that shown in FIG. 4, in that, in FIG. 13, a third test word TW 3 having a write-in ratio of 100% has been added (the cross-hatched squares represent the written-in bits).
  • the test word TW 3 is, for example, formed by short-circuiting the emitter-base junctions of all memory cells in word line l 4 shown in FIG. 2, thus converting them into the equivalent of diodes D 1 .
  • FIG. 14A shows a more detailed equivalent circuit diagram of the above memory cell
  • FIG. 14B shows a cross-sectional diagram of the memory cell.
  • those parts that are the same as the corresponding parts in FIGS. 3A and 3B are designated by like reference numbers.
  • a pnp-type transistor transistor TR 3 of FIG. 14A
  • transistor TR 3 of FIG. 14A having the p - -type semiconductor substrate 19
  • a junction capacitance C 0 (capacitance C 0 is larger than the above described capacitance C 1 ) is formed between the n-type semiconductor layer 20 and the p - -type semiconductor substrate 19 in the reverse-biased state and this capacitance C 0 acts as a load after the conducting channel CH is formed.
  • the capacitance of the written-in cells is larger than that of the non-written cells, and the load seen from the peripheral circuit side differs according to the write-in ratio. Therefore, in the present embodiment, a test word line TW 3 having a maximum load is provided, to guarantee the AC characteristics or the access time of the field programmable device being shipped, by forcing the slowest access time when the test is performed with the additional test word TW 3 selected.
  • Test words TW 1 and TW 2 are also provided, of course, and thus the DC characteristics on the word line side is also fully guranteed. The same is true on the bit line side, but it is a repetitive description of the above, and is omitted.
  • the test cells for measuring the access time of the memory device can be provided on the test bit side, test word side, or on both the test word and test bit sides.
  • the code pattern written-in to the test word TW 3 does not necessarily have to be of a 100% write-in ratio, that is, some bits may be non-written cells. Furthermore, it is also possible to assume the slowest access time, by providing two rows of test bits or test words having different write-in ratios between 0% and 100%, and measuring their access time. In this case, one of the test bit ot test word rows for performing the DC test can be used as the above test bit and test word rows. Moreover, according to the type of memory device being used, it is necessary in some cases to set the code pattern of the test word TW 3 to a pattern in which the bits (cells) are all zeros, or close to all zeros.
  • FIGS. 15A and 15B show a ROM (or EAROM) having memory cells made out of amorphous semiconductor (chalcogenied glass).
  • the cells are in "1" states as in the pn-junction type, but in the case of a fuse type device, the memories must all contain the reverse of the above, namely "0s", as shown in FIGS. 16A and 16B.
  • FIGS. 15A and 16B those parts that are the same as the corresponding parts in FIGS. 3A and 3B are designated by like reference numerals, and their description are omitted.
  • a chalcogenied glass layer 27 and a metal electrode 28 are inserted between the metal electrode (bit line) 24 and the anode 21 of diode D 1 to provide a bias voltage at the electrodes 24 and 28.
  • the write-in is performed. Accordingly, this type of memory cell is the same as the pn-junction type cell.
  • the cell shown in FIGS. 16A and 16B performs the write-in by flowing an overcurrent to melt and break a fuse 29. This is the opposite mechanism than that of the above two examples, and comprises a maximum capacitance in the word line (or bit line) having 100% non-written cells and the capacitance is minimum for the 100% written-in word line (or bit line ).

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US06/214,210 1979-12-18 1980-12-08 Field programmable device with internal dynamic test circuit Expired - Lifetime US4429388A (en)

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JP16433379A JPS5693189A (en) 1979-12-18 1979-12-18 Field programable element
JP54-164333 1979-12-18

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US (1) US4429388A (enrdf_load_stackoverflow)
EP (1) EP0032015B1 (enrdf_load_stackoverflow)
JP (1) JPS5693189A (enrdf_load_stackoverflow)
CA (1) CA1177956A (enrdf_load_stackoverflow)
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506363A (en) * 1982-05-28 1985-03-19 Siemens Aktiengesellschaft Programmable logic array in ECL technology
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein
US5357471A (en) * 1992-03-20 1994-10-18 National Semiconductor Corporation Fault locator architecture and method for memories
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
WO1996015536A1 (en) * 1994-11-09 1996-05-23 Philips Electronics N.V. A method of testing a memory address decoder and a fault-tolerant memory address decoder
US5764654A (en) * 1984-08-07 1998-06-09 Fujitsu Limited Semiconductor integrated circuit device having a test circuit
US6111799A (en) * 1998-10-29 2000-08-29 Nec Corporation Semiconductor memory in which access to broken word line is inhibited
US6341091B1 (en) * 2000-11-06 2002-01-22 Texas Instruments Incorporated Method and system for testing a bit cell in a memory array
US6407953B1 (en) 2001-02-02 2002-06-18 Matrix Semiconductor, Inc. Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
WO2003003379A1 (en) * 2001-06-29 2003-01-09 Koninklijke Philips Electronics N.V. Non-volatile memory and accelerated test method for address decoder by added modified dummy memory cells
US6853598B2 (en) * 2001-08-30 2005-02-08 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198596A (ja) * 1983-04-22 1984-11-10 Hitachi Micro Comput Eng Ltd 検査回路
JPS61230700A (ja) * 1985-04-05 1986-10-14 Nec Corp プログラマブル・リ−ド・オンリ−・メモリ
JPS6258500A (ja) * 1985-09-09 1987-03-14 Fujitsu Ltd 半導体記憶装置の試験方法
JPS63276794A (ja) * 1987-05-07 1988-11-15 Mitsubishi Electric Corp 半導体記憶装置
JPS6425399A (en) * 1987-07-21 1989-01-27 Fujitsu Ltd Programmable device and its test method
US5428621A (en) * 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
FR2771840B1 (fr) * 1997-11-28 2003-06-27 Sgs Thomson Microelectronics Memoire rom testable en consommation statique

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3063636A (en) 1959-07-06 1962-11-13 Ibm Matrix arithmetic system with input and output error checking circuits
US3221310A (en) 1960-07-11 1965-11-30 Honeywell Inc Parity bit indicator
US3633016A (en) 1970-03-04 1972-01-04 Digital General Corp Apparatus and method for testing electrical systems having a plurality of terminals
US3944800A (en) 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
US3995215A (en) 1974-06-26 1976-11-30 International Business Machines Corporation Test technique for semiconductor memory array
US4176258A (en) 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips
US4253059A (en) 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit
US4312067A (en) 1978-12-23 1982-01-19 Tokyo Shibaura Denki Kabushiki Kaisha Function test evaluation apparatus for evaluating a function test of a logic circuit
US4320507A (en) 1978-11-25 1982-03-16 Fujitsu Limited Field programmable device having test provisions for fault detection

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3420991A (en) * 1965-04-29 1969-01-07 Rca Corp Error detection system
DE2966682D1 (en) * 1978-11-25 1984-03-22 Fujitsu Ltd Programmable memory device provided with test means

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3063636A (en) 1959-07-06 1962-11-13 Ibm Matrix arithmetic system with input and output error checking circuits
US3221310A (en) 1960-07-11 1965-11-30 Honeywell Inc Parity bit indicator
US3633016A (en) 1970-03-04 1972-01-04 Digital General Corp Apparatus and method for testing electrical systems having a plurality of terminals
US3995215A (en) 1974-06-26 1976-11-30 International Business Machines Corporation Test technique for semiconductor memory array
US3944800A (en) 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
US4176258A (en) 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips
US4320507A (en) 1978-11-25 1982-03-16 Fujitsu Limited Field programmable device having test provisions for fault detection
US4312067A (en) 1978-12-23 1982-01-19 Tokyo Shibaura Denki Kabushiki Kaisha Function test evaluation apparatus for evaluating a function test of a logic circuit
US4253059A (en) 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506363A (en) * 1982-05-28 1985-03-19 Siemens Aktiengesellschaft Programmable logic array in ECL technology
US5764654A (en) * 1984-08-07 1998-06-09 Fujitsu Limited Semiconductor integrated circuit device having a test circuit
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein
US5357471A (en) * 1992-03-20 1994-10-18 National Semiconductor Corporation Fault locator architecture and method for memories
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
WO1996015536A1 (en) * 1994-11-09 1996-05-23 Philips Electronics N.V. A method of testing a memory address decoder and a fault-tolerant memory address decoder
US6111799A (en) * 1998-10-29 2000-08-29 Nec Corporation Semiconductor memory in which access to broken word line is inhibited
US6341091B1 (en) * 2000-11-06 2002-01-22 Texas Instruments Incorporated Method and system for testing a bit cell in a memory array
US6407953B1 (en) 2001-02-02 2002-06-18 Matrix Semiconductor, Inc. Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
WO2003003379A1 (en) * 2001-06-29 2003-01-09 Koninklijke Philips Electronics N.V. Non-volatile memory and accelerated test method for address decoder by added modified dummy memory cells
US20040188716A1 (en) * 2001-06-29 2004-09-30 Steffen Gappisch Non-volatile memory and accelerated test method for address decoder by added modified dummy memory cells
US7664998B2 (en) * 2001-06-29 2010-02-16 Nxp B.V. Non-volatile memory and accelerated test method for address decoder by added modified dummy memory cells
US6853598B2 (en) * 2001-08-30 2005-02-08 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection
US20050078515A1 (en) * 2001-08-30 2005-04-14 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection
US6999363B2 (en) 2001-08-30 2006-02-14 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection
US20060083089A1 (en) * 2001-08-30 2006-04-20 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection
US7248515B2 (en) 2001-08-30 2007-07-24 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection

Also Published As

Publication number Publication date
JPS5693189A (en) 1981-07-28
IE55516B1 (en) 1990-10-10
EP0032015A2 (en) 1981-07-15
EP0032015B1 (en) 1990-02-28
IE802647L (en) 1981-06-18
EP0032015A3 (en) 1981-08-05
JPS6330720B2 (enrdf_load_stackoverflow) 1988-06-20
DE3072171D1 (de) 1990-04-05
CA1177956A (en) 1984-11-13

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