DE3072171D1 - Kundenprogrammierbare vorrichtung mit testbits. - Google Patents

Kundenprogrammierbare vorrichtung mit testbits.

Info

Publication number
DE3072171D1
DE3072171D1 DE8080304531T DE3072171T DE3072171D1 DE 3072171 D1 DE3072171 D1 DE 3072171D1 DE 8080304531 T DE8080304531 T DE 8080304531T DE 3072171 T DE3072171 T DE 3072171T DE 3072171 D1 DE3072171 D1 DE 3072171D1
Authority
DE
Germany
Prior art keywords
testbits
programmable device
custom programmable
custom
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8080304531T
Other languages
English (en)
Inventor
Toshitaka Fukushima
Kazumi Koyama
Kouji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=15791172&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3072171(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3072171D1 publication Critical patent/DE3072171D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
DE8080304531T 1979-12-18 1980-12-16 Kundenprogrammierbare vorrichtung mit testbits. Expired - Fee Related DE3072171D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16433379A JPS5693189A (en) 1979-12-18 1979-12-18 Field programable element

Publications (1)

Publication Number Publication Date
DE3072171D1 true DE3072171D1 (de) 1990-04-05

Family

ID=15791172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080304531T Expired - Fee Related DE3072171D1 (de) 1979-12-18 1980-12-16 Kundenprogrammierbare vorrichtung mit testbits.

Country Status (6)

Country Link
US (1) US4429388A (de)
EP (1) EP0032015B1 (de)
JP (1) JPS5693189A (de)
CA (1) CA1177956A (de)
DE (1) DE3072171D1 (de)
IE (1) IE55516B1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3220302C2 (de) * 1982-05-28 1984-03-15 Siemens AG, 1000 Berlin und 8000 München Programmierbare Logikanordnung in ECL-Technik
JPS59198596A (ja) * 1983-04-22 1984-11-10 Hitachi Micro Comput Eng Ltd 検査回路
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
JPS61230700A (ja) * 1985-04-05 1986-10-14 Nec Corp プログラマブル・リ−ド・オンリ−・メモリ
JPS6258500A (ja) * 1985-09-09 1987-03-14 Fujitsu Ltd 半導体記憶装置の試験方法
JPS63276794A (ja) * 1987-05-07 1988-11-15 Mitsubishi Electric Corp 半導体記憶装置
JPS6425399A (en) * 1987-07-21 1989-01-27 Fujitsu Ltd Programmable device and its test method
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein
US5357471A (en) * 1992-03-20 1994-10-18 National Semiconductor Corporation Fault locator architecture and method for memories
US5495486A (en) * 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
US5428621A (en) * 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
WO1996015536A1 (en) * 1994-11-09 1996-05-23 Philips Electronics N.V. A method of testing a memory address decoder and a fault-tolerant memory address decoder
FR2771840B1 (fr) * 1997-11-28 2003-06-27 Sgs Thomson Microelectronics Memoire rom testable en consommation statique
JP3248497B2 (ja) * 1998-10-29 2002-01-21 日本電気株式会社 半導体記憶装置
US6341091B1 (en) * 2000-11-06 2002-01-22 Texas Instruments Incorporated Method and system for testing a bit cell in a memory array
US6407953B1 (en) 2001-02-02 2002-06-18 Matrix Semiconductor, Inc. Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
DE60234446D1 (de) * 2001-06-29 2009-12-31 Nxp Bv Nichtflüchtiger speicher und beschleunigtes testverfahren für zugehörigen adressendekodierer durch zugefügte modifizierte dummy-speicherzellen
US6597609B2 (en) * 2001-08-30 2003-07-22 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3063636A (en) 1959-07-06 1962-11-13 Ibm Matrix arithmetic system with input and output error checking circuits
US3221310A (en) 1960-07-11 1965-11-30 Honeywell Inc Parity bit indicator
US3420991A (en) * 1965-04-29 1969-01-07 Rca Corp Error detection system
US3633016A (en) 1970-03-04 1972-01-04 Digital General Corp Apparatus and method for testing electrical systems having a plurality of terminals
US3995215A (en) 1974-06-26 1976-11-30 International Business Machines Corporation Test technique for semiconductor memory array
US3944800A (en) 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
US4176258A (en) 1978-05-01 1979-11-27 Intel Corporation Method and circuit for checking integrated circuit chips
JPS5914838B2 (ja) 1978-11-25 1984-04-06 富士通株式会社 フィ−ルドプログラマブル素子
DE2966682D1 (en) * 1978-11-25 1984-03-22 Fujitsu Ltd Programmable memory device provided with test means
JPS5585264A (en) 1978-12-23 1980-06-27 Toshiba Corp Function test evaluation device for integrated circuit
US4253059A (en) 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit

Also Published As

Publication number Publication date
IE802647L (en) 1981-06-18
EP0032015B1 (de) 1990-02-28
US4429388A (en) 1984-01-31
IE55516B1 (en) 1990-10-10
EP0032015A3 (en) 1981-08-05
JPS6330720B2 (de) 1988-06-20
EP0032015A2 (de) 1981-07-15
JPS5693189A (en) 1981-07-28
CA1177956A (en) 1984-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee