US4412240A - Semiconductor integrated circuit and wiring method - Google Patents

Semiconductor integrated circuit and wiring method Download PDF

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Publication number
US4412240A
US4412240A US06/198,131 US19813180A US4412240A US 4412240 A US4412240 A US 4412240A US 19813180 A US19813180 A US 19813180A US 4412240 A US4412240 A US 4412240A
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Prior art keywords
wiring
vertical
horizontal
interval
grid
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Expired - Lifetime
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US06/198,131
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English (en)
Inventor
Hideo Kikuchi
Shigenori Baba
Shoji Sato
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Definitions

  • the present invention relates to a semiconductor integrated circuit, and more particularly to a large scale integrated circuit and wiring method suited to automatic designing.
  • the density of an integrated circuit (IC) structure is increasing and resultingly layout of an IC can be made in a unit of a circuit (called a "cell") such as a NAND gate or flip-flop instead of a transistor, and wiring is carried out by the grid system where connection between cells can be established.
  • a cell such as a NAND gate or flip-flop instead of a transistor
  • the layout space is partitioned in the form of a grid with the dimensions larger than the minimum dimension for patterning the wiring material layer in fabrication of ICs, for example, by the vertical and horizontal lines having the interval of the wiring pitch dimensions (in actuality that interval multiplied by the reduction scale), and the wiring pattern is depicted on such vertical and horizontal lines.
  • the wiring pitch differs in accordance with the wiring layer location such as 1st or 2nd layers and the wiring material such as aluminium, polysilicon or diffusion layer.
  • the allowable minimum line interval is 10 ⁇ m; or in the case of polysilicon it is 10 ⁇ m, while that of the 2nd layer of aluminium is 15 ⁇ m.
  • the existing grid employs the rectangular mesh having a horizontal line interval of 10 ⁇ m and vertical line interval of 15 ⁇ m.
  • this grid allows drawing of the wiring pattern of the 1st layer (with the allowable minimum line interval) correctly only by depicting the lines indicating the wiring on the horizontal lines, and also allows drawing of the wiring pattern of the 2nd layer correctly only by depicting the lines indicating the wiring on the vertical lines.
  • a mask can be generated on the basis of this grid and wiring of the IC can be obtained through the photo process, etc.
  • the section paper forming a square mesh with equal horizontal and vertical line intervals has been used in order to depict the wiring pattern.
  • the lines indicating wirings were are drawn on the horizontal or vertical lines of this section paper or between the horizontal and vertical lines. Then, such drawing is reduced, for example, to the scale of 1/1000 (when the mesh has an interval of 1 mm, it is reduced up to 1 ⁇ m or 0.5 ⁇ m which almost corresponds to the minimum dimensions of the patterning) in order to obtain the mask.
  • this method using such section paper it is required to check if the interval between wiring patterns depicted is larger than the allowable minimum line interval or not, and this check is very troublesome when an IC has succeeded in achieving greater density.
  • the grid system is very convenient and the wiring interval always becomes broader than the allowable minimum line interval when a rule that the wiring should always be depicted on the grid (vertical, horizontal lines) is observed. Therefore, the line interval check is not required in the grid system.
  • the horizontal line is used for the 1st layer individually, while the vertical line is used for the 2nd layer (thereby the allowable minimum line interval of each layer can be reserved easily).
  • the cells 1 and 2 exist as shown in FIG.
  • the vertical lines when it is attempted to form the wirings 3, 4, and 5 as the 1st wiring layer, the vertical lines have the allowable minimum line interval of the 2nd layer which is larger than that of the 1st layer and the line interval is wider than necessary.
  • the horizontal lines When it is attempted to form the wirings 3, 4, and 5 as the 2nd wiring layer, the horizontal lines must be depicted in every other line because if it is depicted on the adjacent horizontal line, the line interval becomes insufficient. However, in this case, such line interval becomes 10 ⁇ m ⁇ 2 which is larger than the 15 ⁇ m required. Thus, in any case, line interval becomes large in the vertical or horizontal line portions of wiring, resulting in reduction of integration density.
  • the size of a cell is selected to be an integer times the grid interval, and when the cell is disposed within a chip the input and output terminals are usually arranged on the vertical and horizontal lines of the grid.
  • the intervals of vertical and horizontal lines differ, if a cell orientation is rotated by 90 degrees (rotation in 90 degrees often occurs due to the convenience of connections, etc.), a problem that the terminals of the cell do not match the arrangement of vertical and horizontal lines will occur. Such a problem suppresses the degree of freedom of layout and also restricts improvement in integration density.
  • This invention discloses a semiconductor integrated circuit and its wiring method, which has eliminated the disadvantages of the existing methods yet maintained the advantages of them.
  • an interval of said vertical and horizontal lines of the grid is selected to a dimension of the greatest common factor of the minimum wiring pitches which can be expressed by the maximum unit indicated by an integer of overlapped plural wiring layers which is not a prime number;
  • the vertical and horizontal dimensions of the cell of integrated circuits which are formed by the abovementioned wiring method are set to the integer multiple of said interval;
  • the terminals of said cell are arranged in the allowed wiring locations of said vertical and horizontal lines.
  • FIG. 1 explains the existing wiring method.
  • FIG. 2 explains the wiring method of this invention.
  • FIG. 3 explains cell layout.
  • FIG. 4 is a plan view indicating an example of a cell of the present invention.
  • FIG. 5 is an equivalent circuit of the cell shown in FIG. 4.
  • FIG. 6 shows the layout where a couple of cells shown in FIG. 4 are rotated by 90 degrees.
  • FIG. 2 explains a wiring method of the present invention.
  • 10 is a grid with the same interval for the vertical lines and horizontal lines, forming square meshes.
  • This vertical and horizontal line interval d should be selected to the greatest common measure 5 ⁇ m when the allowable minimum pitch of the 1st layer wiring is 10 ⁇ m, while that of the 2nd wiring layer is 15 ⁇ m.
  • the 1st and 2nd layer wirings assuring allowable minimum line interval can be depicted easily by depicting the wiring of the 1st layer on the vertical and horizontal lines in every other line, while depicting the wiring of the 2nd layer on the vertical and horizontal line. In the every two other lines.
  • the 1st layer wiring pattern can be depicted only by drawing the line on the vertical and horizontal lines in every other line (in actuality, a line having a width must be drawn since the wiring has a certain width, but in this figure the width is omitted for simplification), and there is no need of forming the wiring at the portions a and b of the 2nd layer.
  • the wirings 3, 4, 5 can be formed as the 2nd layer. In this case, the drawing of wiring patterns for both the vertical and horizontal parts on the vertical and horizontal lines of the grid is required in every two other line.
  • the line interval does not exceed the required interval and thereby the integration density is improved.
  • This can be done only by depicting the wiring patterns according to the rule that the pattern of the 1st layer should be depicted on the vertical and horizontal lines in every other line, while that of the 2nd layer in every two other lines.
  • it goes without saying that it is also possible to make wiring with an interval larger than that mentioned above under the condition of connection with the cell terminals and other conditions.
  • the check required for the wiring patterns depicted is to find out the use of the adjacent grid or the use of the grid one or two lines apart; breaking the rule that the pattern should be drawn in every other one or two other lines, and the check whether each wiring pitch maintains an interval of 10 ⁇ m or 15 ⁇ m or not which has been carried out in the existing section paper system is no longer required. This actually results in a significant advantage. Namely, in the case of the system shown in FIG.
  • the check of wiring pitch can be done (for the first layer wiring), for example, by storing the horizontal part of each wiring pattern in the memory (1 or 0 for each horizontal line according to the line depicted or not depicted on such horizontal line with the X coordinate considered as an address), storing in the same way the vertical part in the memory and by checking whether the line is depicted in the horizontal part on both sides of each line (including the part slightly preceding the line because the diagonal direction should also be considered), namely checking whether 1 is stored or not (should not be stored in the normal condition). This check can be carried out with comparative easiness.
  • the section paper system assures high flexibility due to excessive degree of freedom but is not suited for automatic wiring due to complicated programming.
  • the existing grid system is very simple, and is suitable for application of the line search method (the empty vertical and horizontal lines are searched according to the connection command and when an empty line is found, wiring is depicted on it) and a channel router (for example, the necessary vertical line group is depicted along the vertical grid line at the time of connecting between cells 1 and 2, and then terminals of cells 1 and 2 connected in common using the above vertical lines as the bus line are connected by the horizontal lines).
  • this method has a disadvantage that degree of freedom in layout is small because the horizontal wirings are carried as the 1st wiring layer and the vertical wirings are made as the 2nd wiring layer.
  • the present invention has succeeded in introducing the advantages of the foregoing systems but eliminating the disadvantages.
  • the concept of the grid system still maintains a simplified check of wiring and allows high degree of freedom to prevent complication of wirings, reduction of integration density and deterioration of characteristic.
  • the grid interval is determined on the basis of the minimum wiring pitch of each wiring layer but in case the greatest common measure or factor becomes very small (in this case many vertical and horizontal lines must be depicted between the wiring patterns of each layer), the minimum wiring pitch is selected at a value which is larger than the allowable minimum pitch and convenient for use.
  • the allowable minimum pitches are not 10 ⁇ m and 15 ⁇ m, but 10 ⁇ m and 14 ⁇ m, and therefore the greatest common factor is 2 ⁇ m
  • the grid pitch should be determined by the greatest common factor among these layers.
  • the allowable minimum wiring pitch of the 3rd layer in the above example is 17 ⁇ m
  • wiring can be made using a grid of 5 ⁇ m as the greatest common factor of these three layers.
  • the grid pitch should be selected to the greatest common factor of the allowable minimum line intervals of these layers. In this case also adjustment is necessary so that said pitch is not selected to an excessively small value.
  • FIG. 4 shows an embodiment of a cell of a semiconductor integrated circuit generated by said wiring method.
  • 10 is a grid shown in FIG. 2 having an interval of 5 ⁇ m which is the greatest common factor of the wiring pitches of the 1st and 2nd wiring layers . . . of an integrated circuit, for which the wiring pitch of the 1st layer is 10 ⁇ m and of the 2nd layer is 15 ⁇ m in the preceding example.
  • 20 is a cell similar to cells 1 and 2 of FIG. 1 in the above example. The vertical and horizontal dimensions are selected to be an integer multiple of the interval (5 ⁇ m) of the square mesh grid 10. In this example, this cell 20 is selected to such dimensions as 5 ⁇ 18 ⁇ m in vertical and 5 ⁇ 9 ⁇ m in horizontal.
  • This cell 20 is the CMOS NOR gate with two inputs and its equivalent circuit is shown in FIG. 5.
  • FIG. 6 is an example of a cell disposed by rotation of 90 degrees.
  • 21, 22 are cells disposed vertically and horizontally, respectively; 10 a and 10 b are respectively vertical and horizontal intervals of the grid.
  • the cells 21 and 22 have the same dimensions where the longer side is 18 times of the grid interval, while the shorter side is 9 times of the grid interval.
  • 21 a, 21 b, . . . 22 a, 22b, . . . are terminals which are arranged with the interval larger than the allowable minimum line interval and being matched with the vertical and horizontal lines of grid. Therefore, they easily and accurately match the wirings 23 a, 23 b, . . . provided by the grid system.
  • 24 a, 24 b . . . are contact windows.
  • the wiring 23 d connected by the contact window 24 d is respectively provided on the 2nd layer in the left side of the figure and 1st layer in the right side.
  • wiring in the cell follow the wiring method of the present invention, and wiring may be done at the outside of the grid.
  • layout can be simplified and automatic wiring becomes possible.
  • a high degree of freedom in circuit design can be obtained.
  • advancement of design automation (DA) for layout directly brings about easy manufacture of a large scale integrated circuit having high integration density and performance which can provide the outstanding result of the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
US06/198,131 1979-02-27 1980-02-22 Semiconductor integrated circuit and wiring method Expired - Lifetime US4412240A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP54-22289 1979-02-27
JP2228979A JPS55115353A (en) 1979-02-27 1979-02-27 Cell rotatable by 90

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US (1) US4412240A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0026233B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS55115353A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3071715D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1980001859A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564773A (en) * 1981-08-13 1986-01-14 Fujitsu Limited Semiconductor gate array device having an improved interconnection structure
US4686629A (en) * 1984-05-10 1987-08-11 Rca Corporation Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
US4716450A (en) * 1984-06-26 1987-12-29 Nec Corporation Semiconductor integrated circuit having complementary field effect transistors
US5175604A (en) * 1985-11-15 1992-12-29 Kabushiki Kaisha Toshiba Field-effect transistor device
US5264390A (en) * 1990-10-02 1993-11-23 Hitachi, Ltd. Method of automatic wiring in a semiconductor device
US5404033A (en) * 1992-08-20 1995-04-04 Swift Microelectronics Corporation Application specific integrated circuit and placement and routing software with non-customizable first metal layer and vias and customizable second metal grid pattern
US5581097A (en) * 1993-10-13 1996-12-03 Kawasaki Steel Corporation Method of fabricating semiconductor device using shared contact hole masks and semiconductor device using same
US6185722B1 (en) * 1997-03-20 2001-02-06 International Business Machines Corporation Three dimensional track-based parasitic extraction
US6436804B2 (en) * 1998-06-23 2002-08-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US20060136848A1 (en) * 2004-12-20 2006-06-22 Matsushita Electric Industrial Co., Ltd. Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
US20070264758A1 (en) * 2005-06-27 2007-11-15 International Business Machines Corporation Systems and arrangements to interconnect components of a semiconductor device
US9659129B2 (en) 2013-05-02 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell having cell height being non-integral multiple of nominal minimum pitch

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
DE3902693C2 (de) * 1988-01-30 1995-11-30 Toshiba Kawasaki Kk Mehrebenenverdrahtung für eine integrierte Halbleiterschaltungsanordnung und Verfahren zur Herstellung von Mehrebenenverdrahtungen für integrierte Halbleiterschaltungsanordnungen
US5157618A (en) * 1988-03-10 1992-10-20 Cirrus Logic, Inc. Programmable tiles
US4931946A (en) * 1988-03-10 1990-06-05 Cirrus Logic, Inc. Programmable tiles
CN111651958B (zh) * 2020-05-22 2022-06-21 深圳华大九天科技有限公司 一种集成电路版图中遵循布线格点的交互式布线方法
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564773A (en) * 1981-08-13 1986-01-14 Fujitsu Limited Semiconductor gate array device having an improved interconnection structure
US4686629A (en) * 1984-05-10 1987-08-11 Rca Corporation Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
US4716450A (en) * 1984-06-26 1987-12-29 Nec Corporation Semiconductor integrated circuit having complementary field effect transistors
US5175604A (en) * 1985-11-15 1992-12-29 Kabushiki Kaisha Toshiba Field-effect transistor device
US5264390A (en) * 1990-10-02 1993-11-23 Hitachi, Ltd. Method of automatic wiring in a semiconductor device
US5404033A (en) * 1992-08-20 1995-04-04 Swift Microelectronics Corporation Application specific integrated circuit and placement and routing software with non-customizable first metal layer and vias and customizable second metal grid pattern
US5581097A (en) * 1993-10-13 1996-12-03 Kawasaki Steel Corporation Method of fabricating semiconductor device using shared contact hole masks and semiconductor device using same
US6185722B1 (en) * 1997-03-20 2001-02-06 International Business Machines Corporation Three dimensional track-based parasitic extraction
US6436804B2 (en) * 1998-06-23 2002-08-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US6645842B2 (en) 1998-06-23 2003-11-11 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
US20060136848A1 (en) * 2004-12-20 2006-06-22 Matsushita Electric Industrial Co., Ltd. Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
US7503026B2 (en) 2004-12-20 2009-03-10 Panasonic Corporation Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
US20090138840A1 (en) * 2004-12-20 2009-05-28 Panasonic Corporation Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
US20070264758A1 (en) * 2005-06-27 2007-11-15 International Business Machines Corporation Systems and arrangements to interconnect components of a semiconductor device
US7749816B2 (en) * 2005-06-27 2010-07-06 International Business Machines Corporation Systems and arrangements to interconnect components of a semiconductor device
US9659129B2 (en) 2013-05-02 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell having cell height being non-integral multiple of nominal minimum pitch
US10289789B2 (en) 2013-05-02 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. System for designing integrated circuit layout and method of making the integrated circuit layout
US10867099B2 (en) 2013-05-02 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. System for designing integrated circuit layout and method of making the integrated circuit layout
US11544437B2 (en) 2013-05-02 2023-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. System for designing integrated circuit layout and method of making the integrated circuit layout
US12153868B2 (en) 2013-05-02 2024-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having non-integral multiple pitch

Also Published As

Publication number Publication date
DE3071715D1 (en) 1986-10-02
JPS6330784B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-06-21
EP0026233A1 (en) 1981-04-08
WO1980001859A1 (fr) 1980-09-04
EP0026233B1 (en) 1986-08-27
JPS55115353A (en) 1980-09-05
EP0026233A4 (en) 1983-04-25

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