US3803589A - Display signal converting apparatus - Google Patents

Display signal converting apparatus Download PDF

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Publication number
US3803589A
US3803589A US00203597A US20359771A US3803589A US 3803589 A US3803589 A US 3803589A US 00203597 A US00203597 A US 00203597A US 20359771 A US20359771 A US 20359771A US 3803589 A US3803589 A US 3803589A
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Prior art keywords
signal
lines
character
output lines
signal converting
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Expired - Lifetime
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US00203597A
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English (en)
Inventor
Y Hatsukano
K Nomiya
H Kawagoe
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Definitions

  • G06t 3/00 Mos matrix circuit fci ccnvciiiig dccimai signal [58] Field of Search 340/347, 324.1, 336 into a Character signal to be p y and a drive cuit connected to the second MOS matrix circuit for 5 R f n i d and applying the character signal to and driving the UNITED STATES PATENTS Nakauchi 340/336 R1 DYNAMII) SHlFl H? READ lllll REGISTER ll SlGNAl ll'ltMllllV Q luminous elements.
  • a signal converting apparatus for converting a bit signal representing predetermined information into a drive signal for operating a display device having a plurality of luminous elements
  • said display signal converting apparatus comprising 1) signal memory means for storing the bit signal, (2) a first signal converting means including a plurality of bit input lines, a plurality of character output lines, the bit input lines and the character output lines being arranged in a matrix circuit, the first coupling means arranged between the bit input lines and the character output lines to respond to a binary signal impressed upon the bit input lines for producing a character output signal on a predetermined one of the character output lines, (3) means for applying the bitsignal to the bit input lines of the first signal converting means, (4) a second signal converting means including a plurality of character lines respectively connected to the character output lines, a plurality of display drive output lines corresponding to the luminous elements, and second coupling means arranged between the character input lines and the drive output lines to respond to the character output signals applied to the predetermined one of the character lines
  • FIG. 1 is a block connection diagram of one embodiment of the display signal converting apparatus constructed according to the teaching of this invention
  • FIG. 2v shows an equivalent circuit .of the circuit shown in FIG. 1; I I
  • FIGS. 3a and .4 are plan views of a portion of the novel display signal converting apparatus fabricated by integrated circuit technique
  • FIGS. 5 and 6 are sectional views to show different steps of fabricating the integrated circuit
  • FIGS is a connection diagram illustrating a modified embodiment of this invention.
  • FIGS. 9 and 10 show block diagrams showing different display circuit systems
  • FIG. 11 shows waveforms of electric signals helpful to explain the operation of the banking circuit
  • FIG. 12 shows practical constructions of the load resistors shown-in FIG. 1, and
  • FIG. 13 shows an arrangement of the luminous segments of the display device adapted to display digits.
  • FIG. 1 of the accompanying drawing shows one embodiment of the novel converting apparatus for providing visual displays of bit signals of a shift register of a table type electronic computer on a display device of the digit type.
  • the result of the operation of an adder is written in a dynamic shift register R,.
  • the information in the dynamic shift register R is circulated through a feedback circuit 1 connected between the input and output of the dynamic shift register to be stored therein.
  • the number of bits of the dynamic shift register is determined dependent upon the magnitude of the information to be stored therein. For example, when it is desired to store decimal numbers of I4 digits, at least 56 bits are required.
  • the bit signal of the digit to be displayed is sent to a readout register R which comprises four bits and acts to convert a series signal into a parallel signal.
  • the converted bit signals are memorized in signal memories M, to M.,.
  • first signal converter D comprises a group of bit input lines 1, to I a group of character output lines m, to m,,,, and coupling means a,, a a a, respectively responsive to bit signals applied to the group of input lines I, to 1,, for providing a character output signal to the selected one of the character output lines m, to m,,,.
  • Each of the coupling means may comprise an insulated gate type field effect transistor (MOSFET) having a gate electrode connected to a bit input line and a drain electrode connected to a character output line, as shown in FIG. 2. More particularly, a MOSFET a, comprises a gate electrode g connected to a bit input line I, and a drain electrode (I connected to a character output line m,.
  • MOSFET insulated gate type field effect transistor
  • FIG. 7 illustrates one example of a combination of memories M, to M, and inverters I, to I.,.
  • pairs of memories and inverters may be formed of MOSFETs h, through h which can be fabricated as an integrated circuit.
  • Register R can also be formed of three delay type flip-flop circuits DF,, DF, and DF, each comprising a MOSFET. Each flip-flop circuit is driven by two phase clock pulses cp, and cp, to shift a binary information signal by the clock pulses cp, and cp In FIG.
  • a signal from register R is stored in an input capacitor 2 of the MOSFET h through a gating MOSFET h, to produce an inverted output of the input signal at the drain electrode of MOSFET h.
  • a signal of the same phase is derived out from the drain electrode of an inverter MOSFET h
  • a second signal converter D comprises a group of character input lines m, to m',,,,, respectively, connected to corresponding ones of the character output lines m, to m,,,, a group of display drive output lines n to n, disposed at right angles with respect to lines m to m,,, and coupling means disposed to respond to the signals impressed upon input lines m to m' for producing a drive output on predetermined ones of the drive output lines n to ri
  • coupling means disposed to respond to the signals impressed upon input lines m to m' for producing a drive output on predetermined ones of the drive output lines n to ri
  • each of the coupling means comprises a MOSFET having a gate electrode 8 connected to a character input line and a driah electrode connected to a drive output line.
  • a MOSFET b has a gate electrode g connected to the character input line m, and a gate electrode connected to the drive output line m.
  • Drive output lines connected to the drain electrodes are connected to load resistors r to r respectively.
  • load resistors r and r can also be made of MOSFETs as shown in FIG. 12.
  • the output signals from drive output lines it, to n of the second signal converter D are applied to drive circuits B to B respectively which are connected to apply operating voltage to the input terminals 9, to p, of a display device T.
  • the display device T includes eight luminous segments p, to p, which are arranged as shown. As is well known in the art, by selective energization of the luminous segments any one of a group of digits from 0 to 9 can be displayed. There are provided a plurality of such display devices of the number corresponding to the number of digits or of the order of magnitude to be stored in the shift register R Thus for example, where it is desired to display a numericalvalue of 14 digits there are provided 14 display devices. The switching operation of these display devices are effected by a control circuit C For the sake of simplicity, only one display device T is shown in FIG. 1. Actually, however, as diagrammatically shown in FIG.
  • a plurality of display devices T to T,, of the number corresponding to the number of digits to be displayed are provided which are controlled by control circuit C on a time division basis.
  • display devices T to T may be selectively operated without utilizing the time division control by providing a plurality of signal memories M, to M,,, first signal converters D to D,,,, second signal converters D to D and driving circuits B, to B',,, each of the number corresponding to the number of digits to be displayed.
  • the display system shown in FIG. 9 is more advantageous because it requires a lesser number of component parts.
  • the display apparatus thus far described operates as follows. Upon receipt of a signal to be displayed by respective bits 1, 2, 4 and 8 of readout register R the signals of respective bits are stored concurrently in respective-signal memories. For the sake of understanding, it is now assumed that bit signals 1, 0, l and 0 representing a decimal digit 5 are stored in memories M M M and M.,, respectively. If level 1 is represented by a voltage-V and level 0 by a voltage of 0, respective memories will'store signal voltages of -V, 0, -V and 0, respectively.
  • input lines 1 l l and I constitute a NOR input circuit for output line m and the voltage V impressed upon bit input lines l l l and I, will produce a 0 output voltage on all output lines exceptingoutput lines m
  • the first signal converter D is constructed such that it produces an output voltage on only one of the character output lines m to m in accordance with input signal voltages impressed upon its bit input lines I, to 1, inclusive.
  • the apparatus can be readily fabricated as an integrated circuit on a semiconductor substrate.
  • each MOSFET constituting the NOR circuit can be readily formed by making thinner the thick ness of a portion 13 of the silicon oxide layer 12 extending between'drain semiconductor region m d and source semiconductor region m s underlying metal layer 1 than that of the layer 12.
  • the thickness of the portion 13 may be made to be l/ 10 to l/2O of that of layer 12, for example 1,000A. Consequently, portion 13 acts as the insulated gate of the MOSFET to enable channel control between the source and drain electrodes.
  • the source semiconductor region may be provided in common for adjoining drain semiconductor regions.
  • the number of source semiconductor regions can be reduced to one half of that of the drain semiconductor region thereby increasing the density of the elements of the integrated circuit.
  • load resistors r to r as MOS- FETs, respectively, they can also be formed as a part of the integrated circuit of the silicon semiconductor substrate 10.
  • the design of the display signal converting apparatus should be changed in accordance with the construction of the display device. More particularly, although in the above description a converting apparatus utilizing luminescent elements combined to form a crisscross bounded by a rectangle has been shown, manufacturers may utilize a display device in which the luminescent elements are combined to form a figure 8 or another letter. For this reason, integrated circuit manufacturers are required to manufacture display signal converting apparatus having matrix circuits suitable for such different display devices. This invention can meet such a requirement by merely changing the pattern of the mask utilized to form the insulated gate of the second signal converting device D shown in FIG. 3. This is extremely advantageous for IC manufacturers because they can manufacture many types of products ordered by customers without the necessity of largely changing the manufacturing steps.
  • the input level to the drive circuit means for the display devices is at an OFF LEVEL or an ON level.
  • the input level to the drive circuit required to operate the luminescent segments of the display device corresponds to the ON level (0 volts) of the output of the second signal converting device. If it is desired to use an OFF level (-V volts for the input level for operating the luminescent segments this can be readily accomplished by changing the positions of the MOS- FETS included in the second signal converter device. This can also be readily accomplished by changing the pattern design of the mask.
  • the operation of one example of the blanking circuit will now be described with reference to FIG. 11.
  • the luminous or operating voltages suppliedto various display devices through the control circuit C on a time division basis are distributed with the time phases as shown inFlG. l'la through 11d.
  • the signals to drive the first, second, third. nth display devices are also supplied insuccession to the display devices through the driving circuit B in the periods of time t t t t respectively.
  • the time period of the first display device mainly displays a numeral corresponding to the signal to drive the first display device.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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US00203597A 1970-12-02 1971-12-01 Display signal converting apparatus Expired - Lifetime US3803589A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP45105831A JPS5013132B1 (de) 1970-12-02 1970-12-02

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JP (1) JPS5013132B1 (de)
DE (1) DE2159901C3 (de)
IT (1) IT941936B (de)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947721A (en) * 1973-06-22 1976-03-30 Matsushita Electric Industrial Company, Ltd. Liquid crystal device
US3947976A (en) * 1975-03-10 1976-04-06 Eric F. Burtis Mathematical problem and number generating systems
USD242741S (en) * 1974-09-03 1976-12-14 Micon Industries Electroluminescent character D
USD242824S (en) * 1974-09-03 1976-12-21 Micon Industries, a California Corporation Electroluminescent character B
USD242823S (en) * 1974-09-03 1976-12-21 Micon Industries, a California Corporation Electroluminescent character K
USD242821S (en) * 1974-09-03 1976-12-21 Micon Industries Electroluminescent character X
USD242822S (en) * 1974-09-03 1976-12-21 Micon Industries Electroluminescent character R
US4149151A (en) * 1976-05-25 1979-04-10 Hitachi, Ltd. Display data synthesizer circuit
GB2164777A (en) * 1984-09-19 1986-03-26 Telepane Inc Improvements in or relating to alphanumeric display modules
US4603495A (en) * 1984-09-19 1986-08-05 Stevens John K Alphanumeric display modules
US5373291A (en) * 1992-01-15 1994-12-13 Texas Instruments Incorporated Decoder circuits
US6005537A (en) * 1992-08-21 1999-12-21 Hitachi, Ltd. Liquid-crystal display control apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2941639C3 (de) * 1979-10-13 1982-04-22 Deutsche Itt Industries Gmbh, 7800 Freiburg MOS-Binär-Dezimal-Codewandler

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3204234A (en) * 1961-08-08 1965-08-31 Tohoku Oki Electric Company Lt Matrix controlled numeral display
US3396378A (en) * 1965-08-17 1968-08-06 Gen Precision Systems Inc Thermochromic display system
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340524A (en) * 1963-03-08 1967-09-05 Ind Macchine Elettroniche I M Device for the digital display of data stored in electronic circuits
GB1277114A (en) * 1968-09-09 1972-06-07 Texas Instruments Inc Mos-bipolar high voltage driver circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3204234A (en) * 1961-08-08 1965-08-31 Tohoku Oki Electric Company Lt Matrix controlled numeral display
US3396378A (en) * 1965-08-17 1968-08-06 Gen Precision Systems Inc Thermochromic display system
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3947721A (en) * 1973-06-22 1976-03-30 Matsushita Electric Industrial Company, Ltd. Liquid crystal device
USD242822S (en) * 1974-09-03 1976-12-21 Micon Industries Electroluminescent character R
USD242741S (en) * 1974-09-03 1976-12-14 Micon Industries Electroluminescent character D
USD242824S (en) * 1974-09-03 1976-12-21 Micon Industries, a California Corporation Electroluminescent character B
USD242823S (en) * 1974-09-03 1976-12-21 Micon Industries, a California Corporation Electroluminescent character K
USD242821S (en) * 1974-09-03 1976-12-21 Micon Industries Electroluminescent character X
US3947976A (en) * 1975-03-10 1976-04-06 Eric F. Burtis Mathematical problem and number generating systems
US4149151A (en) * 1976-05-25 1979-04-10 Hitachi, Ltd. Display data synthesizer circuit
GB2164777A (en) * 1984-09-19 1986-03-26 Telepane Inc Improvements in or relating to alphanumeric display modules
US4603495A (en) * 1984-09-19 1986-08-05 Stevens John K Alphanumeric display modules
US5373291A (en) * 1992-01-15 1994-12-13 Texas Instruments Incorporated Decoder circuits
US6005537A (en) * 1992-08-21 1999-12-21 Hitachi, Ltd. Liquid-crystal display control apparatus
US6259421B1 (en) 1992-08-21 2001-07-10 Hitachi, Ltd. Liquid-crystal display control apparatus
US6396464B2 (en) 1992-08-21 2002-05-28 Hitachi, Ltd. Liquid-crystal display control apparatus

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Publication number Publication date
JPS5013132B1 (de) 1975-05-17
DE2159901A1 (de) 1972-07-27
IT941936B (it) 1973-03-10
DE2159901B2 (de) 1978-07-20
DE2159901C3 (de) 1985-06-20

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