US3700977A - Diffused resistor - Google Patents

Diffused resistor Download PDF

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Publication number
US3700977A
US3700977A US116144A US3700977DA US3700977A US 3700977 A US3700977 A US 3700977A US 116144 A US116144 A US 116144A US 3700977D A US3700977D A US 3700977DA US 3700977 A US3700977 A US 3700977A
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resistor
epitaxial layer
high impedance
coupled
low
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Gerald K Lunn
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Motorola Solutions Inc
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Motorola Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/136—Resistors

Definitions

  • ABSTRACT There is disclosed an improved technique for reducing or eliminating parasitic capacitance associated with diffused resistors in which the normal buried layer is eliminated and in which each resistor is either fully or partially surrounded by an isolation ring.
  • the epitaxial layer between the resistive element and the isolation ring is provided with a back bias either at one end of the resistor or at the point along the resistor at which no signal exists. In one case this may be accomplished by shorting the epitaxial layer to the low impedance end of the resistor.
  • the resistor is polarized having a low impedance end and a high impedance end, such that the end to which the epitaxial layer is shorted is the end which is coupled to the low impedance node of a circuit.
  • the epitaxial layer is provided with back bias adjacent that point along the length of the resistor at which no signal appears.
  • a guard circuit which minimizes parasitic capacitance in cases where a low resistivity epitaxial layer or a buried layer is provided.
  • the guard circuit is in the form of an impedance convertor having a high impedance output applied to the high impedance end of the resistor while the low impedance of the convertor is coupled to an epitaxial layer contact adjacent this high impedance end.
  • an additional epitaxial layer contact is provided adjacent the low impedance end of the resistor and is shorted thereto so as to provide the aforementioned back bias.
  • This invention relates to an improved diffused resistance element and more specifically to a technique for reducing parasitic capacitance associated with diffused resistors.
  • the reason for the high parasitic capacitance in high frequency circuits utilizing the aforementioned technique, is the fact that the buried layer provides a low resistance underneath the resistor, thus allowing the distributed junction capacitance to collect or lump at one point. Since the parasitic capacitance between the resistive element andthe buried layer is effectively collected or lumped at one point, his more effectively coupled to ground by the buried layer. The parasitic capacitance in this prior art configuration is thus much more of a problem than if the buried layer were not used.
  • a second problem with prior art diffused resistors is the need for back biasing to prevent a diode from being formed somewhere along the resistor between it and the epitaxial layer into which it is diffused. Any contact to the epitaxial layer to provide back bias is surrounded with a region of low impedance to ground. It is this low impedance which makes significant any parasitic capacitance between the resistor and the epitaxial layer. Thus the placement of this back bias contact can be critical in the reduction of parasitic capacitance.
  • the subject invention which includes two embodiments, thus solves the parasitic capacitance problem by either removing the buried layer and providing a shorting contact; or by compensating for the buried layer by providing a guard circuit at one end of the resistor and a shorting contact at the other end.
  • the contact on the epitaxial layer adjacent one end of the diffused resistor is provided with the aforementioned back bias.
  • the contact at one end of the diffused resistor is shorted to the portion of the epitaxial layer immediately adjacent thereto.
  • each resistive element is either encircled or almost completely surrounded by an isolation ring so as to greatly reduce the parasitic capacitance.
  • the effect of back biasing the epitaxial layer adjacent-one end of the resistor is to minimize the capacitive effect of back biasing the epitaxial layer. Because of the placement of the back biasing contact the resistive element is polarized, in the sense that there is an end to be connected to the high impedance node in the particular circuit, while the other end is to be connected to the low impedance node of the circuit.
  • node In any given circuit it will be imrnediately obvious that of the two nodes across which the resistor is to be connected, one node will be a high impedance node and the other node will be a low impedance node. In the situation when the nodes are of equal impedance, that point along the resistor at which no signal occurs, is the point adjacent which the epitaxial layer is to be providedwith back bias. In a first embodiment, no buried layer and a high resistivity epitaxial layer is used to minimize the aforementioned lumping effect.
  • the second embodiment of the invention relates to the use of a low resistivity epitaxial layer and guard circuitry which counteracts such lumping that the high impedance end of the resistor is driven directly with the signal, while the epitaxial layer adjacent this high impedance end is driven with a low impedance replica of the signal.
  • a separate contact to the epitaxial layer is provided adjacent the high impedance end of the resistor.
  • a linear voltage distribution equivalent to the voltage distribution along the resistor is formed along the epitaxial layer-substrate junction directly underneath the resistor. This provides that there be no voltage difference between corresponding points along the resistor and the epitaxial layer. If there is no voltage difference, there is no current flowing from the resistor to the epitaxial layer-substrate junction.
  • the low impedance end has the low impedance end shorted to the epitaxial region adjacent thereto, as in the first configuration so as to back bias the resistor.
  • the guard circuitry minimizes parasitic capacitance between the resistor and the epitaxial layer-substrate junction, while the provision of the back bias to the low impedance end further minimizes the effect of any stray parasitic capacitance.
  • the epitaxial layer resistivity is made sufficiently low either by use of small buried layers within the isolation ring or by doping so that the distributed capacitance from the epitaxial layer to the substrate does not significantly affect the voltage distribution'along the epitaxial layer. In this manner, the resistor driven by the aforementioned impedance con- -vertor is completely guarded and the capacitance from the resistor to the epitaxial layer has no effect.
  • FIG. 3 is a diagram showing one e'mbodimentof the improved diffused resistor in which the buried layer is removed and in which the resistor is surrounded by an isolation ring, the epitaxial layer adjacent one end of the resistive element being provided with a back bias potential.
  • FIG. 4 is atypical amplifying circuit showing the low impedance and high impedance nodes across which the resistive element shown in FIG. 3 is shown connected.
  • FIG. 5 is a schematic diagram showing the parasitic capacitance developed between the resistive element of FIG. 3 and the epitaxial layer and the distributed capacitance between the epitaxial layer, and ground.
  • FIGS. 6 and 7 are top views of two different embodiments of the improved resistor showing both the case where the resistive element'is completely surrounded by an isolation ring and where the resistive element is only partially surrounded.
  • FIG. 8 shows an alternate embodiment of the invention which includes the combination of anlimpedance convertor and a completely surrounded resistive element having contacts to the epitaxial layer adjacent either end of the resistive element.
  • FIG. 9 is a schematic diagram of the guard circuit connected to the resistor shown in FIG. 8 in which parasitic-capacitance between the resistive element and the epitaxial layer and between the epitaxial layer and AC ground is minimized.
  • each resistor is either fully or partially surrounded by an isolation ring.
  • the epitaxial layer between the resistive element and the isolation ring is provided with back bias either at one end of the resistor or at the point on the resistor at which no signal exists.
  • the epitaxial layer at one end of the resistor is provided with a back bias.
  • the resistor is said to be polarized so as to have a low impedance endand a high impedance end. The end at which the epitaxial layer is provided with back bias becomes the low impedance end.
  • the epitaxial layer is provided with a back bias at that point along the length of the resistor at which no signal appears.
  • an additional guard circuit which further minimizes the parasitic capacitance.
  • the guard circuit functions as an impedance convertor such that the high impedance signal from the convertor is applied to the resistor-at its high impedance end while the low impedance output of the convertor is coupled to the epitaxial layer contact adjacent this high impedance end.
  • An additional epitaxial layer contact is provided adjacent the low impedance end for the provision of back bias adjacent thereto.
  • FIG. 1 a P-type material 13 is shown diffused into an N-type epitaxial layer 14 which is deposited on'an N+ type buried layer 15. In this configuration the buried layer 15 is diffused into a P-type substrate 17. Unfortunately, this configuration maximizes the parasitic capacitance problem because the low resistance buried layer 15 effectively connects the whole epitaxial island 14 to AC ground.
  • One coupling path is through an AC decoupling circuit 18 and is shown by a dotted line 19 going through the epitaxial island 14 to a contact 20.
  • the necessary V+ back bias voltage is applied to the contact 20 so as to reverse bias the junction between the resistive elements and the epitaxial layer to prevent transistor action. Normally this back biasing is provided with.
  • the other low impedance path, between the buried layer 15 and the AC ground, is provided through the substrate 17.
  • this substrate lies on a grounded heat sink or header 22 such that the buried layer has a direct capacitance coupled link to the AC ground through the substrate.
  • This capacitance coupled path is shown by dotted line 21 and is caused by the aforementioned lumped capacitance, due to the low resistivity of the buried layer 15.
  • This low resistivity buried layer effectively couples allof the distributed capacitance, shown along resistor 13 of FIG. 2, to ground as follows.
  • the low resistivity of the buried layer effectively eliminates any resistance between the lower ends of the distributed capacitors shown at 26.
  • each of the little parasitic capacitors 26 are effectively shorted together at their lower ends by the buried layer.
  • the buried layer provides a uniform voltage plane which functions as the top plate of the capacitor 27.
  • the top plate of the capacitor 27 is the bottom of the buried layer 15 and the bottom plate is the header 22.
  • the buried layer 15 can be considered the top plate of a large capacitor which directly and strongly couples the distributed capacitance along the length of the resistive element 13 to ground. This latter low impedance path is removed by the removal of the aforementioned buried layer.
  • the resistive element 13 will be directly capacitance coupled to the AC ground as shown in FIG. 2.
  • the buried layer while potentially eliminating stacking faults in growing the epitaxial layer and while providing a uniform potential under all of the resistors in the epitaxial island, generates a far greater problem than it solves, when the resistors are to be used in high frequency circuits.
  • the buried layer and the arbitrary placement of the epitaxial layer contact maximizes the effect of parasitic capacitance distributed along the resistive element.
  • This problem is solved by the subject invention by providing the aforementioned back bias at a predetermined place adjacent the resistor and by providing either a separate isolation region with no buried layer in which the epitaxial layer is of a high resistivity or alternately, or by retaining a portion of the buried layer so as to make the epitaxiallayer of a low resistivity and by providing a guard circuit.
  • the first of these techniques is shown by the structure of FIG. 3.
  • a particular resistor to have low parasitic capacitance is isolated within the island by an isolation ring 30.
  • the particular, resistor is shown in FIG. 3 at 31 to be diffused into an epitaxial layer 32 which is in turn deposited on a substrate of an opposite conductivity type 33.
  • the resistor 31 is P-type material diffused into an N-type epitaxial island which is in turn deposited on a P-type substrate.
  • the isolation ring 30, in this embodiment, is P- type material and in the configuration shown in FIG. 3, completely surrounds the resistive element 31.
  • a contact 34 to the epitaxial region interior to the isolation ring 30. This is accomplished by diffusing an N+ region 35 into the epitaxial layer 32 such that the contact 34 can be made adjacent this one end of the resistive element 31.
  • This end is given a reference numeral 40 and corresponds to the aforementioned low impedance end of the resistor.
  • the contact 34 is shown in spaced adjacency to the end 40 of the resistive element 31 so that the N+ region 35 can be. diffused into the epitaxial layer 32 without contacting the P-region 36.
  • the low impedance end 40 may be shorted to the contact 34 either by external circuitry, as shown by arrows 37, or by providing a shorting bar 55 directly across the contacts, 34 and 38, as shown in FIG. 6.
  • the other end of the resistive element 31 is referred to herein as the high impedance end 41 having a contact 42 thereon.
  • this bias may be provided separately at this low impedance end by applying the necessary voltage at the contact 34. In this case the contact 34 is not shorted to the contact at the low impedance end of the resistor.
  • any given circuit there is usually a low impedance node and a high impedance node across which the resistor is to be connected.
  • This is shown by the simple amplifying circuit of FIG. 4 composed of an NPN transistor 44 having a signal delivered to its base, with its emitter grounded and its collector connected through a diffused resistor to the collector supply voltage V
  • a low impedance node is the collector supply voltage V while the high impedance node is the collector of the transistor 44.
  • a resistor is to be connected between two nodes which node is the high impedance node and which node is the low impedance node.
  • each capacitance 26' is only weakly coupled to ground 25 by the distributed. capacitances 27 along the epitaxial layer 32. There is, however, a direct short, as shown at line 45, which serves to reduce the effect of the parasitic capacitance between the resistive element 31 and epitaxial layer 32.
  • the capacitance from the resistor to the epitax-' ial layer is only significant if there is a low impedance path from the epitaxial layer to ground. The problem then becomes where to put the necessary epitaxial layer contact to minimize the effect of its low impedance region. It will be appreciated that when the subject resistor is connected in a circuit, one end of the resistor will usually be connected to a high impedance node. It is important that the effect of parasitic capacitance is felt most strongly at this high impedance node. Therefore, by placing the epitaxial contact as far away from this high impedance node as possible, the effects of the low impedance region in generating capacitance between the resistor and the epitaxial layer is minimized.
  • the epitaxial layer need not be shorted to one end of the resistor, in normal operation back bias may be supplied by the voltage to the low impedance end of the resistor, and this is why the epitaxial contact is shorted to this low impedance end.
  • the epitaxial layer 32 has a resistance which is higher per unit length than the resistive element 31, the series resistance to the AC ground 25 is significant and the distributed capacitance to ground is determined by the series combination of resistor-to-epitaxial layer capacitance with epitaxial Iayer-to-substrate capacitance.
  • the resistor has a resistance of 200 ohms per mil while the epitaxial layer has a resistance of 500 ohms per mil.
  • resistive element 31 is diffused into epitaxial layer 32 and is completely surrounded by an isolation ring 30. It will be appreciated that the resistive element 31 and the isolation ring have a like conductivity type with the epitaxial layer having an opposite conductivity type.
  • the resistor impedance end of the resistor minimizes the effect of g in this con-figuration is of a P-typehaving a sheet resistivity of 20009.
  • the epitaxial layer 32 is N typeand has a-bulk resistivity of 2Q'-cm.
  • the isolation ring 30 is of a P-type and has an impurity concentration of 10 atoms/cc.
  • the resistor 31' need not be entirelysurrounded by the isolation ring. As shown by the isolation region 60, one end of the resistive element 31' may be left unsurrounded. This is the low impedance end 40' with the high impedance end 41' being well within isolation region 60.
  • This configuration saves on layout space because the contact to the epitaxial layer, hereshown at 61, can be anywhere outside of the isolation region 60.
  • the simulated adjacency of contact 61 to end 40 is provided by the U-shaped isolation region 60 such that the adjacency of the contact 61 to the end 40' is not critical since the rest of the resistive element is shielded by the region 6.0.
  • the end 40 in this case, is shown with a contact 38 audit will be appreciated that either a direct shorting bar may be attached between the contact 61 and contact 38' or the connection therebetween may be made externally as shown at line 62.
  • an alternate configuration which will reduce parasitic capacitance, is one in which theepitaxial layer is of a low resistivity.
  • Thestructure which can be used is shown in FIG. 8 to include a completely encircling isolation ring which surrounds a resistive element 71 having a like conductivity type to that of the isolation ring 70.
  • the resistive element 71 is diffused into an epitaxial layer 72, which is of a low resistivity per unit length and is indeed much lower than that of the resistive element 71.
  • a buried layer is not necessary, a buried layer 73 is shown to be directly underneath the resistive element 71 so as to give the epitaxial layer 72 a lower resistivity. This differs from the configuration shown in FIG.
  • FIG. 8 further differs from the structure shown in FIG. 1 in that two contacts, 74 and 75, are provided adjacent either end of the resistive element 71.
  • the low impedance end of this resistor is shown at a contact 76 which may be either shorted to a contact 75 or connected externally to a back biasing potential, as shown in this figure. This shorting acts in the same manner as the shorting in the embodiment shown in FlG. 3 to reduce the effects of back biasing nected directly to the epitaxial layer.
  • the high impedance end of the resistor is provided with guard circuitry in which the contact 77 is provided with a high impedance version of the input signal, as shown by the line 78, while the contact immediately adjacent the contact 77, i.e., the contact 74, is provided with a low impedance version of the input signal, as shown by the line 79.
  • the input signal, shown at 80, is coupled to an impedance convertor 81 which in general is an emitter follower type circuit involving transistors 82 and 83, which are PNP and NPN transistors, respectively.
  • the emitter of the transistor 82 and the collector of the transistor 83 are coupled through identical resistors 84 and 85 to the supply voltage, shown as V+.
  • the high impedance output is taken at the collector of the transistor 83 while the low impedance output is taken at the emitter of the transistor 82.
  • the low impedance end of the resistor is shown coupled to the power supply voltage V+.
  • Guard circuitry such as that shown by the emitter-follower pair may be-provided separately or may already be part of the circuit in to which the resistor is to be placed.
  • the equivalent circuit is shown in FIG. 9. It will be appreciated that the resistive element 71 is driven by guard circuitry, which in essense is an impedance convertor which lowers the impedance of the input signal while preserving phase and all other aspects.
  • the impedance convertor is therefore represented as box 90 with a +1 therein.
  • an epitaxial layer has a resistivity which is made sufficiently low that the distributed capacitance from the epitaxial layer to the substrate does not significantly effect the voltage distribution along the epitaxial layer, then the resistive element 71 will be completely guarded and the capacitance from the resistive element to the epitaxial layer will have no effect. Even if there is some departure from the linear voltage distribution, there is still a considerable reduction in effective parasitic capacitance. To achieve this significant effect, the end to end epitaxial layer resistance must be lower than that for the resistive element. With high resistivity epitaxial layers, the epitaxial layer resistance is too high to give good results without making the epitaxial island very wide.
  • the guard circuitry represented by the impedance convertor 90 compensates for what would otherwise be an intolerable situation by driving the epitaxial layer, immediately adjacent the high impedance end of the resistive element 71, in such a manner that the signal voltage developed across the parasitic capacitance, shown at 75, between the resistor element 71 and the epitaxial region 72 is zero.
  • the spurious current through the parasitic capacitance is also zero.
  • the capacitor has no effect.
  • the ends of the capacitors 75 will have equal voltages on them.
  • capacitors 76 If any spurious capacitance occurs it will be coupled to the AC ground by capacitors 76. These capacitors are not lumped as in PEG.
  • isolation ring need not fully surround resistive element 71 but may leave the low impedance end of the resistor 71 unsurrounded as in the case shown in FIG. 7.
  • the contact 75 may therefore be placed anywhere outside the isolation ring and be provided with the appropriate back biasing potential.
  • Apparatus for reducing the effects of parasitic capacitance associated with a resistor diffused into a semiconductive material having a lower resistivity per unit length than that of said resistor comprising in combination with said resistor;
  • pedance node adapted to be coupled to said low 5

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US116144A 1971-02-17 1971-02-17 Diffused resistor Expired - Lifetime US3700977A (en)

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DE (1) DE2206793A1 (enrdf_load_stackoverflow)
NL (1) NL7201965A (enrdf_load_stackoverflow)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936789A (en) * 1974-06-03 1976-02-03 Texas Instruments Incorporated Spreading resistance thermistor
EP0000863A1 (de) * 1977-08-18 1979-03-07 International Business Machines Corporation Temperaturkompensierter integrierter Halbleiterwiderstand
FR2430092A1 (fr) * 1978-06-29 1980-01-25 Ibm France Procede de correction du coefficient en tension de resistances semi-conductrices, diffusees ou implantees et resistances ainsi obtenues
EP0017919A1 (en) * 1979-04-16 1980-10-29 Fujitsu Limited Diffused resistor
US4314268A (en) * 1978-05-31 1982-02-02 Nippon Electric Co., Ltd. Integrated circuit with shielded lead patterns
FR2532473A1 (fr) * 1982-08-25 1984-03-02 Philips Nv Resistance integree
US4467312A (en) * 1980-12-23 1984-08-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor resistor device
EP0139027A1 (de) * 1983-10-19 1985-05-02 Deutsche ITT Industries GmbH Monolithisch integrierte Schaltung mit mindestens einem integrierten Widerstand
EP0571814A1 (en) * 1992-05-26 1993-12-01 Texas Instruments Deutschland Gmbh Integrated voltage divider
US6100153A (en) * 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
US20020126839A1 (en) * 2001-01-04 2002-09-12 Haque Yusuf A. Data encryption for suppression of data-related in-band harmonics in digital to analog converters

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3443176A (en) * 1966-03-31 1969-05-06 Ibm Low resistivity semiconductor underpass connector and fabrication method therefor
US3517280A (en) * 1967-10-17 1970-06-23 Ibm Four layer diode device insensitive to rate effect and method of manufacture
US3534237A (en) * 1969-01-21 1970-10-13 Burroughs Corp Power isolation of integrated circuits
US3569800A (en) * 1968-09-04 1971-03-09 Ibm Resistively isolated integrated current switch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3443176A (en) * 1966-03-31 1969-05-06 Ibm Low resistivity semiconductor underpass connector and fabrication method therefor
US3517280A (en) * 1967-10-17 1970-06-23 Ibm Four layer diode device insensitive to rate effect and method of manufacture
US3569800A (en) * 1968-09-04 1971-03-09 Ibm Resistively isolated integrated current switch
US3534237A (en) * 1969-01-21 1970-10-13 Burroughs Corp Power isolation of integrated circuits

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936789A (en) * 1974-06-03 1976-02-03 Texas Instruments Incorporated Spreading resistance thermistor
EP0000863A1 (de) * 1977-08-18 1979-03-07 International Business Machines Corporation Temperaturkompensierter integrierter Halbleiterwiderstand
US4314268A (en) * 1978-05-31 1982-02-02 Nippon Electric Co., Ltd. Integrated circuit with shielded lead patterns
FR2430092A1 (fr) * 1978-06-29 1980-01-25 Ibm France Procede de correction du coefficient en tension de resistances semi-conductrices, diffusees ou implantees et resistances ainsi obtenues
EP0017919A1 (en) * 1979-04-16 1980-10-29 Fujitsu Limited Diffused resistor
US4309626A (en) * 1979-04-16 1982-01-05 Fujitsu Limited Diffused resistor
US4467312A (en) * 1980-12-23 1984-08-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor resistor device
FR2532473A1 (fr) * 1982-08-25 1984-03-02 Philips Nv Resistance integree
US4466013A (en) * 1982-08-25 1984-08-14 U.S. Philips Corporation Tapped integrated resistor
EP0139027A1 (de) * 1983-10-19 1985-05-02 Deutsche ITT Industries GmbH Monolithisch integrierte Schaltung mit mindestens einem integrierten Widerstand
EP0571814A1 (en) * 1992-05-26 1993-12-01 Texas Instruments Deutschland Gmbh Integrated voltage divider
US6100153A (en) * 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
US20020126839A1 (en) * 2001-01-04 2002-09-12 Haque Yusuf A. Data encryption for suppression of data-related in-band harmonics in digital to analog converters
US7068788B2 (en) 2001-01-04 2006-06-27 Maxim Integrated Products, Inc. Data encryption for suppression of data-related in-band harmonics in digital to analog converters

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NL7201965A (enrdf_load_stackoverflow) 1972-08-21

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