US3664117A - Non-time indicating number correction circuit - Google Patents

Non-time indicating number correction circuit Download PDF

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Publication number
US3664117A
US3664117A US43786A US3664117DA US3664117A US 3664117 A US3664117 A US 3664117A US 43786 A US43786 A US 43786A US 3664117D A US3664117D A US 3664117DA US 3664117 A US3664117 A US 3664117A
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United States
Prior art keywords
counter
gate
time indicating
time
signal
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Expired - Lifetime
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US43786A
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Bruce C Mcintosh
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RCA Licensing Corp
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General Electric Co
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G13/00—Producing acoustic time signals
    • G04G13/02—Producing acoustic time signals at preselected times, e.g. alarm clocks
    • G04G13/025—Producing acoustic time signals at preselected times, e.g. alarm clocks acting only at one preselected time
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se

Definitions

  • the gate circuit also includes a time delay to avoid response to such Refemnces Clml transients.
  • the time delay may be provided by a second signal synchronized with the source of transient generation and UNITED STATES PATENTS gated with the strobe signal in a phase to block response to the 3,051,855 8/1962 Lee ..328/48 X transient for one-half cycle of the second signal.
  • This non-time 3,067,936 11/1962 asp et --235/9 indicating number correction circuit is also employed to cor- 3,l63,747 l2/1964 Veverka 2 rect non time indicating numbers in the alarm time counter 3,178,536 1965 Rosenfield 328/48 X when the digital clock is switched to present an alarm time in- 3,307,023 2/l967 Burger ..235/92 di i 3,350,580 10/1967 Harrison ..328/48 X 6 Claims 3 Drawing Figures CLOCK 75 MINUTE HOUR COUNTER COUNTER COUNTER 5
  • the counter While these four flip-flops are gated to recycle upon reaching a count of 9, when power is first applied, or after a power interruption, the counter is capable of assuming states representing non-time indicating numbers such as 10, 1 1, l2, 13, 14 and 15. Although the counters will eventually advance to time indicating numbers, the display of a non-time indicating number is undesirable as it may be taken as a malfunction by the user of the clock.
  • a solution for the elimination of non-time indicating numbers includes a gate circuit responsive to each number outside the time indicating range of numbers of each counter.
  • a high frequency signal source such as the strobe signal which, as described in the above-mentioned application, sequentially switches the time indicating counters to the time display device, is applied to the counters by the gate circuit to rapidly change the count. This count advancing continues until the gate circuit no longer sees a non-time indicating number.
  • the counters in the digital clock described in the abovementioned application are sequentially read out to the display, Accordingly, it is possible to have a count overlay momentari- 1y appear during the transition in sequential switching from the readout of one counter to the readout of another counter so that non-time indicating number may be transiently presented to the gate circuit for correction of such numbers. It is also possible to realize a forbidden count for the moment when the counter changes from one count to the next. As employed in the present discussion, forbidden count is intended to mean a count falling outside of the logic constraints imposed upon the circuitry, which count may result in the display of a non-time indicating number. Thus a delay is provided to prevent response by the gate circuit to such transiently occurring non-time indicating numbers.
  • the delay to the gate means is occasioned by applying to the gate circuit the 60 Hz signal from which the time counters count change signals are derived. Because each counter can only change on the 0 to 1 transition of the 60 Hz signal, this signal is of proper phase to block gate circuit response to the transient for one-half cycle (8.3 milliseconds). This delay is sufficient for the transient to disappear before corrective action is taken.
  • the sequencing strobe When a non-time indicating number transiently appears due to a code overlap, i.e. when the counters are being sequentially presented to the output display, the sequencing strobe itself is gated into the gate means to provide a half cycle delay before such a forbidden number can be responded to for correction by the gate circuit.
  • the sequencing strobe like the 60 Hz signal, is synchronized with the changes in the clock causing the transiently appearing improper codes, so that when these signals are applied in blocking phase relation to the transients they will inhibit response by the gate circuit.
  • FIG. 1 presents a logic diagram of one embodiment of the non-time indicating number correction circuit and a block diagram of the time counter, alarm counter and related portions of a digital clock;
  • FIG. 2 is a timing diagram showing the relationship between the 60 Hz delay signal and the application of the high frequency strobe to the counter;
  • FIG. 3 is a timing diagram showing the relationship between the high frequency strobe and a corrective signal being applied to the counter.
  • FIG. 1 shows a time counter made up of a minute counter 27, a 10 minute counter 59 and an hour counter 77; an alarm counter made up of a 10 minute counter 33 and an hour counter 113.
  • Each of these counters is connected to a switch matrix 53 where the information from the counters are sequentially applied to a display device. Note, for example, the connection of counter 27 to matrix 53 is via lines 45, 47, 49 and 51.
  • a strobe signal from a source not shown is applied via line 135, strobe counter 137, leads 139 and 141 and strobe decoder 143 to switch matrix 53 to cause the sequential application of information from the counters to a display device.
  • the display device although not shown, receives the indication of each counter in sequence via lines 159, 161, 163 and 165, the decimal decoder indicated in FIG. 1 and, for example, a 7 bar decoder (shown in FIG, 1 of the above-mentioned application).
  • NOR gate logic is used throughout the description.
  • the NOR gate responds to any 1 input to produce a 0 output and to an all 0 input to produce a 1 output.
  • the output is an inversion of any binary data stream applied to the other input.
  • the NOR gate will block binary data on the other input.
  • the digital clock gate circuit 15 is also shown in FIG. 1.
  • This gate circuit is substantially identical to the gate circuit shown in FIG. 3 of the above-mentioned application, with the exception that NOR gate 216 has replaced inverting amplifier 303.
  • Gate 15 serves to direct 1 pulse per minute to the clock minute counter during normal operation, 2 pulses per second during slow set operation, 60 pulses per second during fast set operation, and with the addition of NOR gate 216, 3.3 K pulses per second during counter correction operation to either the clock minute counter 27 or the alarm 10 minute counter 33.
  • the input 29 to gate 15 controls whether the output of the gate is directed to the clock counter or to the alarm counter.
  • NOR gate 311 applies a l to NOR gate 311 on line 29 to produce a 0 output from NOR gate 311 while inverter 313 changes the 1 to a 0 input for gate 309 and any time-set information from NOR gate 307 is passed by gate 309. If a 0 is presented to gate 311 by line 29, the output of gate 307 is passed by gate 311 and the 1 presented to gate 309 prevents this gate from passing the information from gate 307.
  • NOR gates 309, 311 and inverter 313 provide a data stream switch to control whether the time counter or the alarm counter receives time-set strobing from either the 60 Hz source applied to gate 305 or the 2 pulse per second source applied to gate 301.
  • NOR gate 301 During normal operation, a 1 appears on line 29 to establish a clock display condition. At this time, a 0 and a l are applied to NOR gate 301 via lines 17 and 19 respectively. The l on line 19 insures that gate 301 has a 0 output. The 0 on line 17 permits gate 216 to pass high frequency correction pulses from NOR gate 215 of the non-time indicating number impossible time correction circuit 210. In the absence of an output from NOR gate 215, the applied from lead 17 to NOR gate 216 will be inverted and appear as a l at the output thereof to insure that the 60 Hz pulse input on lead 21 will not pass gate 305. Thus, the 1 pulse per minute applied to gate 315 on lead 13 is the only input to the clock time counter.
  • the I on line 19 becomes 0, permitting the two pulse per second input on line 23 to pass gate 301.
  • the 0 output from gate 305 remains, permitting the two per second pulses at the input of gate 307 to pass to gate 309 and be applied to gate 315. Since the input at gate 315 is 0 except for the 1 pulse per minute, the two per second pulses are passed, inverted, again inverted by inverter 317 and applied to the clock minute counter.
  • the input on line 17 becomes 1, which is inverted by NOR gate 216 to appear as a permitting 0 at gate 305, allowing the 60 Hz pulses to be applied to gate 307.
  • the other input to this gate is a 0 due to the inversion by gate 301 of its 1 input on line 17.
  • FIG. 1 also shows that the output of the time and alarm counters, as sequentially strobed to the output lines of switch matrix 53 by the decoded strobe signal, is applied to the nontime indicating number correction circuit 210, comprised of NOR gates 211,212, 213, 214 and 215. Gates 211, 212 and 213 respond to all the non-time indicating counts of time counters 27, 59 and 77 or alarm counters 33 and l 13.
  • minute counter 27 is a modulo counter
  • ten minute counter 59 is a modulo 6 counter
  • hour counter 77 is a modulo 12 counter. Accordingly, four flip-flops make up minute counter 27, three flip-flops make up 10 minute counter 59 and four flip-flops make up hour counter 77.
  • Alarm 10 minute counter 33 is made up of three flip-flops and alarm hour counter 113 is made up of four flipflops. Thus, it can be seen that each of the counters can assume non-time indicating numbers.
  • the four flip-flops in the hours counter can assume various states when power is first applied or after power has been interrupted so that the numbers 12, 13, 14 or 15 could be generated; the four flip-flop modulo 10 minute counter can assume codes from 10 through 15, all non-time indicating numbers; and Table I, shows that the three flip-flop modulo 6 10 minute counter can assume the non-time indicating numbers 6 and 7.
  • NOR gate 211 is accordingly responsive to 4 and 8, the 4 and 8 outputs on leads 163 and 165 igspectively as inverted by inverters 218 and 219.
  • gate 211 produces a l at its output so that the gate 214 output is O and NOR gate 215 is thereby enabled to pass the high frequency correction pulses from the strobe source at line 135.
  • Gate 212 is responsive to forbidden codes generated by the ten minute counters 59 or 33. As indicated by Table I, a number 6 and a number 7 are both forbidden numbers which the three flip-flops of the 10 minute counters can assume. Thus, a l indication in both the binary 2 and the binary 4 output pgsitions converted by inverters 217 and 218 to a 0 for 2 and 4 are inputs to NOR gate 212.
  • strobe counter 137 (a three state counter producing a A 0, B 0 output for the minute counter readout; a A l, B 0 output for the 10 minute counters readout; and a A O, B l for the hour counters readout) is l
  • the 10 minute counter information is present at the output of the switch matrix 53 and accordingly gate 212 responds to a 0 from the A output of strobe counter 137.
  • NOR gate 212 presents a 1 to NOR gate 214 so that this gate applies a 0 to enable gate 215 to pass the high frequency correcting signal to gate 15.
  • NOR gate 213 responds to forbidden counts from the clock minute counter 27.
  • Table 1 shows that this modulo 10 four flip-flop counter can assume the binary states of the numbers 10 through 15. Since NOR gate 211 responds to the forbidden numbers 12 through 15, only the numbers 10 and 11 need be recognized by NOR gate 213. The numbers 10 and 11 are both made up of a bina ry 2 and a binary 8. Thus, this NOR gate responds to 2 and 8 in the 0 state.
  • strobe counter 137 provides a A 0 output and a B 0 output to NOR gate 213 via inverters 221 and 220, the minute counter 27 is being read out and ready for monitoring.
  • NOR gate 213 provides a l to NOR gate 214 when A and B and 2 and are all 0 so that the high frequency strobe is applied to gate 15.
  • NOR gates 211, 212, 213 and 214 contain no deliberate delay producing components and will respond almost instantly to any improper time indication presented by the switch matrix 53. Accordingly, non-time indicating numbers which transiently appear will be needlessly detected by these gates.
  • One source of transiently appearing non-time indicating is derived from the counters themselves. When the states of the flip-flops change, an forbidden code may momentarily be present.
  • a delay is included in the correction path by adding the 60 Hz signal to NOR gate 305 in gate circuit 15. Reference is made to FIG. 2 for illustration of the delay obtained by adding the 60 Hz signal.
  • FIG. 2 shows the shaped 60 Hz square wave as presented to NOR gate 305 on lead 21, the high frequency strobe signal output from gate 215 (gate 216 merely acts as an inverter to the output of gate 215 when a 0 appears at its other input), and the resultant output from gate 305.
  • gate 216 merely acts as an inverter to the output of gate 215 when a 0 appears at its other input
  • the resultant output from gate 305 It will be recognized by reference to the above-identified application Serial No. 25, 930, that the very same 60 Hz signal serves as the clock signal for the time and alarm counters. These counters respond to the 60 Hz clock and the signals derived therefrom (2/sec and l/min) only on the O to 1 transition. This is illustrated in FIG.
  • NOR gate 215 indicates that the non-time indicating number correction circuit is responding to a non-time number by passing one pulse of the strobe signal. Because NOR gate 305 is receiving a l input from the 60 Hz signal at this time, the transient correction does not pass gate 305.
  • FIG. 2 also shows that when power is interrupted and reapplied between times and t so that a nontransient non-time indicating number is generated by the counters, the high frequency strobe is passed by gate 215.
  • NOR gate 305 responds to pass the high frequency strobe only when the 60 Hz signal is in the state.
  • the high frequency signal is applied to correct the forbidden indication in, for example, the 10 minute counter where the faulty number was located, but there is no correction between times 1,, and when the 60 Hz signal is in the I state. Correction continues at time 1 correction being completed between times and l
  • the second source of transiently occurring forbidden numbers is the switch matrix 53.
  • FIG. 3 shows that the solution provided by the non-time indicating number correction circuit is to incorporate a second delay in the form of the high frequency strobe itself. It will be appreciated that the gating of the 60 Hz cycle into the correction data stream at NOR gate 305 does not provide correction for transients occurring in the switch matrix, since such transients can occur during the 0 state of the 60 Hz signal and thus correction information would be passed by gate 305.
  • FIG. 3 shows, from top to bottom, the strobe signal as applied to gate 215, the A output of strobe counter 137, the B output of this counter and the output of NOR gates 214, 215, 216 and 305.
  • FIG. 3 is related to FIG. 2 by again showing correction of a continuing forbidden code in the ten minute counter.
  • FIG. 3 provides an exploded view of the signals passed by the gates in the t time period of FIG. 2.
  • the A output of the strobe counter 137 is presented in FIG. 3.
  • the B output of this counter is also presented to indicate the generation of a transient non-time indicating number by switch matrix 53.
  • the output of NOR gate 214 is an inversion of the output of gate 212.
  • gate 214 is accordingly in the 0 state. This occurs during the 10 minute state of strobe counter 137, as indicated in FIG. 3 by the letter T directly beneath the strobe signal illustration.
  • counter 137 is in the hour counter read state as indicated by H and the output of NOR gate 214 has dropped to the 1 state.
  • strobe counter 137 and thus switch matrix 53 changes states in response to the 0 to 1 transition of the strobe so that a forbidden code can be generated only at this transition.
  • the next half cycle of the strobe after the transient forbidden code is produced is a 1 state half cycle so that the output of gate 215 is 0 and the transient correction pulse present at the output of gate 214 does not pass.
  • FIG. 3 also shows the correction pulses for correcting the illegal count in the ten minute counter passing gates 215, 216, and 305. It is seen that during the third readout of the 10 minute counter (indicated by the third T) a legal count is recognized and the pulse of strobe signal is cut short upon recognition of a legal number by gate 212.
  • gates 211, 212, and 213 of the non-time indicating number correction circuit 210 provide an AND function with input inversion, and that gate 214 provides an OR function plus output inversion.
  • a substitute for the NOR logic employed is AND gates to replace NOR gates 21], 212 and 213 and to eliminate inverters 217, 218 and 219.
  • NOR gate 214 could be replaced by an OR gate and an inverter.
  • the AND gate replacing NORgate 211 would respond to counter 4 and 8 information; the AND gate replacing NOR gate 212 would respond to A, 2 and 4 inguts; and the NOR gate 213 replacement would respond to X, B, 2 and 8 inputs.
  • the switch matrix is eliminated as a source of transient forbidden counts and the 60 Hz signal may be used for count correction as well as for delay.
  • separate detectors would be needed for each counter, but the outputs of all such detectors could be summed together for presentation to the non-time indicating number correction circuit.
  • a non-time indicating number correction circuit comprising a signal source, said signal source having a repetition rate that is high compared to the normal time change rate of said counter, and
  • gate means responsive to counter non-time indicating numbers to apply said signal source to advance said counter to a time indicating number.
  • said delay means includes a signal source synchronized with count transitions of the counters
  • the delaying signal being combined with the correction strobe signal in blocking phase relating to count transition transients
  • said correction strobe signal being synchronized with counter readout switching and applied to said gate means in blocking phase relating to readout switching transients, whereby said gate means will not respond to a non-time indicating number transiently occurring at a count transition for one half cycle of said delaying signal and one half cycle of said strobe signal after occurrence of a non-time indicating number due to counter readout switching.

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US43786A 1970-06-05 1970-06-05 Non-time indicating number correction circuit Expired - Lifetime US3664117A (en)

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US (1) US3664117A (enrdf_load_stackoverflow)
CH (2) CH545507A (enrdf_load_stackoverflow)
DE (1) DE2126813A1 (enrdf_load_stackoverflow)
GB (1) GB1352544A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798428A (en) * 1971-03-20 1974-03-19 Seikosha Kk Electronic time-keeping apparatus
US4130319A (en) * 1975-03-25 1978-12-19 Coal Industry (Patents) Limited Mining machines
US4193255A (en) * 1976-01-12 1980-03-18 Citizen Watch Co., Ltd. Electronic timepiece with calendar function
US4196583A (en) * 1976-03-19 1980-04-08 Kabushiki Kaisha Daini Seikosha Analogue electronic alarm timepiece
EP0050350A3 (en) * 1980-10-21 1982-05-26 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Process for comparing the actual time with the contents of a register in an alarm timepiece, circuit therefor and utilisation of said circuit
US4444512A (en) * 1981-10-21 1984-04-24 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Method and circuit for comparing the timekeeping state and contents of a register in an electronic reminder giving timepiece

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2169082B1 (enrdf_load_stackoverflow) * 1972-01-22 1977-02-04 Suwa Seikosha Kk

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3051855A (en) * 1959-09-23 1962-08-28 Bell Telephone Labor Inc Self-correcting ring counter
US3067936A (en) * 1959-11-16 1962-12-11 Itt Coin controlled computer
US3163747A (en) * 1962-05-15 1964-12-29 Western Electric Co Circuit for analyzing selected patterns of multiple intelligence signals
US3178586A (en) * 1961-03-23 1965-04-13 Bell Telephone Labor Inc Self-correcting shift-register distributor
US3307023A (en) * 1963-09-05 1967-02-28 Addressograph Multigraph Electronic counter
US3350580A (en) * 1965-11-30 1967-10-31 Sperry Rand Corp Monitor employing logic gate and counter to indicate normal pulse-train failure after predetermined time interval

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3051855A (en) * 1959-09-23 1962-08-28 Bell Telephone Labor Inc Self-correcting ring counter
US3067936A (en) * 1959-11-16 1962-12-11 Itt Coin controlled computer
US3178586A (en) * 1961-03-23 1965-04-13 Bell Telephone Labor Inc Self-correcting shift-register distributor
US3163747A (en) * 1962-05-15 1964-12-29 Western Electric Co Circuit for analyzing selected patterns of multiple intelligence signals
US3307023A (en) * 1963-09-05 1967-02-28 Addressograph Multigraph Electronic counter
US3350580A (en) * 1965-11-30 1967-10-31 Sperry Rand Corp Monitor employing logic gate and counter to indicate normal pulse-train failure after predetermined time interval

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798428A (en) * 1971-03-20 1974-03-19 Seikosha Kk Electronic time-keeping apparatus
US4130319A (en) * 1975-03-25 1978-12-19 Coal Industry (Patents) Limited Mining machines
US4193255A (en) * 1976-01-12 1980-03-18 Citizen Watch Co., Ltd. Electronic timepiece with calendar function
US4196583A (en) * 1976-03-19 1980-04-08 Kabushiki Kaisha Daini Seikosha Analogue electronic alarm timepiece
EP0050350A3 (en) * 1980-10-21 1982-05-26 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Process for comparing the actual time with the contents of a register in an alarm timepiece, circuit therefor and utilisation of said circuit
US4444512A (en) * 1981-10-21 1984-04-24 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Method and circuit for comparing the timekeeping state and contents of a register in an electronic reminder giving timepiece

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GB1352544A (en) 1974-05-08
CH545507A (enrdf_load_stackoverflow) 1974-01-31
DE2126813A1 (enrdf_load_stackoverflow) 1971-12-16
CH796571A4 (enrdf_load_stackoverflow) 1973-06-29

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