ES485969A1 - Circuito de prueba para emisores de cadencia de funciona- miento sincrono - Google Patents

Circuito de prueba para emisores de cadencia de funciona- miento sincrono

Info

Publication number
ES485969A1
ES485969A1 ES485969A ES485969A ES485969A1 ES 485969 A1 ES485969 A1 ES 485969A1 ES 485969 A ES485969 A ES 485969A ES 485969 A ES485969 A ES 485969A ES 485969 A1 ES485969 A1 ES 485969A1
Authority
ES
Spain
Prior art keywords
clocks
pulses
clock
check
synchronism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES485969A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES485969A1 publication Critical patent/ES485969A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Circuito de prueba para emisores de cadencia de funcionamiento síncrono, caracterizado porque se alimentan señales de tiempo (Ti) de por lo menos dos emisores de cadencia a un circuito de enlace lógico, recorriendo al menos una de las señales de tiempo un dispositivo de retardo.
ES485969A 1978-12-12 1979-11-15 Circuito de prueba para emisores de cadencia de funciona- miento sincrono Expired ES485969A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2853546A DE2853546C2 (de) 1978-12-12 1978-12-12 Prüfschaltung für mindestens zwei synchron arbeitende Taktgeber

Publications (1)

Publication Number Publication Date
ES485969A1 true ES485969A1 (es) 1980-06-16

Family

ID=6056904

Family Applications (1)

Application Number Title Priority Date Filing Date
ES485969A Expired ES485969A1 (es) 1978-12-12 1979-11-15 Circuito de prueba para emisores de cadencia de funciona- miento sincrono

Country Status (9)

Country Link
US (1) US4295220A (es)
EP (1) EP0012185B1 (es)
JP (1) JPS5925980B2 (es)
AU (1) AU528615B2 (es)
BR (1) BR7908071A (es)
CA (1) CA1113575A (es)
DE (2) DE2853546C2 (es)
ES (1) ES485969A1 (es)
IT (1) IT1165393B (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2853523C2 (de) * 1978-12-12 1981-10-01 Ibm Deutschland Gmbh, 7000 Stuttgart Dezentrale Erzeugung von Taktsteuersignalen
US4467412A (en) * 1981-05-18 1984-08-21 Atari, Inc. Slave processor with clock controlled by internal ROM & master processor
US4482819A (en) * 1982-01-25 1984-11-13 International Business Machines Corporation Data processor system clock checking system
US4551836A (en) * 1983-06-22 1985-11-05 Gte Automatic Electric Incorporated Cross-copy arrangement for synchronizing error detection clock signals in a duplex digital system
US4835728A (en) * 1986-08-13 1989-05-30 Amdahl Corporation Deterministic clock control apparatus for a data processing system
DE3767984D1 (de) * 1986-10-16 1991-03-14 Siemens Ag Verfahren und anordnung zur versorgung einer taktleitung mit einem von zwei taktsignalen in abhaengigkeit vom pegel eines der beiden taktsignale.
US4811343A (en) * 1987-03-02 1989-03-07 International Business Machines Corporation On-chip on-line AC and DC clock tree error detection system
US5210846B1 (en) * 1989-05-15 1999-06-29 Dallas Semiconductor One-wire bus architecture
WO1990014626A1 (en) * 1989-05-15 1990-11-29 Dallas Semiconductor Corporation Systems with data-token/one-wire-bus
US5758130A (en) * 1995-08-04 1998-05-26 Apple Computer, Inc. Digital signal distribution for long and short paths
US5742798A (en) * 1996-08-09 1998-04-21 International Business Machines Corporation Compensation of chip to chip clock skew

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1197922B (de) * 1960-10-27 1965-08-05 Int Standard Electric Corp UEberwachungseinrichtung fuer mehrere Impulsquellen
DE1295627B (de) * 1967-01-25 1969-05-22 Siemens Ag Schaltungsanordnung zur UEberwachung von Taktgebern
US3369190A (en) * 1967-02-15 1968-02-13 Collins Radio Co Phase locked indicator for plurality of oscillators phase locked to common reference
CA871381A (en) * 1968-03-20 1971-05-18 Larsen Bjorn Synchronizing pulse comparator circuitry
FR1587572A (es) * 1968-10-25 1970-03-20
GB1236494A (en) * 1969-06-23 1971-06-23 Marconi Co Ltd Improvements in or relating to phase difference detectors
DE2243555A1 (de) * 1972-09-05 1974-04-18 Hartmann & Braun Ag Schaltungsanordnung zur erfassung von betrag und vorzeichen des phasenwinkels zwischen zwei sinusfoermigen elektrischen wechselgroessen
US3803568A (en) * 1973-04-06 1974-04-09 Gte Automatic Electric Lab Inc System clock for electronic communication systems
US3866184A (en) * 1973-08-31 1975-02-11 Gte Automatic Electric Lab Inc Timing monitor circuit for central data processor of digital communication system
US3932847A (en) * 1973-11-06 1976-01-13 International Business Machines Corporation Time-of-day clock synchronization among multiple processing units
DE2612532C3 (de) * 1976-03-24 1978-09-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur Überwachung von zeitlich gestaffelt mehreren Leitungen jeweils als Taktimpulsfolge zugeordneten Taktimpulsen
US4144448A (en) * 1977-11-29 1979-03-13 International Business Machines Corporation Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors

Also Published As

Publication number Publication date
AU5343379A (en) 1980-06-19
DE2963788D1 (en) 1982-11-11
IT1165393B (it) 1987-04-22
US4295220A (en) 1981-10-13
IT7927740A0 (it) 1979-11-30
AU528615B2 (en) 1983-05-05
DE2853546A1 (de) 1980-06-19
EP0012185A1 (de) 1980-06-25
CA1113575A (en) 1981-12-01
JPS5925980B2 (ja) 1984-06-22
DE2853546C2 (de) 1982-02-25
BR7908071A (pt) 1980-07-22
JPS55112574A (en) 1980-08-30
EP0012185B1 (de) 1982-09-29

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