US20240113068A1 - Ultrafine-pitch all-copper interconnect structure and forming method thereof - Google Patents

Ultrafine-pitch all-copper interconnect structure and forming method thereof Download PDF

Info

Publication number
US20240113068A1
US20240113068A1 US18/500,714 US202318500714A US2024113068A1 US 20240113068 A1 US20240113068 A1 US 20240113068A1 US 202318500714 A US202318500714 A US 202318500714A US 2024113068 A1 US2024113068 A1 US 2024113068A1
Authority
US
United States
Prior art keywords
copper
chip
nano
pitch
ultrafine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/500,714
Other languages
English (en)
Inventor
Yu Zhang
Ranyuan ZHANG
Junyu HE
Wenjun Huang
Chengqiang CUI
Guannan YANG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong University of Technology
Original Assignee
Guangdong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong University of Technology filed Critical Guangdong University of Technology
Publication of US20240113068A1 publication Critical patent/US20240113068A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81095Temperature settings
    • H01L2224/81096Transient conditions
    • H01L2224/81098Cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8184Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Definitions

  • This application relates to ultrafine-pitch all-copper interconnection, and more particularly to an ultrafine-pitch all-copper interconnect structure and a forming method thereof.
  • the commonly-used copper-pillar bumps are formed by a copper pillar and a top tin cap, which will still experience collapse during reflow. Because of the relatively low proportion of tin, the collapse within a certain pitch range has little effect on the bump height. However, as the connection pitch becomes smaller and smaller, it is necessary to replace the tin cap with pure copper or silver. Through ultrasonic-assisted sintering of micron silver paste, the ultrafine-pitch micro-copper pillar interconnection has been achieved in the prior art.
  • the traditional solder coating methods have limitations in terms of ultrafine-pitch interconnection, and fail to achieve all-copper interconnection at low temperatures. Moreover, the traditional methods have poor interconnect effect, thereby failing to meet requirements of high-density packaging.
  • An object of the disclosure is to provide an ultrafine-pitch all-copper interconnect structure and a forming method thereof involving low-temperature sintering, which can achieve the ultimate ultrafine-pitch interconnection and meet requirements of high-density packaging, so as to overcome the technical defects existing in the prior art.
  • this application provides a method for forming an ultrafine-pitch all-copper interconnect structure, comprising:
  • the step (1) specifically comprises the following sub-step:
  • the solvent is selected from the group consisting of ethylene glycol, terpineol, polyethylene glycol, rosin, acetone, chloroform, cyclohexane, epichlorohydrin, epoxy resin, primary amine, tertiary amine, and a combination thereof;
  • the step (2) specifically comprises the following sub-steps:
  • the pretreatment is acid treatment, plasma treatment, SAM or a combination thereof.
  • the method further comprises:
  • the step (4) specifically comprises the following sub-step:
  • the protective gas is an inert gas or a reducing gas; the inert gas is nitrogen, argon or helium; and the reducing gas is hydrogen, formaldehyde or carbon monoxide.
  • step (5) the bonding is performed at 150-300° C. and 0-50 MPa under an ultrasonic frequency of 0-100 kHz.
  • this application provides an ultrafine-pitch all-copper interconnect structure, which is obtained by the above forming method.
  • the present disclosure has the following beneficial effects.
  • an ultrafine-pitch all-copper interconnect structure is obtained by mixing nano-copper particles with a solvent, a dispersant and a viscosity modifier to prepare a nano-copper paste; selecting and cleaning a chip with a preset number of copper pillars having a preset diameter and a substrate followed by pretreatment; loading the substrate into a bonding machine, sucking, by the bonding machine, the chip and flipping the chip, such that the copper pillars face outward; sucking the chip by a suction nozzle of the bonding machine to dip the copper pillars in the nano-copper paste; feeding a protective gas, aligning the copper pillars respectively with copper pads on the substrate through an optical system of the bonding machine and performing bonding at a preset pressure and a preset temperature under ultrasonication; and performing cooling at room temperature.
  • This application involves low-temperature sintering and all-copper interconnection. Moreover, a way of dipping the nano-copper paste effectively breaks through limits of a traditional solder coating method in achieving ultrafine-pitch interconnection, which can achieve the ultimate ultrafine-pitch interconnection and meet requirements of high-density packaging.
  • FIG. 1 is a flow chart of a method for forming an ultrafine-pitch all-copper interconnect structure according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart of step (2) of the method according to an embodiment of the present disclosure.
  • FIG. 3 schematically illustrates the forming method according to an embodiment of the present disclosure.
  • FIGS. 1 - 3 provides a method for forming an ultrafine-pitch all-copper interconnect structure, which includes the following steps.
  • this application involves low-temperature sintering and all-copper interconnection.
  • a way of dipping the nano-copper paste effectively breaks through limits of a traditional solder coating method in achieving ultrafine-pitch interconnection, which can achieve the ultimate ultrafine-pitch interconnection and meet requirements of high-density packaging. This can achieve the pure copper interconnection without a presence of other intermetallic compounds.
  • the way of dipping the nano-copper paste can also achieve finer pitch interconnection than the traditional coating method, and achieve lower temperature interconnection through a low melting point of nano-copper materials.
  • S1 specifically included the following sub-step.
  • Nano-copper particles, a solvent, a dispersant and a viscosity modifier were prepared into a nano-copper paste.
  • the nano-copper particles had a particle size of 100 nm or less.
  • a mass percentage concentration of the nano-copper particles in the nano-copper paste was 80% or more.
  • nano-copper particles, a solvent, a dispersant and a viscosity modifier were put into a container and stirred so that the nano-copper particles, the solvent, the dispersant and the viscosity modifier were evenly mixed, thereby preparing a suitable nano-copper paste.
  • the nano-copper particles had a particle size of 100 nm or less.
  • a mass percentage concentration of the nano-copper particles in the nano-copper paste was 80% or more. This resulted in better sintering effect and faster finished product efficiency.
  • the solvent was selected from the group consisting of ethylene glycol, terpineol, polyethylene glycol, rosin, acetone, chloroform, cyclohexane, epichlorohydrin, epoxy resin, primary amine, tertiary amine, and a combination thereof, which results in good solvent effect, good catalytic effect and high reaction efficiency of the nano-copper particles, which resulted in good solvent effect, good catalytic effect and high reaction efficiency of the nano-copper particles.
  • the dispersant was selected from the group consisting of gum arabic, polyvinyl alcohol, polyethylene glycol, gelatin, polyvinyl imidazolidinone, 1-methylimidazole, 2-methylimidazole, 4-methylimidazole, phenylimidazole, 2-ethylimidazole, and a combination thereof.
  • Surfactants described above with opposite properties of lipophilic and hydrophilic can uniformly disperse solid and liquid particles of inorganic and organic pigments that are difficult to dissolve in liquids, and can also prevent a sedimentation and an agglomeration of particles and form an amphiphilic reagent required for stable suspension, which facilitate a dissolution of the nano-copper particles with good mixing effect.
  • the viscosity modifier was selected from the group consisting of methylcellulose, ethylcellulose, hydroxycellulose, primary amine, tertiary amine, acid anhydride and a combination thereof.
  • Methylcellulose has excellent wettability, dispersion, adhesion, thickening, emulsification, water retention and film-forming properties, as well as impermeability to grease. Therefore, the viscosity modifier can increase a reaction efficiency of the nano-copper particles, the solvent, and the dispersant.
  • S2 specifically included the following sub-steps.
  • the copper pillars were appropriately selected and the pitch of the chip was good, which facilitated cleaning and pretreating of the substrate and the chip, making surfaces of the substrate and the chip clean and convenient for processing.
  • the pretreatment was acid treatment, plasma treatment, SAM or a combination thereof.
  • the acid treatment included a dilute sulfuric acid treatment and a dilute hydrochloric acid treatment, which were used to remove metal dust on the surfaces of the substrate and the chip.
  • the plasma treatment included Ar plasma treatment and N 2 plasma passivation surface.
  • the SAM treatment was to perform RCA cleaning and then immersing the chip in a propanethiol solution (1 mM).
  • the method further included the following step.
  • S4 specifically included the following step.
  • the chip was sucked through the suction nozzle of the bonding machine in a closed environment in the presence of the protective gas, and the copper pillars were dipped in the nano-copper paste.
  • the protective gas was an inert gas or a reducing gas
  • the inert gas was nitrogen, argon or helium
  • the reducing gas was hydrogen, formaldehyde or carbon monoxide. This resulted in good protection effect and good safety during processing.
  • the bonding was performed at 150-300° C. and 0-50 MPa under an ultrasonic frequency of 0-100 kHz.
  • the embodiment provides a method for forming an ultrafine-pitch all-copper interconnect structure, which includes the following steps.
  • the embodiment provides a method for forming an ultrafine-pitch all-copper interconnect structure, which includes the following steps.
  • the embodiment provides a method for forming an ultrafine-pitch all-copper interconnect structure, which includes the following steps.
  • the embodiment provides a method for forming an ultrafine-pitch all-copper interconnect structure, which includes the following steps.
  • the ultrafine-pitch all-copper semiconductor interconnect structures described in Embodiments 2-5 have an overall shear strength of 18.38-31.59 MPa, a shear strength of the copper pillars of 0.12-0.42 N/bump, a resistivity of 4.6-14.5 ⁇ cm, and a high-temperature storage test pass rate of 95%-98%, which means high shear strength, low resistivity, and high pass rate of high-temperature storage test, thereby achieving a limit of ultrafine-pitch interconnection, enabling finer-pitch interconnection, and meeting requirements of high-density packaging.
  • An ultrafine-pitch all-copper interconnect structure is provided according to an embodiment of the present disclosure.
  • the ultrafine-pitch all-copper is fabricated by the method of Embodiments 1-5 described above.
  • the ultrafine-pitch all-copper can achieve finer pitch interconnection and meet requirements of high-density packaging.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)
US18/500,714 2022-11-03 2023-11-02 Ultrafine-pitch all-copper interconnect structure and forming method thereof Pending US20240113068A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211371335.5 2022-11-03
CN202211371335.5A CN115662946B (zh) 2022-11-03 2022-11-03 一种超细节距全铜互连方法及超细节距全铜互连结构

Publications (1)

Publication Number Publication Date
US20240113068A1 true US20240113068A1 (en) 2024-04-04

Family

ID=84996176

Family Applications (1)

Application Number Title Priority Date Filing Date
US18/500,714 Pending US20240113068A1 (en) 2022-11-03 2023-11-02 Ultrafine-pitch all-copper interconnect structure and forming method thereof

Country Status (2)

Country Link
US (1) US20240113068A1 (zh)
CN (1) CN115662946B (zh)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100642746B1 (ko) * 2004-02-06 2006-11-10 삼성전자주식회사 멀티 스택 패키지의 제조방법
CN106205772B (zh) * 2016-07-01 2018-07-03 中国科学院深圳先进技术研究院 铜基导电浆料及其制备与其在芯片封装铜铜键合中的应用
CN110311030A (zh) * 2019-07-19 2019-10-08 厦门理工学院 一种实现全铜互连的led封装方法及led灯
JP6713120B1 (ja) * 2019-12-27 2020-06-24 小松 晃雄 銅焼結基板ナノ銀含浸型接合シート、製法及び接合方法

Also Published As

Publication number Publication date
CN115662946B (zh) 2023-07-07
CN115662946A (zh) 2023-01-31

Similar Documents

Publication Publication Date Title
Fan et al. Effect of electroplated Au layer on bonding performance of Ag pastes
CN112157371B (zh) 一种亚微米Cu@Ag焊膏及其制备方法
CN107877030B (zh) 一种纳米锡铋复合焊膏及制备方法
CN109664048B (zh) 纳米铜膏的制备方法、纳米铜膏及其应用
CN112756841B (zh) 一种用于低温烧结互连的微纳复合银铜合金焊膏及制备方法
US10202512B2 (en) Conductive paste, method for forming an interconnection and electrical device
WO2023109597A1 (zh) 纳米铜焊膏及其在芯片封装互连结构中的应用
JP2017514995A (ja) 低圧焼結用粉末
CN111554445B (zh) 一种表面金属化纳米碳材料复合纳米银膏及其制备方法
US20240113068A1 (en) Ultrafine-pitch all-copper interconnect structure and forming method thereof
Fang et al. Rapid pressureless and low-temperature bonding of large-area power chips by sintering two-step activated Ag paste
CN109659272B (zh) 一种基于可自修复铜纳米颗粒浆料的低温铜铜键合方法
CN116532841A (zh) 一种银焊膏及其制备工艺
CN110181041B (zh) 一种表面进行抗氧化保护的铜颗粒、低温烧结铜膏及使用其的烧结工艺
CN113579563B (zh) 纳米立方银焊膏、互连结构及焊接方法
Jung et al. A review of soft errors and the low α-solder bumping process in 3-D packaging technology
CN114502301A (zh) 接合用铜糊料、接合体的制造方法及接合体
Gao et al. A Cu-Cu Bonding method using preoxidized Cu microparticles under formic acid atmosphere
CN114450107A (zh) 接合用铜糊料、接合体的制造方法及接合体
US10910340B1 (en) Silver sintering preparation and the use thereof for the connecting of electronic components
CN110211934B (zh) 一种抗氧化保护的铜颗粒、烧结铜膏及使用其的烧结工艺
Jiang et al. Defect formation and mitigation in Cu/Cu joints formed through transient liquid phase bonding with Cu-Sn nanocomposite interlayer
WO2022061834A1 (zh) 一种铜颗粒焊膏及其制备方法以及烧结方法
CN116652447A (zh) 用于一步键合的铜基焊膏的制备方法及其键合方法
Wang et al. Low-temperature Copper Sinter-joining Technology for Power Electronics Packaging: A Review

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION