US20230178639A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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US20230178639A1
US20230178639A1 US17/958,787 US202217958787A US2023178639A1 US 20230178639 A1 US20230178639 A1 US 20230178639A1 US 202217958787 A US202217958787 A US 202217958787A US 2023178639 A1 US2023178639 A1 US 2023178639A1
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insulating film
film
contact hole
thickness
impurity region
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Tomohiro Imai
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Renesas Electronics Corp
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Renesas Electronics Corp
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Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a semiconductor device having a contact hole formed in an interlayer insulating film and a method of manufacturing the same.
  • IGBT Insulated Gate Bipolar Transistor
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2013-140885
  • Patent Document 2 Japanese Unexamined Patent Application Publication No. 2016-225566
  • Patent Document 1 discloses an IGBT having a GGEE structure.
  • a pair of trenches are formed in an n-type semiconductor layer, a gate electrode is buried inside the pair of trenches, and an n-type emitter region is formed in a p-type base region located between the pair of trenches.
  • the emitter region is not formed in the base region located between the pair of trenches.
  • a gate potential is supplied to the gate electrode of the active cell, and an emitter potential is supplied to the gate electrode of the inactive cell.
  • Patent Document 2 discloses an IGBT having a GGEE structure similar to that of Patent Document 1.
  • An interlayer insulating film is formed on a semiconductor layer, and a contact hole penetrating the interlayer insulating film and an emitter region is formed.
  • the interlayer insulating film is formed of a stacked film of a silicon oxide film formed by the thermal oxidation method or the CVD (Chemical Vapor Deposition) method and a silicon oxide film such as a PSG (Phospho Silicate Glass) film, a BPSG (Boro Phospho Silicate Glass) film, an NSG (Non-doped Silicate Glass) film, or an SOG (Spin On Glass) film.
  • the inside of the contact hole is filled with a plug mainly made of a tungsten film. Since the tungsten film is deposited not only inside the contact hole but also on the interlayer insulating film, it is necessary to remove the tungsten film on the interlayer insulating film. At that time, there is a problem that a part of the tungsten film is likely to remain as a residue if the upper surface of the interlayer insulating film is not flat.
  • the thickness of the interlayer insulating film differs in each region if the upper surface of the interlayer insulating film is not flat. Therefore, since it is necessary to individually form contact holes for each region, there is a problem that the number of masks increases and the manufacturing cost increases.
  • the upper surface of the interlayer insulating film is planarized by the polishing process using the CMP method, but such a polishing process is a relatively expensive process, and there is also a demand for suppressing the manufacturing cost without using the polishing process as much as possible.
  • a main object of this application is to improve the reliability of a semiconductor device by ensuring the flatness of the upper surface of a thick interlayer insulating film and suppressing residues such as a tungsten film. Another object of this application is to suppress the increase in manufacturing cost. Still another object of this application is to provide a relatively versatile manufacturing method that can be easily implemented in various fabrication facilities.
  • a semiconductor device includes: a semiconductor substrate having a semiconductor layer of a first conductivity type; a first impurity region of a second conductivity type opposite to the first conductivity type formed in the semiconductor layer; a second impurity region of the first conductivity type formed in the first impurity region; a trench penetrating the first impurity region and the second impurity region and reaching the semiconductor layer; a gate insulating film formed inside the trench; a gate electrode formed on the gate insulating film so as to fill an inside of the trench; an interlayer insulating film formed on the semiconductor layer; a contact hole penetrating the interlayer insulating film and the second impurity region and reaching the first impurity region; and a plug filling an inside of the contact hole and electrically connected to the first impurity region and the second impurity region.
  • the interlayer insulating film includes a first insulating film formed on the semiconductor layer and a second insulating film formed on the first insulating film, the first insulating film is a silicon oxide film, the second insulating film is a BPSG film, a thickness of the second insulating film is larger than a thickness of the first insulating film, the contact hole is formed of a first contact hole penetrating the second impurity region and reaching the first impurity region and a second contact hole formed in the first insulating film and the second insulating film and communicating with the first contact hole, and an opening width of the second contact hole is larger than an opening width of the first contact hole.
  • a method of manufacturing a semiconductor device includes: (a) preparing a semiconductor substrate having a semiconductor layer of a first conductivity type; (b) forming forming a trench in the semiconductor layer; (c) forming a gate insulating film inside the trench; (d) forming a gate electrode on the gate insulating film so as to fill an inside of the trench; (e) forming a first insulating film on the semiconductor layer; (f) forming a first impurity region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; (g) forming a second impurity region of the first conductivity type in the first impurity region; (h) forming a second insulating film having a thickness larger than a thickness of the first insulating film on the first insulating film, thereby forming an interlayer insulating film including the second insulating film and the first insulating film on the semiconductor layer; (i) forming a contact hole penetrating the interlayer insulating film and the second
  • the first insulating film is a silicon oxide film
  • the second insulating film is a BPSG film.
  • the (i) includes: (i1) forming a first contact hole in the second insulating film, the first insulating film, the second impurity region, and the first impurity region; and (i2) after the (i1), performing isotropic etching process to the second insulating film and the first insulating film, thereby forming, in the second insulating film and the first insulating film, a second contact hole having an opening width larger than an opening width of the first contact hole and communicating with the first contact hole.
  • the embodiment it is possible to improve the performance of a semiconductor device. Also, according to the embodiment, it is possible to suppress the increase in manufacturing cost.
  • FIG. 1 is a plan view showing a semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing another region of the semiconductor device according to the first embodiment.
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing the manufacturing process subsequent to FIG. 4 .
  • FIG. 6 is a cross-sectional view showing the manufacturing process subsequent to FIG. 5 .
  • FIG. 7 is a cross-sectional view showing the manufacturing process subsequent to FIG. 6 .
  • FIG. 8 is a cross-sectional view showing the manufacturing process subsequent to FIG. 7 .
  • FIG. 9 is a cross-sectional view showing the manufacturing process subsequent to FIG. 8 .
  • FIG. 10 is a cross-sectional view showing another region of the semiconductor device in the manufacturing process subsequent to FIG. 8 .
  • FIG. 11 is a cross-sectional view showing the manufacturing process subsequent to FIG. 10 .
  • FIG. 12 is a cross-sectional view showing the manufacturing process subsequent to FIG. 9 .
  • FIG. 13 is a cross-sectional view showing the manufacturing process subsequent to FIG. 12 .
  • FIG. 14 is an enlarged cross-sectional view of FIG. 13 .
  • FIG. 15 is a cross-sectional view showing the manufacturing process subsequent to FIG. 13 .
  • FIG. 16 is a cross-sectional view showing the manufacturing process subsequent to FIG. 14 .
  • FIG. 17 is a cross-sectional view showing a semiconductor device according to the second embodiment.
  • FIG. 18 is a cross-sectional view showing a semiconductor device according to the third embodiment.
  • FIG. 19 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the fourth embodiment.
  • FIG. 1 is a plan view showing a semiconductor chip which is the semiconductor device 100 .
  • a gate wiring GW is formed around the emitter electrode EE.
  • a region surrounded by a broken line in the emitter electrode EE is an emitter pad EP, and a region surrounded by a broken line in the gate wiring GW is a gate pad GP.
  • a part of each of the emitter electrode EE and the gate wiring GW is covered with a protective film (not shown). The regions exposed from the protective film serve as the emitter pad EP and the gate pad GP.
  • Wire bonding or an external connection terminal such as a clip (copper plate) is connected to the emitter pad EP and the gate pad GP, so that the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.
  • FIG. 2 is a cross-sectional view showing the principal part corresponding to the region 1 A in FIG. 1 .
  • the region 1 A is a cell region in which the IGBT is formed.
  • the IGBT shown in FIG. 2 is an IGBT having a GGEE structure and is an IE-IGBT capable of using IE (Injection Enhancement) effect.
  • the IE effect is a technique for increasing the concentration of charges accumulated in a semiconductor layer ND by making it difficult to discharge holes from the emitter electrode EE side when the IGBT is in an ON state. Therefore, the semiconductor device 100 has an active cell region AC for performing the main operation of the IGBT and an inactive cell region IAC other than the active cell region AC.
  • a gate electrode GE 1 in the active cell region AC is electrically connected to the gate wiring GW, and a gate potential is supplied to the gate electrode GE 1 during the operation of the IGBT.
  • a gate electrode GE 2 in the inactive cell region IAC is electrically connected to the emitter electrode EE, and an emitter potential is supplied to the gate electrode GE 2 during the operation of the IGBT.
  • the semiconductor substrate SUB has a low concentration n-type semiconductor layer (drift region) ND.
  • n-type field stop region (impurity region) NS having an impurity concentration higher than that of the semiconductor layer ND
  • a p-type collector region (impurity region) PC and a collector electrode CE made of a metal film are formed.
  • a collector potential is supplied to the collector region PC via the collector electrode CE.
  • Trenches TR are formed in the semiconductor layer ND on the front surface side of the semiconductor substrate SUB.
  • the trenches TR penetrate an emitter region NE and/or a base region PB described later, and reach the semiconductor layer ND.
  • a gate insulating film GI is formed inside the trenches TR.
  • the gate electrodes GE 1 and GE 2 are formed on the gate insulating film GI so as to fill the inside of the trenches TR.
  • the gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE 1 and GE 2 are, for example, polycrystalline silicon films into which n-type impurities are introduced.
  • a hole barrier region (impurity region) NHB having an impurity concentration higher than that of the semiconductor layer ND is formed in the semiconductor layer ND between the pair of gate electrodes GE 1 .
  • a p-type base region (impurity region) PB is formed in the hole barrier region NHB.
  • An n-type emitter region (impurity region) NE having an impurity concentration higher than that of the hole barrier region NHB is formed in the p-type base region PB.
  • a hole barrier region NHB is formed in the semiconductor layer ND between the pair of gate electrodes GE 2 .
  • a p-type floating region (impurity region) PF is formed in the semiconductor layer ND between the gate electrode GE 1 and the gate electrode GE 2 .
  • a p-type base region PB having an impurity concentration higher than that of the floating region PF is formed in the floating region PF.
  • the floating region PF is preferably formed to a position deeper than the bottom portion of the trench TR, and is more preferably formed so as to cover the bottom portion of the trench TR.
  • An interlayer insulating film IL is formed on the semiconductor layer ND.
  • a contact hole CH penetrates the interlayer insulating film IL and the emitter region NE, and reaches the base region PB.
  • the contact hole CH is formed so as to be in contact with the emitter region NE and the base region PB.
  • a plug PG fills the inside of the contact hole CH and is eletrically connected to the emitter region NE and the base region PB.
  • the configuration of the contact hole CH and the plug PG in the inactive cell region IAC is also substantially the same as that in the active cell region AC, except for the absence of the emitter region NE.
  • a p-type high concentration diffusion region (impurity region) PR having an impurity concentration higher than that of the base region PB is formed around the bottom portion of the contact hole CH.
  • the high concentration diffusion region PR is provided in order to reduce the contact resistance with the plug PG and to prevent the latch-up.
  • the emitter electrode EE is formed on the interlayer insulating film IL 1 .
  • the emitter electrode EE is electrically connected to the emitter region NE, the base region PB, and the high concentration diffusion region PR via the plug PG, and supplies an emitter potential to these regions.
  • the gate wiring GW formed in the same process as the emitter electrode EE is also formed on the interlayer insulating film IL.
  • Such an emitter electrode EE and a gate wiring GW are made of, for example, a TiW film and an aluminum film formed on the TiW film.
  • the aluminum film is the main conductor film of the emitter electrode EE and the gate wiring GW, and is sufficiently thicker than the TiW film.
  • FIG. 3 is a cross-sectional view showing the principal part corresponding to the region 2 A in FIG. 1 .
  • the region 2 A is a semiconductor element formation region different from the region where the IGBT (trench TR and others) is formed in the semiconductor substrate SUB.
  • FIG. 3 shows, for example, a resistance element 10 as a semiconductor element formed in the region 2 A.
  • the resistance element 10 is made of a conductive film formed on the semiconductor layer ND via the gate insulating film GI.
  • Such a conductive film is made of a film in the same layer as the gate electrodes GE 1 and GE 2 , and is made of, for example, a polycrystalline silicon film into which n-type impurities are introduced.
  • the resistance element 10 but also other semiconductor elements such as a pn diode are formed in the region 2 A.
  • the resistance element 10 and other semiconductor elements are electrically connected to the gate wiring GW (gate pad GP) via the plug PG, and constitute a protection circuit for protecting the semiconductor device 100 from a surge voltage applied to the gate pad GP.
  • the interlayer insulating film IL in the first embodiment includes an insulating film IF 1 formed on the semiconductor layer ND and an insulating film IF 2 formed on the insulating film IF 1 ,
  • the insulating film IF 1 is a silicon oxide film containing no impurity, and is a thermal oxide film formed by the thermal oxidation method. Even if the insulating film IF 1 contains an impurity, the impurity concentration thereof is very small and is lower than the concentration of the impurity contained in the PSG film or the BFSG film.
  • the insulating film IF 2 is a silicon oxide film containing boron and phosphorus and is a BPSG film.
  • Phosphorus contained in the insulating film IF 2 plays a role of fixing (gettering) Na ions that degrade the characteristics of the semiconductor element.
  • Boron contained in the insulating film IF 2 plays a role of lowering the melting point of the insulating film IF 2 , so that the insulating film IF 2 is easily melted by the heat treatment. Since the softening point of the insulating film IF 2 is lower than the softening point of the PSG film, the upper surface of the insulating film IF 2 is planarized by performing the reflow process.
  • the upper surface of the interlayer insulating film IL can be easily kept flat even if there is a difference in level between the regions of the semiconductor substrate SUB.
  • the difference in level is likely to occur between the region 2 A and the region 1 A shown in FIG. 3 when forming the insulating film IF 2 (see FIG. 10 and FIG. 11 below).
  • the insulating film IF 1 when the insulating film IF 1 is not provided, diffusion of phosphorus occurs from the insulating film IF 2 to the semiconductor layer ND.
  • the insulating film IF 1 functions as a protective film for preventing the diffusion of phosphorus.
  • the thickness of the insulating film IF 1 is, for example, 100 to 500 angstroms ( ⁇ ).
  • the thickness of the insulating film IF 2 is larger than the thickness of the insulating film IF 1 , and is, for example, 8000 to 10000 angstroms ( ⁇ ).
  • the contact hole CH in the first embodiment is formed of a first contact hole CH 1 and a second contact hole CH 2 communicating with the first contact hole CH 1 .
  • the first contact hole CH 1 is formed in the semiconductor layer ND, penetrates the emitter region NE, and reaches the base region PB.
  • the second contact hole CH 2 is formed in the insulating film IF 1 and the insulating film IF 2 .
  • An opening width of the second contact hole CH 2 is larger than an opening width of the first contact hole CH 1 by 600 angstroms ( ⁇ ) or more.
  • the second contact hole CH 2 includes the first contact hole CH 1 in plan view.
  • the plug PG can be properly and easily buried inside the contact hole CH. Moreover, since the opening width of the second contact hole CH 2 is large, the upper surface of the emitter region NE is also exposed. Therefore, inside the contact hole CH, the plug PG is in contact not only with the side surface of the emitter region NE but also with the upper surface of the emitter region NE. Accordingly, the contact resistance between the plug PG and the emitter region NE can be reduced.
  • the plug PG is formed of a stacked film of a barrier metal film BM and a conductive film CF.
  • the barrier metal film is formed of, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film.
  • the conductive film CF is made of, for example, a tungsten film.
  • a silicide film SI made of a metal material contained in the barrier metal film BM and silicon is formed on the upper surface and the side surface of the emitter region NE, on the base region PB, and on the high concentration diffusion region PR. More specifically, the silicide film SI is an alloy film of a titanium film contained in the barrier metal film BM and silicon constituting the emitter region NE, the base region PB, and the high concentration diffusion region PR, and is a titanium silicide film.
  • a problem in the conventional art is that if the upper surface of the interlayer insulating film IL is not flat when forming the plug PG, a part of the conductive film CF (tungsten film) is left as a residue.
  • the thickness of the interlayer insulating film IL differs in each region, so that it is necessary to individually form the contact holes CH for each region.
  • it is also conceivable to planarize the upper surface of the interlayer insulating film IL by the polishing process using the CMP method there is a problem that the manufacturing cost increases.
  • the insulating film IF 2 is thickened such that the insulating film IF 2 serves as a major part of the interlayer insulating film IL.
  • the upper surface of the insulating film IF 2 is planarized. Therefore, it is possible to solve the problem that the residue of the conductive film CF (tungsten film) is generated and the problem that the contact hole CH needs to be individually formed for each region. Therefore, it is possible to improve the reliability of the semiconductor device.
  • an expensive polishing process by the CMP method is not required, the increase in manufacturing cost can be suppressed.
  • a method of manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to FIG. 4 to FIG 15 .
  • the region 1 A will be mainly described, but the region 2 A will also be described as needed.
  • the semiconductor substrate SUB having the n-type semiconductor layer ND is prepared.
  • the semiconductor layer ND is formed by preparing the p-type semiconductor substrate SUB and then growing an epitaxial layer on the semiconductor substrate SUB by the epitaxial growth method.
  • the n-type semiconductor substrate SUB can be used as the semiconductor layer ND.
  • the n-type hole barrier region NHB and the p-type floating region PF are formed in the semiconductor layer ND by the photolithography method and the ion implantation method.
  • an insulating film made of, for example, a silicon oxide film is formed on the semiconductor layer ND, and the insulating film is patterned by the photolithography method and the dry etching process to form a hard mask.
  • the trenches TR are formed in the semiconductor layer ND by performing the anisotropic etching process using the hard mask as a mask to the semiconductor layer ND.
  • the hard mask is removed by the wet etching process or the like.
  • the hole barrier region NHB is diffused to the vicinity of the bottom portion of the trench TR
  • the floating region PF is diffused to a position deeper than the bottom portion of the trench TR so as to cover the bottom portion of the trench TR.
  • the thermal oxidation process is performed to the semiconductor layer ND to form the gate insulating film GI inside the trenches TR and on the semiconductor layer ND.
  • a conductive film PL such as a polycrystalline silicon film into which n-type impurities are introduced is formed on the gate insulating film GI by, for example, the CVD method so as to fill the inside of the trenches TR.
  • the thickness of the gate insulating film GI is, for example, 1000 angstroms ( ⁇ ).
  • the gate insulating film GI is formed also on the semiconductor layer ND in the region 2 A, and the conductive film PL is formed on the gate insulating film GI.
  • the thickness of the conductive film PL in the region 2 A is, for example, 3000 to 6000 angstroms ( ⁇ ).
  • the conductive film PL formed outside the trenches TR is removed by the dry etching process.
  • the conductive film PL formed inside the trenches TR is left as the gate electrodes GE 1 and GE 2 .
  • the gate insulating film GI formed outside the trenches TR is removed by the isotropic etching process or the anisotropic etching process.
  • the dry etching process of the conductive film PL is performed using a resist pattern having a pattern that opens the region 1 A and partially covers the region 2 A. In this way, the conductive film PL in the region 2 A is patterned to form the resistance element 10 (see FIG. 10 below).
  • the insulating film IF 1 made of a thermal oxide film formed on the semiconductor layer ND by, for example, the thermal oxidation method.
  • the thickness of the insulating film IF 1 is smaller than the thickness of the gate insulating film GI, is equal to or smaller than half the thickness of the gate insulating film GI, and is, for example, 100 to 500 angstroms ( ⁇ ).
  • the p-type base region PB is formed in the semiconductor layer ND (floating region PF and hole barrier region NHB) by the photolithography method and the ion implantation method using the insulating film IF 1 as a through film.
  • the n-type emitter region NE is formed on the surface of the base region PB of the active cell region AC by the photolithography method and the ion implantation method.
  • boron is used for the ion implantation of the base region PB, and the ion implantation is performed under the conditions of an energy of 50 to 300 keV and a dose amount of 1 ⁇ 10 13 cm 2 . Thereafter, for example, heat treatment is performed at 1000° C. for 100 to 200 minutes to diffuse the impurities contained in the base region PB. Also, arsenic or phosphorus or both of them is used for the ion implantation of the emitter region NE, and the ion implantation is performed under the conditions of an energy of 100 keV and a dose amount of 1 ⁇ 10 15 cm 2 . Thereafter, for example, heat treatment is performed at 950° C. for 30 seconds to activate the impurities contained in each impurity region.
  • the insulating film IF 2 is formed on the insulating film IF 1 by, for example, the CVD method.
  • the insulating film IF 2 is a silicon oxide film containing boron and phosphorus, and is a BPSG film.
  • the insulating film IF 1 and the insulating film IF 2 each constitute a part of the interlayer insulating film IL.
  • the thickness of the insulating film IF 2 is larger than the thickness of the insulating film IF 1 , and is, for example, 6000 to 10000 angstroms ( ⁇ ).
  • heat treatment is performed the insulating film IF 2 at, for example, 900 to 950° C. for 30 minutes.
  • the insulating film IF 2 is softened and the upper surface of the insulating film IF 2 is planarized.
  • the upper surface of the insulating film IF 2 after the reflow process is more planarized than the upper surface of the insulating film IF 2 before the reflow process.
  • FIG. 10 and FIG. 11 show the state of the insulating film IF 2 before and after the reflow process.
  • FIG. 10 there is the difference in level on the upper surface of the insulating film IF 2 between the region 1 A and the region 2 A before the reflow process.
  • FIG. 11 the upper surface of the insulating film IF 2 is planarized by performing the reflow process.
  • the expensive polishing process by the CMP method is not performed in the first embodiment, the increase in manufacturing cost can be suppressed.
  • the resistance element 10 is formed in the region 2 A, and the insulating film IF 2 is formed so as to cover the resistance element 10 . Since the thickness of the insulating film IF 2 formed on the resistance element 10 becomes relatively small after the reflow process, it is necessary to adjust the thickness of the insulation film IF 2 such that the resistance element 10 is not exposed after the reflow process. Therefore, the thickness of the insulating film IF 2 formed on the resistance element 10 is preferably larger than the thickness of the resistance element 10 before the reflow process, and is preferably about twice the thickness of the resistance element 10 .
  • the first contact holes CH 1 are formed in the insulating film IF 2 , the insulating film IF 1 , the emitter region NE, and the base region PB by the photolithography method and the dry etching process.
  • the p-type body region PR is formed at the bottom portion of the contact hole CH 1 by the photolithography method and the ion implantation method. Thereafter, heat treatment for activating each impurity region is performed. Boron difluoride is used for the ion implantation of the body region PR, and the ion implantation is performed under the conditions of an energy of 50 to 100 keV and a dose amount of 1 ⁇ 10 15 cm 2 . Thereafter, for example, heat treatment is performed at 950° C. for 30 seconds to activate the impurities contained in each impurity region.
  • the insulating film IF 2 and the insulating film IF 1 are recessed by performing the isotropic etching process to the insulating film IF 2 and the insulating film IF 1 .
  • an aqueous solution containing hydrofluoric acid is used for this isotropic etching process.
  • the second contact holes CH 2 are formed in the insulating film IF 2 and the insulating film IF 1 .
  • the opening width of the second contact hole CH 2 is larger than the opening width of the first contact hole CH 1 , and the second contact hole CH 2 communicates with the first contact hole CH 1 .
  • the contact hole CH which penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB is formed in the active cell region AC.
  • the contact hole CH which penetrates the interlayer insulating film IL and reaches the base region PB is formed also in the inactive cell region IAC.
  • the recessed amount of the insulating film IF 2 and the insulating film IF 1 by the isotropic etching process is preferably 300 angstroms ( ⁇ ) or more.
  • the opening width of the second contact hole CH 2 becomes larger than the opening width of the first contact hole CH 1 by 600 angstroms ( ⁇ ) or more.
  • the etching rate of the insulating film IF 2 in the isotropic etching process is different from the etching rate of the insulating film IF 1 , and is faster than the etching rate of the insulating film IF 1 . Therefore, if the thickness of the insulating film IF 1 is too large, there is a fear that the insulating film IF remains without being removed completely and the upper surface of the emitter region NE is not exposed.
  • the upper surface of the insulating film IF 1 is exposed as the insulating film IF 2 is etched. Consequently, the insulating film IF 1 is etched vertically and laterally as indicated by arrows in FIG. 14 .
  • the insulating film IF 1 can be removed by the isotropic etching process. In this way, the difference between the etching rate of the insulating film IF 2 and the etching rate of the insulating film IF 1 can be effectively reduced.
  • the thickness of the gate insulating film GI is usually set as thick as 1000 angstroms ( ⁇ ). Therefore, it becomes difficult to completely remove the gate insulating film GI outside the trench TR by the isotropic etching process.
  • the insulating film IF 1 having the thickness (for example, 100 to 500 angstroms ( ⁇ )) smaller than the thickness of the gate insulating film GI, the upper surface of the emitter region NE can be easily exposed when forming the second contact hole CH 2 .
  • FIG. 15 shows the manufacturing process subsequent to FIG. 13 .
  • the barrier metal film BM is formed inside the contact holes CH and on the interlayer insulating film IL.
  • the barrier metal film BM can be formed by forming a titanium film inside the contact holes CH and on the interlayer insulating film IL by the sputtering method and then forming a titanium nitride film on the titanium film by the sputtering method.
  • the silicide film SI is formed on the upper surface and the side surface of the emitter region NE, on the base region PB, and on the high concentration diffusion region PR, inside the contact holes CH.
  • the silicide film SI is an alloy film of a metal material (titanium film) contained in the barrier metal film BM and silicon, and is a titanium silicide film.
  • the conductive film CF made of, for example, a tungsten film is formed on the barrier metal film BM by, for example, the CVD method so as to fill the inside of the contact holes CH.
  • the conductive film CF and the barrier metal film BM formed outside the contact holes CH are removed by the dry etch process.
  • the plugs PG which are embedded in the contact holes CH and electrically connected to the emitter region NE and the base region PB are formed.
  • the conductive film CF is formed also on the insulating film IF 2 , since the upper surface of the insulating film IF 2 is planarized, the conductive film CF can be easily removed. Therefore, it is possible to suppress the problem that a residue of the conductive film CF is generated on the insulating film IF 2 .
  • a TiW film is formed on the interlayer insulating film IL by, for example, the sputtering method, and an aluminum film is formed on the TiW film by, for example, the sputtering method.
  • the emitter electrode EE is formed by patterning the TiW film and the aluminum film by the photolithography method and the dry etching process. The emitter electrode EE is electrically connected to the emitter region NE and the base region PB via the plug PG.
  • a contact hole for gate electrode that reaches a part of the gate electrode GE is also formed in the same steps as those in FIG. 12 and FIG. 13 . Also, a plug is formed inside the contact hole for gate electrode and the gate wiring GW in the same layer as the emitter electrode EE is formed in the same steps as those in FIG. 15 and FIG. 16 .
  • a contact hole CH 3 is formed on the resistance element 10 in the same steps as those in FIG. 12 and FIG. 13 , and a plug PG is formed in the contact hole CH 3 in the same steps as those in FIG. 15 and FIG. 16 .
  • the opening width of the contact hole CH 3 in the region 2 A does not have to be the same as the opening width of the contact hole CH 2 in the region 1 A, and can be set freely.
  • the field stop region NS, the collector region PC, and the collector electrode CE are formed on the back surface side of the semiconductor substrate SUB.
  • the back surface of the semiconductor substrate SUB is polished to reduce the thickness of the semiconductor substrate SUB.
  • the n-type field stop region NS and the p-type collector region PC are formed by performing the ion implantation from the back surface side of the semiconductor substrate SUB.
  • the collector electrode CE made of a metal film such as a titanium nitride film is formed by, for example, the sputtering method.
  • the structure shown in FIG. 2 and FIG. 3 can be obtained, and the semiconductor device 100 according to the first embodiment is manufactured.
  • a semiconductor device 100 according to the second embodiment will be described below with reference to FIG. 17 .
  • differences from the first embodiment will be mainly described, and descriptions of points overlapping with the first embodiment will be omitted.
  • the interlayer insulating film IL of the second embodiment further includes an insulating film IF 3 between the insulating film IF 1 and the insulating film IF 2 .
  • the insulating film IF 3 is a silicon oxide film containing phosphorus and is a PSG film.
  • the insulating film IF 1 of the second embodiment is a TEOS (Tetra Ethoxy Silane) film formed by the CVD method.
  • the thickness of the insulating film IF 1 is, for example, 60 to 100 angstroms ( ⁇ )
  • the thickness of the insulating film IF 3 is, for example, 1000 to 2000 angstroms ( ⁇ ).
  • the thickness of the insulating film IF 2 is larger than those of the insulating film IF 1 and the insulating film IF 3 , and is, for example, 6000 to 8000 angstroms ( ⁇ ).
  • the step of forming the insulating film IF 3 is performed between the step of forming the insulating film IF 1 in FIG. 8 and the step of forming the insulating film IF 2 in FIG. 9 .
  • the insulating film IF 3 is formed on the insulating film IF 1 by, for example, the CVD method.
  • the insulating film IF 2 is formed on the insulating film IF 3 .
  • the isotropic etching process of FIG. 13 is performed also to the insulating film IF 3 . Consequently, the second contact hole CH 2 is formed also in the insulating film IF 3 .
  • the thickness of the insulating film IF 2 is increased such that the insulating film IF 2 serves as a major part of the interlayer insulating film IL, and the same effect as that of the first embodiment can be obtained also in the second embodiment.
  • the insulating film IF 1 is formed by the thermal oxidation method in the first embodiment. Therefore, the gate insulating film GI is likely to be re-oxidized and thickened in the vicinity of the upper portion of the trench TR. As a result, the problem that the threshold voltage varies is likely to occur.
  • the insulating film IF 1 is formed by the CVD method. Therefore, the second embodiment has the advantage that the above problem is less likely to occur.
  • the film quality of the CVD film is coarser than the film quality of the thermal oxide film. Accordingly, if the thickness of the insulating film IF 1 is set to approximately 60 to 100 angstroms ( ⁇ ), there is a possibility that the function of preventing the diffusion of phosphorus from the insulating film IF 2 is not sufficiently exerted. Therefore, the diffusion of phosphorus can be prevented by forming the insulating film IF 3 between the insulating film IF 1 and the insulating film IF 2 .
  • a semiconductor device 100 according to the third embodiment will be described below with reference to FIG. 18 .
  • differences from the first embodiment will be mainly described, and descriptions of points overlapping with the first embodiment will be omitted.
  • the insulating film IF 1 is a part of the gate insulating film GI. Further, the thickness of the insulating film IF 1 formed on the semiconductor layer ND outside the trenches TR is smaller than the thickness of the gate insulating film GI formed inside the trenches TR. The thickness of the insulating film IF 1 is 100 to 500 angstroms ( ⁇ ) also in the third embodiment.
  • the isotropic etching process is performed to the gate insulating film GI formed on the semiconductor layer ND in the step in FIG. 7 .
  • the gate insulating film GI is completely removed in the first embodiment, the gate insulating film GI is left by reducing the thickness thereof in the third embodiment. This left gate insulating film GI serves as the insulating film IF 1 .
  • the manufacturing process can be simplified because the insulating film IF 1 does not have to be re-formed. Therefore, the third embodiment is superior to the first embodiment in that the manufacturing cost can be suppressed.
  • the thickness of the insulating film IF 1 is likely to vary.
  • the variation in the thickness of the insulating film IF 1 causes the variation in the implantation depth of the impurities in the subsequent ion implantation and the variation in the opening width of the second contact holes when forming the second contact holes. Therefore, the first embodiment is superior to the third embodiment in that the precision of the thickness of the insulating film IF 1 can be enhanced.
  • a semiconductor device 100 according to the fourth embodiment will be described below with reference to FIG. 19 .
  • differences from the first embodiment will be mainly described, and descriptions of points overlapping with the first embodiment will be omitted.
  • the step of FIG. 8 after forming the insulating film IF 1 , ion implantation using the insulating film IF 1 as a through film is performed to form the base region PB and the emitter region NE.
  • an insulating film IF 4 made of a silicon oxide film is formed on the semiconductor layer ND by, for example, the thermal oxidation method or the CVD method before ion implantation.
  • ion implantation using the insulating film IF 4 as a through film is performed.
  • the insulating film IF 4 is removed by the isotropic etching process.
  • the insulating film IF 1 is formed on the semiconductor layer ND.
  • the subsequent steps are the same as those in the first embodiment.
  • the ion implantation using the insulating film IF 1 as a through film is performed as in the first embodiment, there is a fear that the film quality of the insulating film IF 1 is deteriorated and the function of preventing diffusion of phosphorus from the insulating film IF 2 is degraded. Therefore, by using the insulating film IF 4 different from the insulating film IF 1 at the time of ion implantation as in the fourth embodiment, deterioration of the film quality of the insulating film IF 1 can be prevented.
  • an IGBT has been shown as an example of the device formed in the region 1 A, but the technique disclosed in the above embodiments can be applied not only to the IGBT but also to a power MOSFET having a vertical trench gate.

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