US20220115482A1 - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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Publication number
US20220115482A1
US20220115482A1 US17/262,306 US202017262306A US2022115482A1 US 20220115482 A1 US20220115482 A1 US 20220115482A1 US 202017262306 A US202017262306 A US 202017262306A US 2022115482 A1 US2022115482 A1 US 2022115482A1
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United States
Prior art keywords
pixels
sub
rows
electrically connected
gate
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US17/262,306
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English (en)
Inventor
Lulu Yang
Tinghua Shang
Yi Qu
Xiaofeng Jiang
Huijun Li
Mengqi WANG
Xin Zhang
Meng Zhang
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Assigned to BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIANG, XIAOFENG, LI, HUIJUN, QU, YI, SHANG, TINGHUA, WANG, MENGQI, YANG, Lulu, ZHANG, MENG, ZHANG, XIN
Publication of US20220115482A1 publication Critical patent/US20220115482A1/en
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    • H01L27/3276—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H01L27/3218—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel

Definitions

  • the present disclosure relates to the field of display technology, and in particular relates to an array substrate, a display panel, and a display device.
  • AMOLEDs Active matrix organic light-emitting diodes
  • the present disclosure provides an array substrate, a display panel, and a display device.
  • the technical solutions are as follows.
  • an array substrate includes:
  • a base substrate provided with a display area and a peripheral area surrounding the display area
  • a plurality of gate lines disposed in the display area and the peripheral area, the plurality of rows of first sub-pixels being electrically connected to the plurality of gate lines;
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit;
  • a first target line connected to a first row of the plurality of rows of first sub-pixels is electrically connected to a second gate drive circuit; and a second target line connected to a last row of the plurality of rows of first sub-pixels is electrically connected to a third gate drive circuit;
  • one of the first target line and the second target line is one of the plurality of gate lines, and the other target line is one of the plurality of reset signal lines.
  • the plurality of rows of first sub-pixels is electrically connected to the plurality of gate lines in one-to-one correspondence, and the plurality of rows of first sub-pixels is electrically connected to the plurality of reset signal lines in one-to-one correspondence.
  • a gate line electrically connected to an odd-numbered row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to an even-numbered row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit;
  • the first target line is one of the plurality of reset signal lines
  • the second target line is one of the plurality of gate lines.
  • a reset signal line electrically connected to an odd-numbered row of the plurality of rows of first sub-pixels and a gate line electrically connected to an even-numbered row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit;
  • the first target line is one of the plurality of gate lines
  • the second target line is one of the plurality of reset signal lines.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels is connected to a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels and both are electrically connected to the same first gate drive circuit.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels is connected to a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels and both are electrically connected to the same first gate drive circuit by the gate line.
  • the array substrate includes:
  • the second gate drive circuit disposed in the peripheral area and on one side of the plurality of first gate drive circuits
  • the third gate drive circuit disposed in the peripheral area and on one side of the plurality of first gate drive circuits distal from the second gate drive circuit.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line connected to another row of first sub-pixels are electrically connected to two of the first gate drive circuits.
  • the two first gate drive circuits electrically connected to each two adjacent rows of the plurality of rows of first sub-pixels are oppositely disposed at two ends of the two adjacent rows of the plurality of rows of first sub-pixels.
  • the first target line electrically connected to the first row of the plurality of rows of first sub-pixels is electrically connected to two second gate drive circuits
  • the second target line electrically connected to the last row of the plurality of rows of first sub-pixels is electrically connected to two of the third gate drive circuits.
  • the array substrate further includes:
  • a plurality of light emission control signal lines disposed in the display area and the peripheral area, the plurality of rows of first sub-pixels being electrically connected to the plurality of light emission control signal lines in one-to-one correspondence.
  • a light emission control signal line electrically connected to each row of the plurality of rows of first sub-pixels is electrically connected to a light emission drive circuit, and the light emission drive circuits electrically connected to the light emission control signal lines electrically connected to the plurality of rows of first sub-pixels are different.
  • the light emission control signal lines electrically connected to the plurality of rows of first sub-pixels are electrically connected to the same light emission drive circuit, and the first sub-pixels electrically connected to the same light emission drive circuit are disposed in different rows.
  • the array substrate includes: the light emission drive circuit disposed in the peripheral area.
  • each of the first sub-pixels includes: a pixel circuit and a light-emitting unit electrically connected to the pixel circuit,
  • the pixel circuit is electrically connected to the gate line, the reset signal line, and the light-emitting unit, and the pixel circuit is configured to drive the light-emitting unit to emit light in response to a gate drive signal provided by the gate line and a reset signal provided by the reset signal line.
  • the pixel circuit is also electrically connected to the light emission control signal line;
  • the pixel circuit is configured to drive the light-emitting unit to emit light in response to the gate drive signal, the reset signal, and a light emission control signal provided by the light emission control signal line.
  • the array substrate further includes:
  • a display panel in another aspect, includes a packaging cover plate and an array substrate as described in the above aspect.
  • a display device in yet another aspect, includes a drive circuit and a display panel as described in the above aspect.
  • the drive circuit is electrically connected to the display panel.
  • the drive circuit is configured to drive the display panel. The operation of the display panel is described.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of yet another array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a first sub-pixel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another first sub-pixel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of partial layout of an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a partial layout of another array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • a row of non-luminous dummy sub-pixels adjacent to a first row of the plurality of rows of display sub-pixels is disposed at the top of the display area, that is, at the boundary of the display area, and a gate line is electrically connected to the row of dummy sub-pixels.
  • a reset signal line electrically connected to an odd-numbered row of the plurality of rows of display sub-pixels and a gate line electrically connected to an even-numbered row of the plurality of rows of display sub-pixels are electrically connected to the same gate drive circuit
  • a reset signal line electrically connected to the first row of the plurality of rows of display sub-pixels and a gate line electrically connected to dummy sub-pixels adjacent thereto may be electrically connected to the same gate drive circuit. Furthermore, it is ensured that the reset signal lines electrically connected to the plurality of rows of display sub-pixels are all in the same working environment.
  • signal lines other than the gate line are generally disposed to be electrically connected to the dummy sub-pixels. Accordingly, in order to ensure the working stability of the other signal lines electrically connected to the dummy sub-pixels, a DC signal terminal that provides a DC signal is disposed to be electrically connected to other signal lines.
  • An embodiment of the present disclosure provides an array substrate, which can not only ensure that the normal display is not affected, but also has fewer wiring, simpler design, and lower manufacturing cost.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure. As shown in FIG. 1 , the array substrate may include:
  • a base substrate 01 provided with a display area A 1 and a peripheral area A 2 surrounding the display area A 1 .
  • a plurality of rows of first sub-pixels are disposed in the display area A 1 .
  • the plurality of rows of first sub-pixels is luminous pixels.
  • a boundary of the plurality of rows of first sub-pixels is a boundary of the display area A 1 . That is, the display area A 1 is an outer edge contour of the plurality of rows of first sub-pixels.
  • N is an integer greater than zero. Since the first sub-pixel is a luminous pixel, the first sub-pixel may also be referred to as a display sub-pixel.
  • a plurality of gate lines (n gate lines GATE 1 to GATEn as shown in FIG. 1 ) are disposed in the display area A 1 and the peripheral area A 2 .
  • the plurality of rows of first sub-pixels may be electrically connected to the plurality of gate lines.
  • a plurality of reset signal lines (n reset signal lines RST 1 to RSTn as shown in FIG. 1 ) are disposed in the display area A 1 and the peripheral area A 2 .
  • the plurality of rows of first sub-pixels may be electrically connected to the plurality of reset signal lines.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels may be electrically connected to the same first gate drive circuit 10 .
  • a first target line connected to a first row of the plurality of rows of first sub-pixels may be electrically connected to a second gate drive circuit 20 .
  • a second target line connected to a last row of the plurality of rows of first sub-pixels may be electrically connected to a third gate drive circuit 30 .
  • One of the first target line and the second target line may be one of the plurality of gate lines, and the other target line may be one of the plurality of reset signal lines.
  • the first target line is a first reset signal line RST 1 among the plurality of reset signal lines.
  • the second target line L 2 is a last gate line GATEn among the plurality of gate lines.
  • a first row of first sub-pixels P 1 may be electrically connected to a first gate line GATE 1 and the first reset signal line RST 1 correspondingly.
  • a second row of first sub-pixels P 2 may be electrically connected to a second gate line GATE 2 and a second reset signal line RST 2 correspondingly.
  • a third row of first sub-pixels P 3 is electrically connected to a third gate line GATE 3 and a third reset signal line RST 3 correspondingly; and so on.
  • the gate line GATE 1 electrically connected to the first row of first sub-pixels P 1 and the reset signal line RST 2 electrically connected to the second row of first sub-pixels P 2 are electrically connected to the same first gate drive circuit 10 .
  • the gate line GATE 2 electrically connected to the second row of first sub-pixels P 2 and the reset signal line RST 3 electrically connected to the third row of first sub-pixels P 3 may be electrically connected to the same another first gate drive circuit 10 ; and so on, until a gate line GATE(n ⁇ 1) electrically connected to an (n ⁇ 1) th row of first sub-pixels P(n ⁇ 1) and a reset signal line RSTn electrically connected to an n th row of first sub-pixels Pn are electrically connected to the same last first gate drive circuit 10 .
  • the reset signal line RST 1 (i.e., the first target line) electrically connected to the first row of first sub-pixels P 1 may be electrically connected to the second gate drive circuit 20 .
  • the gate line GATEn (i.e., the second target line) electrically connected to the nth row of first sub-pixels Pn may be electrically connected to the third gate drive circuit 30 .
  • the reset signal lines electrically connected to different rows of first sub-pixels may be different.
  • the gate lines electrically connected to different rows of first sub-pixels, that is, the gate drive circuits electrically connected to different gate lines may be different.
  • the reset signal line RST 1 electrically connected to the first row of first sub-pixels P 1 is connected to the second gate drive circuit 20
  • the reset signal line RST 2 electrically connected to the second row of first sub-pixels P 2 is connected to one first gate drive circuit 10
  • the reset signal line RST 3 electrically connected to the third row of first sub-pixels P 3 is connected to another first gate drive circuit 10 , and so on.
  • the gate line GATE 1 electrically connected to the first row of first sub-pixels P 1 is connected to one first gate drive circuit 10
  • the gate line GATE 2 electrically connected to the second row of first sub-pixels P 2 is connected to another first gate drive circuit 10 , and the like.
  • the gate drive circuit may provide a signal to the first sub-pixel electrically connected to the signal line to drive the first sub-pixel to emit light.
  • the second gate drive circuit 20 may be controlled to output a reset signal to the first row of first sub-pixels P 1 by the reset signal line RST 1 electrically connected thereto to reset the first row of first sub-pixels P 1 .
  • the first one of the first gate drive circuits 10 is controlled to output a gate drive signal to the first row of first sub-pixels P 1 by the gate line GATE 1 electrically connected thereto to drive the first row of first sub-pixels P 1 to emit light.
  • the first one of the first gate drive circuits 10 may also output a reset signal to the second row of first sub-pixels P 2 by the reset signal line RST 2 electrically connected thereto, in order to reset the second row of first sub-pixels P 2 .
  • the second one of the first gate drive circuits 10 is controlled to output a gate drive signal to the second row of first sub-pixels P 2 by the gate line GATE 2 electrically connected thereto to drive the second row of first sub-pixels P 2 to emit light.
  • the second one of the first gate drive circuits 10 may also output a reset signal to the third row of first sub-pixels P 3 by the reset signal line RST 3 electrically connected thereto, in order to reset the third row of first sub-pixels P 3 , and so on.
  • the driving of other rows will not be repeated.
  • the embodiment of the present disclosure provides an array substrate.
  • each gate drive circuit may be flexibly controlled to provide a signal to a signal line electrically connected thereto to realize reliable progressive driving of the first sub-pixels.
  • the array substrate can not only display normally, but also has a simpler design.
  • the plurality of rows of first sub-pixels may be electrically connected to the plurality of gate lines in one-to-one correspondence.
  • the plurality of rows of first sub-pixels may be electrically connected to the plurality of reset signal lines in one-to-one correspondence.
  • Each gate drive circuit i.e., the second gate drive circuit 20 , the first gate drive circuits 10 and the third gate drive circuit 30
  • each gate drive circuit may be disposed outside the array substrate independently of the array substrate.
  • each gate drive circuit may also be disposed on the array substrate. That is, as shown in FIG. 2 , the array substrate may further include:
  • each gate drive circuit may also be referred to as a gate on array (GOA) unit.
  • GAA gate on array
  • each gate drive circuit is disposed on the array substrate as an example for description.
  • FIG. 2 and the figures involved in the following embodiments all use GOA 1 to represent the first gate drive circuit 10 , GOA 2 to represent the second gate drive circuit 20 , and GOA 3 to represent the third gate drive circuit 30 .
  • the second gate drive circuit 20 , the first gate drive circuits 10 , and the third gate drive circuit 30 may be disposed on the array substrate in order along an extension direction perpendicular to the gate lines.
  • each two adjacent gate drive circuits may be cascaded (not shown), and activated sequentially in the cascaded sequence.
  • a circuit composed of the second gate drive circuit 20 , the first gate drive circuits 10 and the third gate drive circuit 30 may be referred to as a gate drive device.
  • the gate drive device may start to work sequentially from the second gate drive circuit 20 . That is, the gate drive device may start driving the plurality of rows of first sub-pixels included in the array substrate from the first row of the plurality of rows of first sub-pixels progressively.
  • This scanning method may also be referred to as forward scanning.
  • the gate drive device may also start to work sequentially from the third gate drive circuit 30 . That is, the gate drive device may start driving the plurality of rows of first sub-pixels included in the array substrate from the last row of the plurality of rows of first sub-pixels progressively.
  • This scanning method may also be referred to as reverse scanning
  • the second gate drive circuit 20 needs to be electrically connected to the reset signal line electrically connected to the first row of the plurality of rows of first sub-pixels.
  • the third gate drive circuit 30 needs to be electrically connected to the reset signal line electrically connected to the last row of the plurality of rows of first sub-pixels.
  • a gate line electrically connected to an odd-numbered row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to an even-numbered row of the plurality of rows of first sub-pixels may be electrically connected to the same first gate drive circuit 10 .
  • the first target line may be one of the plurality of reset signal lines (RST 1 shown in FIG. 1 ).
  • the second target line may be one of the plurality of gate lines (GATEn as shown in FIG. 1 ).
  • the gate drive device can realize progressive driving of the rows of first sub-pixels by forward scanning.
  • the gate drive device can realize progressive driving of the rows of first sub-pixels by forward scanning.
  • the headspace is effectively saved under the premise of ensuring normal display.
  • no dummy sub-pixels are provided, there is no need to provide signal lines electrically connected to the dummy sub-pixels in the array substrate, which simplifies the wiring.
  • a reset signal line electrically connected to an odd-numbered row of the plurality of rows of first sub-pixels and a gate line electrically connected to an even-numbered row of the plurality of rows of first sub-pixels may be electrically connected to the same first gate drive circuit 10 .
  • the first target line may be one of the plurality of gate lines (GATE 1 shown in FIG. 2 ).
  • the second target line may be one of the plurality of reset signal lines (RSTn shown in FIG. 2 ).
  • FIG. 2 continues to illustrate an array substrate including n rows of first sub-pixels P 1 to Pn, n gate lines GATE 1 to GATEn, and n reset signal lines RST 1 to RSTn as an example.
  • the reset signal line RST 1 electrically connected to the first row of first sub-pixels P 1 and the gate line GATE 2 electrically connected to the second row of first sub-pixels P 2 are electrically connected to the same first gate drive circuit 10 (i.e., the first GOA 1 shown in FIG. 2 ).
  • the reset signal line RST 2 electrically connected to the second row of first sub-pixels P 2 and the gate line GATE 3 electrically connected to the third row of first sub-pixels P 3 may be electrically connected to the same another first gate drive circuit 10 (i.e., the second GOA 1 shown in FIG. 2 ); and so on, until the reset signal line RST(n ⁇ 1) electrically connected to the (n ⁇ 1) th row of first sub-pixels P(n ⁇ 1) and the gate line GATEn electrically connected to the n th row of first sub-pixels Pn are electrically connected to the same last first gate drive circuit 10 (i.e., the last GOA 1 shown in FIG. 2 ).
  • the gate line GATE 1 electrically connected to the first row of first sub-pixels P 1 may be electrically connected to the second gate drive circuit 20 (i.e., GOA 2 shown in FIG. 2 ).
  • the reset signal line RSTn electrically connected to the n th row of first sub-pixels Pn may be electrically connected to the third gate drive circuit 30 (i.e., GOA 3 shown in FIG. 2 ).
  • the gate drive device can realize progressive driving of the rows of first sub-pixels by reverse scanning.
  • FIG. 1 and FIG. 2 show that in each two adjacent rows of the plurality of rows of first sub-pixels, a reset signal line electrically connected to one row of the plurality of rows of first sub-pixels and a gate line electrically connected to another row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit 10 as an example for description.
  • FIG. 3 shows another array substrate.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels included in an array substrate 100 may be electrically connected to the same first gate drive circuit 10 .
  • the gate line electrically connected to one row of the plurality of rows of first sub-pixels is connected to the reset signal line electrically connected to another row of the plurality of rows of first sub-pixels, they may be electrically connected to the same first gate drive circuit 10 by the gate line or the reset signal line.
  • the gate line GATE 1 electrically connected to the first row of first sub-pixels P 1 and the reset signal line RST 2 electrically connected to the second row of first sub-pixels P 2 may be electrically connected to the first one of the first gate drive circuits 10 (i.e., the first GOA 1 shown in FIG. 3 ) by the gate line GATE 1 .
  • the gate line GATE 2 electrically connected to the second row of first sub-pixels P 2 may be electrically connected to the reset signal line RST 3 electrically connected to the third row of first sub-pixels P 3 , and they may both be electrically connected to the second one of the first gate drive circuits 10 (i.e., the second GOA 1 shown in FIG. 3 ) by the gate line GATE 2 ; and so on.
  • a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels may be only electrically connected to the same first gate drive circuit 10 .
  • the gate line electrically connected to one row of the plurality of rows of first sub-pixels and the reset signal line electrically connected to another row of the plurality of rows of first sub-pixels may both be electrically connected to two first gate drive circuits 10 .
  • the two first gate drive circuits 10 electrically connected to each two adjacent rows of first sub-pixels may be oppositely disposed at two ends of two adjacent rows of the plurality of rows of first sub-pixels.
  • the first target line electrically connected to the first row of the plurality of rows of first sub-pixels may also be electrically connected to two second gate drive circuits 20 .
  • the second target line electrically connected to the last row of the plurality of rows of first sub-pixels may also be electrically connected to two third gate drive circuits 30 .
  • FIG. 4 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • the gate line GATE 1 electrically connected to the first row of first sub-pixels P 1 and the reset signal line RST 2 electrically connected to the second row of first sub-pixels P 2 may be both electrically connected to two first gate drive circuits 10 (i.e., the two GOA 1 s shown in FIG. 4 ) disposed on the left and right sides of the array substrate 100 .
  • the gate line GATE 2 electrically connected to the second row of first sub-pixels P 2 and the reset signal line RST 3 electrically connected to the third row of first sub-pixels P 3 may be electrically connected to two first gate drive circuits 10 (i.e., the other two GOA 1 s shown in FIG. 4 ) disposed on the left and right sides of the array substrate; and so on.
  • the reset signal line RST 1 electrically connected to the first row of first sub-pixels P 1 may be electrically connected to two second gate drive circuits 20 (i.e., the two GOA 2 s shown in FIG. 4 ) oppositely disposed on the left and right sides of the array substrate 100 .
  • the gate line GATEn electrically connected to the last row of first sub-pixels Pn may be electrically connected to two third gate drive circuits 30 (i.e., two GOA 3 shown in FIG. 4 ) oppositely disposed on the left and right sides of the array substrate 100 .
  • the two gate drive circuits may be controlled to provide signals to the row of the plurality of rows of first sub-pixels by the signal lines electrically connected thereto simultaneously to drive the row of the plurality of rows of first sub-pixels to emit light. Accordingly, it may be ensured that along the extension direction of the gate line, both one end and the other end of the row of the plurality of rows of first sub-pixels can emit light simultaneously, which improves the driving efficiency of driving each row of the plurality of rows of first sub-pixels. For an array substrate with a higher resolution (i.e., an array substrate with a larger number of first sub-pixels included in each row), the driving efficiency is improved significantly.
  • FIG. 5 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • the array substrate 100 may further include:
  • a plurality of light emission control signal lines (n light emission control signal lines EM 1 to EMn as shown in FIG. 5 ) disposed in the display area and the peripheral area (not shown in FIG. 5 ).
  • the plurality of rows of first sub-pixels (n rows of first sub-pixels P 1 to Pn as shown in FIG. 5 ) may be electrically connected to the plurality of light emission control signal lines (such as EM 1 to EMn) in one-to-one correspondence.
  • first row of first sub-pixels P 1 may be electrically connected to a first light emission control signal line EM 1 .
  • the second row of first sub-pixels P 2 may be electrically connected to a second light emission control signal line EM 2 .
  • the third row of first sub-pixels P 3 is electrically connected to a third light emission control signal line EM 3 ; and so on.
  • a light emission control signal line electrically connected to each row of the plurality of rows of first sub-pixels may be electrically connected to a light emission drive circuit 40 .
  • the light emission drive circuits 40 electrically connected to the light emission control signal lines electrically connected to the rows of first sub-pixels are different.
  • Each light emission drive circuit 40 may provide a light emission control signal to the light emission control signal line electrically connected thereto.
  • the first sub-pixel may emit light in response to the light emission control signal.
  • the light emission drive circuit may also be provided outside the array substrate independently of the array substrate, or the light emission drive circuit 40 may be disposed on the array substrate. That is, with respect to FIG. 5 , the array substrate 100 may include:
  • the light emission drive circuit 40 may also be referred to as an emission on array (EOA) control unit.
  • EOA emission on array
  • FIG. 5 the figures involved in the embodiments of the present disclosure all use EOA 40 to represent the light emission drive circuit 40 .
  • the light emission control signal lines electrically connected to the plurality of rows of first sub-pixels may be electrically connected to the same light emission drive circuit, and the first sub-pixels electrically connected to the same light emission drive circuit are disposed in different rows.
  • FIG. 6 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • every three adjacent rows of first sub-pixels may be electrically connected to the same light emission drive circuit (i.e., one EOA 40 shown in FIG. 6 ).
  • FIG. 6 also only takes the first row of first sub-pixels P 1 , the second row of first sub-pixels P 2 , and the third row of first sub-pixels P 3 as an example.
  • the light emission drive circuits 40 may also be disposed on the array substrate along the extension direction perpendicular to the gate line, and adjacent EOAs 40 may be cascaded. Accordingly, each light emission drive circuit may sequentially provide a signal to the light emission control signal line EM electrically connected thereto in the order of arrangement.
  • each row of the plurality of rows of first sub-pixels may include a plurality of first sub-pixels (each first sub-pixel is shown by a long square in FIGS. 1 to 6 ).
  • the plurality of first sub-pixels may include a red sub-pixel capable of emitting red color light, a green sub-pixel capable of emitting green color light, and a blue sub-pixel capable of emitting blue color light.
  • the structure of each first sub-pixel may be the same.
  • FIG. 7 shows a schematic structural diagram of a first sub-pixel according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of another first sub-pixel according to an embodiment of the present disclosure. It may be seen with reference to FIGS. 7 and 8 that the first sub-pixel may include a pixel circuit 01 and a light-emitting unit 02 electrically connected to the pixel circuit 01 .
  • the pixel circuit 01 may be electrically connected to the gate line GATE 1 , the reset signal line RST 1 , and the light-emitting unit 02 , respectively.
  • the pixel circuit 01 may drive the light-emitting unit 02 to emit light in response to a gate drive signal provided by the gate line GATE 1 and a reset signal provided by the reset signal line RST 1 .
  • the reset signal line RST 1 electrically connected to the pixel circuit 01 may first provide a reset signal to reset the pixel circuit 01 .
  • the gate line GATE 1 electrically connected to the pixel circuit 01 may provide a gate drive signal.
  • the reset signal line RST 1 no longer provides the reset signal, and the light-emitting unit 02 emits light in response to the gate drive signal.
  • the pixel circuit 01 may also be electrically connected to a data signal line that provides a data signal.
  • the gate line GATE 1 provides the gate drive signal
  • the data signal may be output to the light-emitting unit 02 to drive the light-emitting unit 02 to emit light.
  • the pixel circuit may also be electrically connected to the emission control signal line EM 1 . Accordingly, the pixel circuit 01 may also drive the light-emitting unit to emit light in response to the gate drive signal, the reset signal, and a light emission control signal provided by the light emission control signal line EM 1 .
  • the light emission control signal line may provide the light emission control signal to the pixel circuit after the gate line electrically connected thereto provides the gate drive signal to it. By disposing the light emission control signal line, the reliable driving of the light-emitting unit 02 may be ensured.
  • the pixel circuit according to the embodiments of the present disclosure may have a structure of 7T1C (i.e., including 7 transistors and 1 capacitor), or other structures, such as 9T2C (i.e., including 9 transistors and 2 capacitors).
  • 7T1C i.e., including 7 transistors and 1 capacitor
  • 9T2C i.e., including 9 transistors and 2 capacitors.
  • the embodiment of the present disclosure does not limit the specific structure of the pixel circuit.
  • FIG. 9 is a schematic diagram of a partial layout (left part) of an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a partial layout (right part) of an array substrate according to an embodiment of the present disclosure.
  • the reset signal line RST 1 electrically connected to the first row of the plurality of rows of first sub-pixels of the display area is electrically connected to the first one of the gate drive circuits;
  • the light emission control signal line EM 1 electrically connected to the first row of the plurality of rows of first sub-pixels is electrically connected to the first one of the light emission drive circuits;
  • the gate line GATE 1 electrically connected to the first row of the plurality of rows of first sub-pixels and the reset signal line RST 2 electrically connected to the second row of the plurality of rows of first sub-pixels are electrically connected to the same gate drive circuit. The same applies to other lines, which will not be repeated here.
  • the array substrate may also include a plurality of rows of second sub-pixels P 0 that are not electrically connected to any signal lines disposed in the peripheral area (not shown in FIGS. 9 and 10 ) and on one side of the second gate drive circuit 20 distal from the first gate drive circuit 10 .
  • the plurality of rows of second sub-pixels P 0 may be non-luminous pixels. Since the second sub-pixel P 0 does not emit light, the second sub-pixel P 0 may also be referred to as a dummy sub-pixel.
  • the embodiment of the present disclosure provides an array substrate.
  • each gate drive circuit may be flexibly controlled to provide a signal to a signal line electrically connected thereto to realize reliable progressive driving of the first sub-pixels.
  • the array substrate can not only display normally, but also has a simpler design.
  • FIG. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include an encapsulation cover plate 200 and an array substrate 100 as shown in FIGS. 1 to 6, 9 and 10 .
  • FIG. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include a drive circuit 001 and a display panel 002 as shown in FIG. 11 .
  • the drive circuit 001 may be electrically connected to the display panel 002 .
  • the drive circuit 001 may be configured to drive the display panel to operate.
  • the drive circuit may be a source drive circuit.
  • the display device may be an AMOLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • a and/or B may represent: A alone exists, A and B exist simultaneously, and B alone exists.
  • the character “I” generally indicates that the associated objects are in an “or” relationship.
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