US20200058827A1 - Near-Ultraviolet Light-Emitting Semiconductor Light-Emitting Element And Group III Nitride Semiconductor Template Used Therefor - Google Patents

Near-Ultraviolet Light-Emitting Semiconductor Light-Emitting Element And Group III Nitride Semiconductor Template Used Therefor Download PDF

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US20200058827A1
US20200058827A1 US16/083,618 US201716083618A US2020058827A1 US 20200058827 A1 US20200058827 A1 US 20200058827A1 US 201716083618 A US201716083618 A US 201716083618A US 2020058827 A1 US2020058827 A1 US 2020058827A1
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group iii
iii nitride
layer
nitride semiconductor
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Sung Min Hwang
In Sung Cho
Won Taeg Lim
Doo Soo Kim
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SOFT-EPI Inc
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials

Definitions

  • the present disclosure relates generally to a near-ultraviolet (UV) light emitting semiconductor device and a Group III nitride semiconductor template used therefor. More particularly, it relates to a near-ultraviolet light emitting semiconductor device using AlGaN, and a Group III nitride semiconductor template used therefor.
  • UV near-ultraviolet
  • semiconductor light emitting device is intended to indicate a semiconductor optoelectronic device which generates light by electron-hole recombination.
  • Group III-nitride semiconductor light emitting device in which the Group III-nitride semiconductor includes a compound containing Al(x)Ga(y)In(1-x-y)N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1) and may also contain impurities such as Si, Mg, etc.
  • FIG. 1 is a diagrammatic representation illustrating a method for growing a Group III nitride semiconductor layer described in U.S. Pat. No. 5,290,393.
  • a Al x Ga 1-x N (x ⁇ 0) nucleation layer 20 followed by a Group III nitride, Al y Ga 1-y N (y ⁇ 0), semiconductor layer 21 are grown on a growth substrate 10 .
  • a GaN nucleation layer 20 is formed at a temperature of 500° C.
  • a Group III nitride, GaN semiconductor layer 21 is next formed at a temperature of 1020° C.
  • FIG. 2 illustrates a Group III nitride semiconductor light emitting device described in U.S. Pat. No. 7,759,140, in which the semiconductor light emitting device includes a growth substrate 10 , a nucleation layer (not shown), an n-type Group III nitride semiconductor layer 30 (e.g. Si-doped GN), an active layer 40 (e.g. InGaN/(In)/GaN multiple quantum well structure) for generating light by electron-hole recombination, a p-type Group III nitride semiconductor layer 50 (e.g. Mg-doped GaN), a p-side electrode 70 , and an n-side electrode 80 .
  • the semiconductor light emitting device includes a growth substrate 10 , a nucleation layer (not shown), an n-type Group III nitride semiconductor layer 30 (e.g. Si-doped GN), an active layer 40 (e.g. InGaN/(In)/GaN
  • the nucleation layer, the n-type Group III nitride semiconductor layer 30 , and the p-type Group III nitride semiconductor layer 50 are based on GaN.
  • the growth substrate 10 e.g. a C-plane sapphire substrate
  • This type of growth substrate is called a PSS (Patterned Sapphire Substrate).
  • UVA from 315 to 400 nm
  • UVB from 280 to 315 nm
  • UVC from 100 to 280 nm.
  • UVA from 315 to 400 nm
  • UVB from 280 to 315 nm
  • UVC from 100 to 280 nm.
  • the UV region from 300 to 400 will be the main target.
  • This problem could be resolved by minimizing the content of GaN during the manufacture of a near-ultraviolet light emitting Group III nitride semiconductor device. Nevertheless, as discussed earlier in relation to FIG. 1 , it is generally hard to grow a high-quality, Al-based Group III nitride semiconductor layer 21 on the side of the growth substrate 10 .
  • a high-quality, GaN-based Group III nitride semiconductor layer 21 is grown on the side abutting against the growth substrate 10 , and subsequently a near-ultraviolet light emitting Group III nitride semiconductor structure is grown on the semiconductor layer 21 . Later, the growth substrate 10 and the GaN-based Group III nitride semiconductor layer 21 are removed. This type of semiconductor light emitting device with the growth substrate 10 removed is called a vertical chip.
  • U.S. Pat. No. 7,759,246 also mentioned that it is not easy to grow a high-quality Al-based layer on the growth substrate by pointing out that the growth speed gets slower by an increase in the Al content, and a layer with a higher Al content is under more stress (e.g. a thick AlGaN layer is likely subject to cracking).
  • an ultraviolet light emitting epitaxial structure is grown on a GaN-based layer, which is later used as a sacrificial layer and removed together with the growth substrate.
  • a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device including: a growth substrate; a nucleation layer based on Al x Ga 1-x N (0 ⁇ x ⁇ 1, x>y); and a monocrystalline Group III nitride semiconductor layer based on Al y Ga 1-y N (y>0).
  • a 300-400 nm near-ultraviolet light emitting semiconductor device including: a growth substrate; a nucleation layer based on Al x Ga 1-x N (0 ⁇ x ⁇ 1, x>y); a monocrystalline Group III nitride semiconductor layer based on Al y Ga 1-y N (y>0); a light emitting structure arranged above the Group III nitride semiconductor layer, for emitting near-ultraviolet light through electron-hole recombination; and a first and a second electrodes supplying electrons and holes to the light emitting structure, in which Al composition value y in the Group III nitride semiconductor layer is determined, so as to prevent the Group III nitride semiconductor layer from absorbing the near-ultraviolet light emitted from the light emitting structure.
  • FIG. 1 is a diagrammatic representation illustrating a method for growing a Group III nitride semiconductor layer described in U.S. Pat. No. 5,290,393.
  • FIG. 2 illustrates a Group III nitride semiconductor light emitting device described in U.S. Pat. No. 7,759,140.
  • FIG. 3 illustrates an exemplary embodiment of a Group III nitride semiconductor template according to the present disclosure.
  • FIG. 4 is a diagrammatic representation illustrating a method for manufacturing a Group III nitride semiconductor template according to the present disclosure.
  • FIG. 5 illustrates another exemplary embodiment of a Group III nitride semiconductor template according to the present disclosure.
  • FIG. 6 is a photo showing crystal defects detected in the Group III nitride semiconductor layer, caused by unsuccessful growth on uneven (protruded and depressed) portions.
  • FIG. 7 shows test results on a Group III nitride semiconductor template that is manufactured according to the present disclosure.
  • FIG. 8 illustrates an exemplary embodiment of a near-ultraviolet light emitting semiconductor device according to the present disclosure.
  • FIG. 9 illustrates another exemplary embodiment of a near-ultraviolet light emitting semiconductor device according to the present disclosure.
  • FIG. 10 shows test results of the near-ultraviolet light emitting semiconductor device of FIG. 9 , using an integrating sphere.
  • FIG. 3 illustrates an exemplary embodiment of a Group III nitride semiconductor template according to the present disclosure, in which the template includes a growth substrate 10 , a nucleation layer 20 , and a Group III nitride semiconductor layer 21 .
  • the growth substrate 10 is generally formed of a material different from the Group III nitride semiconductor layer 21 .
  • it can be a sapphire (Al 2 O 3 ) substrate, and the nucleation layer 20 and the Group III nitride semiconductor layer 21 are usually grown on the C plane of the sapphire substrate.
  • the nucleation layer 20 is introduced for crystal growth of the Group III nitride semiconductor layer 21 on the growth substrate 10 based on a hetero-material. It can be formed of Al x Ga 1-x N (0 ⁇ x ⁇ 1) for example, and grown at a temperature lower than the growth temperature of the Group III nitride semiconductor layer 21 in general. A higher Al content may reduce absorption of light generated by the active layer. In this regard, AlN would be most recommended.
  • the Group III nitride semiconductor layer is formed of Al y Ga 1-y N (y>0), and preferably has a band gap energy range for not absorbing the light emitted from a light emitting structure to be grown on its top. For instance, in case of 365 nm near-ultraviolet light emission, the Group III nitride semiconductor layer may be formed of Al 0.05 Ga 0.95 N. Although the band gap energy increases by a higher Al content, the crystallinity of the Group III nitride semiconductor layer 21 is adversely affected by such a high Al content, as mentioned above.
  • the content of Al should preferably be determined in a way that the Group III nitride semiconductor layer 21 would not absorb the light being emitted and at the same time, its crystallinity may be minimally impaired.
  • the Group III nitride semiconductor layer 21 may contain a dopant (e.g. Si, Mg or the like) or In as its components, it is not recommended for the crystallinity.
  • FIG. 4 is a diagrammatic representation illustrating a method for manufacturing a Group III nitride semiconductor template according to the present disclosure.
  • the growth substrate 10 undergoes a typical pretreatment such as cleansing, and a nucleation layer 20 is then grown thereon at a first temperature.
  • the Group III nitride semiconductor layer 21 is grown at a second temperature that is higher than the first temperature.
  • the nucleation layer 20 is crystallized at a third temperature that is higher than the first temperature and lower than the second temperature.
  • the nucleation layer 20 and the Group III nitride semiconductor layer 21 are grown by means of a MOCVD system.
  • the growth of the nucleation layer 20 takes place at a low temperature (first temperature) where thermos-dynamical effects on molecular elements of the nucleation layer 20 (i.e., Al, N, Ga) are minimal while gas flow in the physical source injection and reactor of an epitaxial growth system (e.g. MOCVD system) has a stronger influence on the growth.
  • a uniform physical deposition can be realized on the growth substrate 10 if the reactor is tuned at a low temperature zone with a high degree of uniformity for source deposition.
  • the Al x Ga 1-x N (0 ⁇ x ⁇ 1) nucleation layer 20 grown at the low, first temperature is a polycrystalline film based on a mixture of AlN and GaN, and their combination ratio can be adjusted to the composition ratio of Al in the Group III nitride semiconductor layer 21 to be grown on the nucleation layer 20 . This is done so that a lattice constant of the nucleation layer 20 conforms to the lattice constant of the Group III nitride semiconductor layer 21 .
  • this conformity of lattice constants is not necessarily advantageous for the crystallinity of the Group III nitride semiconductor layer 21 because the nucleation layer 20 is polycrystalline.
  • the crystal growth mode can be modified by varying the combination ratio of AlN and GaN. That is, if the content of AlN is higher it is modified to ‘3D-like crystal growth mode, and if the content of GaN is higher, it is modified to the ‘2D-like crystal growth mode’. Therefore, with adjustment of the combination ratio, the Group III nitride semiconductor layer 21 may have an optimized quality of crystals.
  • the nucleation layer 20 which is a polycrystalline film, is usually crystallized while it is being warmed up to and/or has reached to the growth temperature (second temperature) of the Group III nitride semiconductor layer 21 . During this process, it is possible to change the crystal growth mode of the nucleation layer 20 . According to the present disclosure, the nucleation layer 20 grown is crystallized while it is being warmed up to and/or has reached to a temperature (third temperature) higher than the second temperature. In this way, not only the nucleation layer 20 can be crystallized, but the Group III nitride semiconductor layer 21 may have an additionally improved crystallinity.
  • the second temperature is still suitable for crystal growth of the Group III nitride semiconductor layer 21 that is a monocrystalline film.
  • the nucleation layer 20 to be crystallized at the third temperature i.e. for the nucleation layer 20 to maintain thermo-dynamical stability at the third temperature
  • it is preferably formed of materials that are thermodynamically stable at around the third temperature.
  • materials that are thermodynamically stable at around the third temperature.
  • they preferably should have a high Al composition ratio therein.
  • the nucleation layer 20 based on Al x Ga 1-x N (0 ⁇ x ⁇ 1) has the x value greater than 0.05.
  • the nucleation layer 20 is re-crystallized at the third temperature and provides a structure that would minimize the density of defective crystals due to the non-conformity of lattice constants during the growth at the second temperature.
  • a suitable composition ratio of Al is required.
  • the x value in Al x Ga 1-x N (0 ⁇ x1) should preferably be at least 0.5. In other words, if the x value is approximate to 1, the thermo-dynamical stability of the nucleation layer 20 at the third temperature is increased, and a 3D island growth mode is activated, creating conditions for a lateral growth mode, i.e. in parallel to the surface of the growth substrate 10 during the growth at the second temperature.
  • composition ratio of Al is too high, 3D island density gets also increased such that sufficient coalescing may not take place on the growth surface during the growth at the second temperature and it can be very difficult to obtain a smooth growth surface.
  • thickness is another important process parameter for the nucleation layer 20 .
  • the thickness of the nucleation layer 20 growing at the first temperature is crucial for determining height of SD islands to be formed at the third temperature.
  • a preferable empirical range of the thickness is between 10 and 100 nm. If the thickness is too small, the height of 3D islands will not be sufficient to give rise to good effects; if the thickness is too great, the 3D islands thus formed will be too high to produce a sufficiently smooth, even surface.
  • the nucleation layer 20 preferably has a thickness ranging from 10 to 100 nm, the Al composition ratio between 50 and 100%, and the growth temperature ranging from 400 to 600° C. prevailing in surface kinetics limited conditions. Meanwhile, growth pressure is generally not a crucial process parameter in the formation of the nucleation layer 20 .
  • the nucleation layer 20 can be grown at various pressures ranging from 100 to 760 torr.
  • MO source or carrier gas flow may be determined according to optimal MOCVD conditions to be used.
  • the third temperature is preferably higher than the second temperature by 10 to 300° C. Since the second temperature is usually between 1000 and 1100° C., the third temperature will be between 1010 and 1400° C.
  • the range of an optimal temperature varies by the thickness and Al composition ratio of the nucleation layer 20 . As the thickness and Al composition rate are increased, the optimal temperature is set higher.
  • shape and size of the 3D islands are determined. If it is set too high, thermos-dynamical stability on the nucleation layer 20 will be deteriorated, causing surface desorption.
  • the shape and size of the 3D islands are also affected by duration of the third temperature and an amount of time required for elevating the first temperature to the third temperature. Since optimization of these parameters is subject to commonly used conditions of the reactor (MO source, V/Ill ratio, pressure of the reactor, etc.), it is desirable to modify them accordingly, instead of giving fixed values for all.
  • the Al composition ratio or value in the Group III nitride semiconductor layer 21 based on Al y Ga 1-y N is preferably smaller than the Al composition ratio x in the nucleation layer 20 based on Al x Ga 1-x N (0 ⁇ x ⁇ 1). In that way, 3D islands that are formed from the nucleation layer 20 going through the process in the third temperature range will produce a smooth epitaxial layer when the growth mode is turned into the 2D growth mode for the Group III nitride semiconductor layer 21 in the second temperature range. In general, the 2D growth mode becomes dominant as the Al composition ratio is small.
  • the Group III nitride semiconductor layer 21 should preferably have the smallest possible Al composition ratio, yet its largest Al composition ratio should preferably be smaller than the Al composition ratio in the nucleation layer 20 .
  • This Group III nitride semiconductor layer 21 corresponds to a so-called buffer layer in the fabrication of a semiconductor device, and preferably has a thickness of 1 to 6 ⁇ m. If it is too thin, it may not be as effective as the buffer layer. Moreover, if it is too thick, due to the non-conformity of lattice constants between the growth substrate 10 and the Group III nitride semiconductor layer, more wafer bowing will be observed.
  • a relatively low pressure between 50 and 200 torr is normally used for the reactor during the growth of Al 0.05 Ga 0.95 N. This will increase the speed of carrier gas so that TMAl used may be prevented from actively getting involved in a parasitic reaction with NH 3 in atmospheric condition.
  • the growth temperature used is typically in a range from 1000 to 1100° C., which is similar to the growth temperature of GaN or within a higher growth temperature zone by 10 to 50° C. In this way, surface mobility is enhanced and therefore, an Al precursor adsorbed on the growth surface can find its growth kink site better.
  • the V/Ill ratio which is a ratio between MO source flow and NH 3 , varies by the type of a reactor used and the purpose of growth and therefore, it is preferably adapted to optimal conditions for each reactor.
  • the Group III nitride semiconductor layer 21 is typically grown at a speed between 1 and 4 ⁇ m/h. In general, crystallinity is improved as the growth speed is slowed down, and vice versa. However, if the speed is too slow, growth efficiency is lowered.
  • FIG. 5 illustrates another exemplary embodiment of a Group III nitride semiconductor template according to the present disclosure.
  • the template includes a growth substrate 10 , a nucleation layer 20 , and a Group III nitride semiconductor layer 21 .
  • the growth substrate 10 has protruded and depressed portions 11 for scattering light. As shown, in the protruded and depressed portions 11 , the protruded portion is formed of bumps created by etching the growth substrate 10 and the depressed portion is formed of an etch-exposed bottom surface of the growth substrate 10 . Alternatively, the depressed portion may be formed by etching the growth substrate 10 and the protruded portion may be formed of the remaining, non-etched surface of the growth substrate 10 . Further, a combination of these two is also applicable. In general, however, the protruded portion is preferably formed by etching the growth substrate 10 .
  • the protruded portion 11 may be formed in a semi-spherical lens shape, for example, and have a width of 1.5 to 3 ⁇ m and a height of 1 to 2 ⁇ m.
  • this templet having protruded and depressed portions requires a higher level of technology for growing the Group III nitride semiconductor layer 21 based on Al y Ga 1-y N (y>0) because it is not easy for the Group III nitride semiconductor layer 21 grown from the bottom surface of the growth substrate 10 to securely cover the protrude and depressed portions as well as coalesce each other.
  • FIG. 6 illustrates an example of crystal defects detected in the Group III nitride semiconductor layer 21 , caused by unsuccessful growth on the protruded and depressed portions.
  • the present disclosure addressed the problem mentioned above by dividing the Group III nitride semiconductor layer 21 into a first layer 22 , a second layer 23 and a third layer 24 .
  • the nucleation layer 20 is formed and the first layer 22 is then grown under conditions that promote vertical growth. For instance, the first layer 22 is formed until it reaches to 80 to 90% of the height of the protruded portion.
  • the second layer 23 is grown under conditions that promote lateral growth for covering the protruded portion, and at the same time, the second layer 23 is encouraged to coalesce well.
  • the third layer 24 is formed under conditions that promote the formation of a flat layer, i.e., in 2D growth mode.
  • FIG. 7 shows test results on a Group III nitride semiconductor template that is manufactured according to the present disclosure.
  • an average value is 352 nm, meaning that the Al composition ratio in the Group III nitride semiconductor layer 21 is approximately 5%.
  • the wavelength uniformity is as good as 2% or lower.
  • the template has an average thickness of 6 ⁇ m and its thickness uniformity is again as good as 3% or lower.
  • XRD X-ray diffraction
  • the first layer 22 is a connecting layer to the nucleation layer 20 and a Group III metal-rich surface suitable for c-axis oriented growth. This is not far from the typical growth conditions of high-crystalline Group III nitride semiconductors, but the V/Ill ratio should preferably be greater than 500.
  • the subsequently growing second layer 23 is a coalescing layer strongly under the 2D growth mode. In this layer, growth surfaces approaching each other in the lateral direction along the semi-spherical lens surface meet each other. Since different growth surfaces have different dangling bond structures thereon, there is still a need for finding optimal conditions for smooth connection.
  • a growth layer of a low-temperature zone for making the second layer less sensitive to crystal structure orientation of the growth surface, and 2) an ultimately reduced growth speed for allowing well-regularized coalesce.
  • this growth layer of a low-temperature zone is grown at a temperature lower than the third layer 24 by 20 to 100° C. and at a growth speed ranging from 0.1 to 1 ⁇ m/h.
  • a valid parameter in the growth conditions for the second layer 23 is growth pressure. In general, a higher pressure is advantageous for smooth coalescing.
  • the third layer 24 can be grown under conventional growth conditions for the high-crystalline Group III nitride semiconductor layer.
  • FIG. 8 illustrates an exemplary embodiment of a near-ultraviolet light emitting semiconductor device according to the present disclosure, in which the semiconductor light emitting device includes a growth substrate 10 , a nucleation layer 20 , a Group III nitride semiconductor layer 21 , a first semiconductor layer having a first conductivity 30 (e.g. n-type AlGaN layer), an active layer 40 (e.g. InGaN multiple quantum well structure) for generating near-ultraviolet light by electron-hole recombination, a second semiconductor layer 50 (e.g. p-type AlGaN layer) having a second conductivity different from the first conductivity, a first electrode 80 (e.g.
  • a first electrode 80 e.g.
  • the growth substrate 10 has protruded and depressed portions 11 , and a transparent current spreading electrode 60 (e.g. ITO) is usually provided almost across the entire surface of the second semiconductor layer 50 for current spreading between the second semiconductor layer 50 and the second electrode 70 .
  • a transparent current spreading electrode 60 e.g. ITO
  • the first semiconductor layer 30 and the second semiconductor layer 50 each can have a plurality of layers.
  • the second semiconductor layer 50 may have an electron blocking layer with a high Al composition ratio adjacent to the active layer 40 .
  • these two semiconductor layers can switch their conductivities with each other.
  • the first semiconductor layer 30 , the active layer 40 and the second semiconductor layer 50 constitute a so-called light emitting structure.
  • FIG. 9 illustrates another exemplary embodiment of a near-ultraviolet light emitting semiconductor device according to the present disclosure.
  • this device does not have the transparent current spreading electrode 60 , and the second electrode 70 (e.g. Ag/Ni/Au or Al/Ni/Au) is formed almost across the entire surface of the second semiconductor layer 50 .
  • the second electrode 70 serves as a bonding pad as well as a reflective film for reflecting near-ultraviolet light generated from the active layer 40 towards the growth substrate 10 .
  • transparent current spreading electrode 60 may additionally be provided.
  • the second electrode 70 may be designed to serve only as a bonding pad, and a DBR may be provided between the second electrode 70 and the second semiconductor layer 50 . This type of a chip is called a flip chip.
  • FIG. 10 shows test results of the near-ultraviolet light emitting semiconductor device of FIG. 9 , using an integrating sphere.
  • the integration sphere test results reveal that the semiconductor light emitting device according to the present disclosure exhibits behavioral characteristics similar to those of commercially available vertical semiconductor light emitting devices that emit 365 nm wavelength light, and 3 to 4 times higher optical output than flip chips that include GaN at the lower portion.
  • a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device comprising: a growth substrate; a nucleation layer based on Al x Ga 1-x N (0 ⁇ x ⁇ 1, x>y); and a monocrystalline Group III nitride semiconductor layer based on Al y Ga 1-y N (y>0).
  • the Group III nitride semiconductor template for a near-ultraviolet light emitting semiconductor device wherein the growth substrate comprises protruded and depressed portions for scattering light, and the Group III nitride semiconductor layer is adapted to cover the protruded and depressed portions.
  • the Group III nitride semiconductor template for a near-ultraviolet light emitting semiconductor device wherein the Group III nitride semiconductor layer comprises a first layer growing from the nucleation layer, a second layer covering the first layer and being coalesced together from above, and a third layer flat on top of the second layer.
  • a 300-400 nm near-ultraviolet light emitting semiconductor device comprising: a growth substrate; a nucleation layer based on Al x Ga 1-x N (0 ⁇ x ⁇ 1, x>y); a monocrystalline Group III nitride semiconductor layer based on Al y Ga 1-y N (y>0); a light emitting structure arranged above the Group III nitride semiconductor layer, for emitting near-ultraviolet light through electron-hole recombination; and a first and a second electrodes supplying electrons and holes to the light emitting structure, wherein Al composition value y in the Group III nitride semiconductor layer is determined, so as to prevent the Group III nitride semiconductor layer from absorbing the near-ultraviolet light emitted from the light emitting structure.
  • the near-ultraviolet light emitting semiconductor device wherein the growth substrate comprises protruded and depressed portions for scattering the near-ultraviolet light emitted from the light emitting structure.
  • the near-ultraviolet light emitting semiconductor device wherein the Group III nitride semiconductor layer covers the protruded and depressed portions, and the Group III nitride semiconductor layer comprises a first layer growing from the nucleation layer, a second layer covering the first layer and being coalesced together from above, and a third layer flat on top of the second layer.
  • any of the near-ultraviolet light emitting semiconductor devices and any of the Group III nitride semiconductor templates used therefor according to the present disclosure can be suitable for obtaining commercially available near-ultraviolet light emitting semiconductor devices and Group III nitride semiconductor templates.

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