US20190385563A1 - Display device and driving method thereof - Google Patents

Display device and driving method thereof Download PDF

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Publication number
US20190385563A1
US20190385563A1 US16/489,590 US201816489590A US2019385563A1 US 20190385563 A1 US20190385563 A1 US 20190385563A1 US 201816489590 A US201816489590 A US 201816489590A US 2019385563 A1 US2019385563 A1 US 2019385563A1
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United States
Prior art keywords
line drive
display device
circuit
data lines
group
Prior art date
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Abandoned
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US16/489,590
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English (en)
Inventor
Masahiro Hirokane
Hirokazu Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
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Sharp Corp
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Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIROKANE, MASAHIRO, FUJIMOTO, Hirokazu
Publication of US20190385563A1 publication Critical patent/US20190385563A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to an active matrix type display device and a driving method thereof.
  • An active matrix type display device includes a display panel, a scanning line drive circuit, a data line drive circuit, and the like.
  • a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits arranged two-dimensionally are formed on the display panel.
  • the scanning line drive circuit is also called a gate driver, and the data line drive circuit is also called a source driver.
  • FIG. 10 is a circuit diagram of a pixel circuit formed on a liquid crystal panel.
  • a pixel circuit 90 shown in FIG. 10 includes a thin film transistor (hereinafter referred to as TFT) 91 , a liquid crystal capacitor 92 , and an auxiliary capacitor 93 .
  • a gate terminal of the TFT 91 is connected to a scanning line Gi, and a source terminal of the TFT 91 is connected to a data line Sj.
  • a drain terminal of the TFT 91 is connected to one electrode of the liquid crystal capacitor 92 and one electrode of the auxiliary capacitor 93 .
  • a common voltage Vcom is applied to the other electrode of the liquid crystal capacitor 92
  • an auxiliary capacitor voltage Vcs is applied to the other electrode of the auxiliary capacitor 93 .
  • the pixel circuit 90 has a gate-source capacitor 94 between the gate terminal and the source terminal of the TFT 91 .
  • a configuration of the data line drive circuit is more complicated than that of the scanning line drive circuit.
  • a plurality of data line drive circuits may be required to drive the data lines.
  • display devices having a plurality of data line drive circuits will be considered.
  • Patent Document 1 describes a display device that supplies a plurality of clock pulses and a plurality of start pulses having shifted phases, to a plurality of data line drive circuits. According to the display device described in Patent Document 1, since the plurality of data line drive circuits perform sampling on image data at different timings, it is possible to take in the image data at a high frequency and to prevent degradation of image quality.
  • Patent Document 1 Japanese Laid-Open Patent Publication No. 2009-31751
  • the scanning line Gi and the data line Sj are connected via the gate-source capacitor 94 , thus, when a voltage of the data line Sj (voltage applied to the data line Sj by the data line drive circuit) changes, a voltage of the scanning line Gi also changes due to its effect. Especially, when an amount of change in the voltage of the data line Sj is large, an amount of change in the voltage of the scanning line Gi becomes unignorably large, and noise is imposed on the voltage of the scanning line Gi. When the noise is large, the scanning line drive circuit may malfunction and a liquid crystal display device may not display an image correctly.
  • each data line drive circuit it is possible for each data line drive circuit to take in the image data at a high frequency, by shifting phases between the plurality of clock pulses and between the plurality of start pulses.
  • this display device cannot solve the above problem.
  • a display device having: a display panel including a plurality of scanning lines, a plurality of data lines classified into a plurality of groups, and a plurality of pixel circuits; a scanning line drive circuit configured to drive the plurality of scanning lines; and a plurality of data line drive circuits, each configured to drive the data lines in each group, wherein the plurality of data line drive circuits is configured to apply voltages to the data lines in each group in accordance with a plurality of latch strobe signals that change at timings different from each other.
  • a driving method of a display device having a display panel including a plurality of scanning lines, a plurality of data lines classified into a plurality of groups, and a plurality of pixel circuits including: driving the plurality of scanning lines using a scanning line drive circuit; and driving the data lines in each group using a plurality of data line drive circuits, wherein in driving the data lines, voltages are applied to the data lines in each group in accordance with a plurality of latch strobe signals that change at timings different from each other, using the plurality of data line drive circuits.
  • the plurality of data line drive circuits apply voltages to the data lines in each group in accordance with the plurality of latch strobe signals that change at timings different from each other, change timings of voltages of the data lines are different with respect to each group.
  • noise imposed on a voltage of the scanning line when the voltage of the data line changes can be reduced to equal to or less than 1/(the number of the data line drive circuits). Therefore, it is possible to prevent from erroneously writing the voltage of the data line to the pixel circuit and to prevent a disturbance of a display image, and it is possible to prevent a malfunction of the scanning line drive circuit and to display an image correctly.
  • FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment.
  • FIG. 2 is a diagram showing details of a liquid crystal panel shown in FIG. 1 .
  • FIG. 4 is a diagram showing another configuration of the timing control circuit shown in FIG. 1 .
  • FIG. 5 is a signal waveform diagram of the liquid crystal display device shown in FIG. 1 .
  • FIG. 6 is a diagram showing positions in the liquid crystal panel shown in FIG. 1 .
  • FIG. 7 is a signal waveform diagram of a liquid crystal display device according to a comparative example.
  • FIG. 8 is a signal waveform diagram of the liquid crystal display device shown in FIG. 1 .
  • the timing control circuit 12 , the scanning line drive circuit 13 , and the data line drive circuits 14 a to 14 d are respectively included in one semiconductor chip.
  • the scanning line drive circuit 13 is provided along one side (left side in the drawings) extending in the column direction of the liquid crystal panel 11 .
  • the data line drive circuits 14 a to 14 d are provided along another side (upper side in the drawings) extending in the row direction of the liquid crystal panel 11 .
  • FIG. 2 is a diagram showing details of the liquid crystal panel 11 .
  • the liquid crystal panel 11 includes m scanning lines G 1 to Gm, n data lines S 1 to Sn, and (m ⁇ n) pixel circuits 15 .
  • the scanning lines G 1 to Gm extend in the row direction, and are arranged in parallel to each other.
  • the data lines S 1 to Sn extend in the column direction, and are arranged in parallel to each other so as to intersect with the scanning lines G 1 to Gm perpendicularly.
  • the scanning lines G 1 to Gm and the data lines S 1 to Sn intersect at (m ⁇ n) positions.
  • the (m ⁇ n) pixel circuits 15 are provided corresponding to intersections of the scanning lines G 1 to Gm and the data lines S 1 to Sn.
  • the data line drive circuits 14 a to 14 d drive the data lines S 1 to Sn based on the control signal and the video signal.
  • the control signal output to the data line drive circuits 14 a to 14 d include a start pulse SP and four latch strobe signals LS 1 to LS 4 .
  • the start pulse SP is supplied to all of the data line drive circuits 14 a to 14 d.
  • the latch strobe signals LS 1 to LS 4 are respectively supplied to the data line drive circuits 14 a to 14 d.
  • the latch strobe signals LS 1 to LS 4 respectively indicate timings at which the data line drive circuits 14 a to 14 d apply voltages to the data lines in each group.
  • the data line drive circuit 14 a applies (n/4) voltages to the data lines in the first group when the latch strobe signal LS 1 changes from high-level to low-level.
  • the data line drive circuit 14 b applies (n/4) voltages to the data lines in the second group when the latch strobe signal LS 2 changes from high-level to low-level.
  • the data line drive circuit 14 c applies (n/4) voltages to the data lines in the third group when the latch strobe signal LS 3 changes from high-level to low-level.
  • the data line drive circuit 14 d applies (n/4) voltages to the data lines in the fourth group when the latch strobe signal LS 4 changes from high-level to low-level.
  • FIG. 3 is a diagram showing a configuration of the timing control circuit 12 .
  • the timing control circuit 12 includes a signal generation circuit 21 and a signal delay circuit 22 .
  • the signal generation circuit 21 generates a latch strobe signal LS and other control signals (not shown).
  • the latch strobe signal LS is a control signal that is a base of the latch strobe signals LS 1 to LS 4 , and becomes high-level once in one line period (one horizontal period) for a predetermined time.
  • the signal delay circuit 22 includes four flip-flop circuits 23 a to 23 d .
  • the latch strobe signal LS is input to the flip-flop circuits 23 a to 23 d.
  • the flip-flop circuits 23 a to 23 d have a configuration in which a plurality of flip-flops is connected in multi-stage.
  • the numbers of the flip-flops included in the flip-flop circuits 23 a to 23 d decrease in an order of the flip-flop circuit 23 a, the flip-flop circuit 23 b, the flip-flop circuit 23 c, and the flip-flop circuit 23 d.
  • delay times of the flip-flop circuits 23 a to 23 d become shorter in the same order.
  • Output signals of the flip-flop circuits 23 a to 23 d are respectively output to the data line drive circuits 14 a to 14 d as the latch strobe signals LS 1 to LS 4 .
  • the latch strobe signals LS 1 to LS 4 change at timings different from each other.
  • the latch strobe signals LS 1 to LS 4 change in an order of LS 4 , LS 3 , LS 2 , and LS 1 .
  • the data line drive circuits 14 a to 14 d apply voltages to the data lines in each group in accordance with the latch strobe signals LS 1 to LS 4 that change at timings different from each other.
  • the signal generation circuit 21 generates the control signal that is the base of the latch strobe signals LS 1 to LS 4 , and the signal delay circuit 22 delays the control signal by times different from each other to generate the latch strobe signals LS 1 to LS 4 .
  • the signal generation circuit 21 and the signal delay circuit 22 are included in a same semiconductor chip.
  • the scanning line drive circuit 13 is provided along one side of the liquid crystal panel 11 , and among the latch strobe signals LS 1 to LS 4 , a latch strobe signal corresponding to a group changes at an earlier timing, as the group is more apart from the scanning line drive circuit 13 .
  • the liquid crystal display device 10 may include a timing control circuit 16 shown in FIG. 4 in place of the timing control circuit 12 .
  • the timing control circuit 16 shown in FIG. 4 includes the signal generation circuit 21 and a signal delay circuit 24 having one flip-flop circuit 25 .
  • the latch strobe signal LS is input to the flip-flop circuit 25 .
  • An output signal of the flip-flop in a final stage of the flip-flop circuit 25 is output to the data line drive circuit 14 a as the latch strobe signal LS 1 .
  • Output signals of non-final stages of the flip-flop circuit 25 are output to the data line drive circuits 14 b to 14 d as the latch strobe signals LS 2 to LS 4 in an order of closeness to the final stage.
  • a latch strobe signal corresponding to a group changes at an earlier timing, as the group is more apart from the scanning line drive circuit 13 .
  • FIG. 5 is a signal waveform diagram of the liquid crystal display device 10 .
  • the gate clock GCK becomes high-level once in one line period for a predetermined time.
  • the latch strobe signals LS 1 to LS 4 become high-level for a predetermined time (becomes high-level once and then becomes low-level) at timings different from each other, after the gate clock GCK becomes high-level.
  • the latch strobe signals LS 1 to LS 4 change in the order of LS 4 , LS 3 , LS 2 , and LS 1 .
  • FIG. 5 describes voltages Va, Vb of the scanning line Gi at points Pa, Pb shown in FIG. 6 and voltages Vc, vd of a scanning line Gi+1 at points Pc, Pd shown in FIG. 6 .
  • the points Pa, Pc are located close to the scanning line drive circuit 13
  • the points Pb, Pd are located apart from the scanning line drive circuit 13 .
  • the larger a distance from the scanning line drive circuit 13 is, the larger dullness of a voltage waveform of the scanning line is.
  • dullness of the voltage waveform of the scanning line Gi is small at the point Pa, but becomes larger at the point Pb than at the point Pa.
  • FIG. 7 is a signal waveform diagram of the liquid crystal display device according to the comparative example.
  • FIG. 8 is a signal waveform diagram of the liquid crystal display device 10 .
  • VS 1 to VS 4 respectively indicate voltages of certain data lines in the first to fourth groups, and VGk indicates a voltage of a k-th scanning line Gk which is not selected.
  • the latch strobe signals LS 1 to LS 4 change from high-level to low-level at same timings at times ta, tb.
  • the voltages VS 1 to VS 4 of the data lines in the first to fourth groups start to change at the same timing at the times ta, tb.
  • the TFT in the pixel circuit has a gate-source capacitor, when a voltage of the data line changes, a voltage of the scanning line also changes, and noise is imposed on the voltage of the scanning line.
  • the voltages of the data lines S 1 to Sn start to change from low-level to high-level at the time ta and start to change from high-level to low-level at the time tb.
  • positive noise is imposed near the time ta
  • negative noise is imposed near the time tb.
  • the positive noise is large and the voltage VGk of the scanning line Gk exceeds a threshold voltage Vth of the TFT in the pixel circuit, the voltage of the data line may be erroneously written to the pixel circuit, and disturbance may occur in a display image.
  • the positive or negative noise is large, the scanning line drive circuit may malfunction, and an image may not be displayed correctly.
  • the latch strobe signals LS 1 to LS 4 change from high-level to low-level at different timings at times ta 1 to ta 4 and tb 1 to tb 4 .
  • the voltages VS 1 to VS 4 of the data lines in the first to fourth groups start to change at the different timings at the times ta 1 to ta 4 and tb 1 to tb 4 . Therefore, noise imposed on the voltage VGk of the scanning line Gk when the voltages of the data lines S 1 to Sn change is reduced to equal to or less than 1 ⁇ 4 of that in the liquid crystal display device according to the comparative example.
  • the liquid crystal display device 10 it is possible to prevent from erroneously writing the voltages of the data lines S 1 to Sn to the pixel circuit 15 , and to prevent disturbance of the display image. Furthermore, it is possible to prevent malfunction of the scanning line drive circuit 13 and to display an image correctly.
  • the plurality of data line drive circuits 14 a to 14 d apply voltages to the data lines in each group in accordance with the plurality of latch strobe signals LS 1 to LS 4 that change at timings different from each other, change timings of the voltages of the data lines S 1 to Sn are different with respect to each group.
  • FIG. 9 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment.
  • a liquid crystal display device 30 shown in FIG. 9 is obtained based on the liquid crystal display device 10 according to the first embodiment, by replacing the timing control circuit 12 with a timing control circuit 31 and a signal delay circuit 32 .
  • the timing control circuit 31 , the signal delay circuit 32 , the scanning line drive circuit 13 , and the data line drive circuits 14 a to 14 d are respectively included in one semiconductor chip.
  • the same reference symbols are provided and their description is omitted.
  • the timing control circuit 31 is obtained by removing the signal delay circuit 22 from the timing control circuit 12 ( FIG. 3 ).
  • the signal delay circuit 32 is the signal delay circuit 22 removed from the timing control circuit 12 .
  • the liquid crystal display device 30 has a configuration in which the signal delay circuit is provided outside the timing control circuit in the liquid crystal display device 10 according to the first embodiment.
  • the signal generation circuit 21 and the signal delay circuit 32 are included in different semiconductor chips. According to the liquid crystal display device 30 according to the present embodiment, since an existing timing control circuit can be used, it is not necessary to newly design a timing control circuit.
  • liquid crystal display devices including four data line drive circuits are described so far, the number of data line drive circuits included in the liquid crystal display device may be arbitrary as long as it is equal to or more than 2. Furthermore, although liquid crystal display devices including one scanning line drive circuit are described so far, the number of scanning line drive circuits included in the liquid crystal display device may be equal to or more than 2. Furthermore, although the signal delay circuit is configured using flip-flops, the signal delay circuit may have any configuration as long as it has a function of delaying a signal. Furthermore, display devices other than liquid crystal display devices can be configured in a manner similar to each embodiment.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US16/489,590 2017-05-12 2018-05-02 Display device and driving method thereof Abandoned US20190385563A1 (en)

Applications Claiming Priority (3)

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JP2017095583 2017-05-12
JP2017-095583 2017-05-12
PCT/JP2018/017497 WO2018207697A1 (fr) 2017-05-12 2018-05-02 Dispositif d'affichage et son procédé de commande

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11114056B2 (en) * 2018-07-16 2021-09-07 Samsung Display Co., Ltd. Power voltage generating circuit compensating ripple of a data power voltage and display apparatus including the same

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Publication number Priority date Publication date Assignee Title
KR100917008B1 (ko) * 2003-06-10 2009-09-10 삼성전자주식회사 액정표시장치
JP2005115290A (ja) * 2003-10-10 2005-04-28 Sharp Corp データラインの駆動方法およびそれを用いた表示装置並びに液晶表示装置。
KR101197057B1 (ko) * 2005-12-12 2012-11-06 삼성디스플레이 주식회사 표시 장치
JP4869706B2 (ja) * 2005-12-22 2012-02-08 株式会社 日立ディスプレイズ 表示装置
JP2008304513A (ja) * 2007-06-05 2008-12-18 Funai Electric Co Ltd 液晶表示装置、および液晶表示装置の駆動方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11114056B2 (en) * 2018-07-16 2021-09-07 Samsung Display Co., Ltd. Power voltage generating circuit compensating ripple of a data power voltage and display apparatus including the same

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