US20180358404A1 - Micro device integration into system substrate - Google Patents
Micro device integration into system substrate Download PDFInfo
- Publication number
- US20180358404A1 US20180358404A1 US16/107,680 US201816107680A US2018358404A1 US 20180358404 A1 US20180358404 A1 US 20180358404A1 US 201816107680 A US201816107680 A US 201816107680A US 2018358404 A1 US2018358404 A1 US 2018358404A1
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Definitions
- the present disclosure relates to the transferred micro device system integration on a receiver substrate. More specifically, the present disclosure relates to the post processing steps for enhancing the performance of micro-devices after transferring into a receiver substrate including the development of optical structure, the integration of electro-optical thin film devices, the addition of color conversion layers, and the proper patterning of devices on a donor substrate.
- the micro device array may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, (micro-electro-mechanical systems) MEMS, and/or other electronic components.
- the receiving substrate may be, but is not no limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical micro devices such as LEDs, a component of a display, for example a driving circuitry backplane.
- PCB printed circuit board
- thin film transistor backplane integrated circuit substrate
- optical micro devices such as LEDs
- a component of a display for example a driving circuitry backplane.
- post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling of the generated LED light.
- dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices.
- the active area of the pixel (or sub-pixel) is extended to be larger than the micro device by using fillers, for example, a dielectric.
- the filler is patterned to define the pixel active area.
- a pixel (or sub-pixel) active area is defined as the area that emits from the pixel (or sub-pixel), light produced by the light emitting micro device (or devices) or in the case of a sensor serves to gather and direct received light to a light sensing micro device of the pixel (or sub-pixel).
- reflective layers are used to confine the light within the active area.
- a method of integrated device fabrication comprising a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising: extending an active area of a first sub-pixel to an area larger than an area of a first micro device of the first sub-pixel by patterning of a filler layer about the first micro device and between the first micro device and at least one second micro device.
- One embodiment includes fabricating at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light within the active area of the sub-pixel.
- the reflective layer is fabricated as an electrode of the micro device
- the patterning of the filler layer further patterns the filler layer about a further sub-pixel.
- the patterning of the filler layer further is performed with a dielectric filler material.
- an integrated device comprising: a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate; and a patterned filler layer formed about a first micro device of a first sub-pixel and between the first micro device and at least one second micro device, the patterned filler layer extending an active area of the first sub-pixel to an area larger than an area of the first micro device.
- the integrated device further comprises: at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light to the active area of the first sub-pixel.
- the reflective layer is an electrode of the micro device.
- the patterned filler layer is formed about a further sub-pixel.
- a method of integrated device fabrication comprising a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising: integrating at least one micro device into a receiver substrate; and subsequently to the integration of the at least one micro device, integrating at least one thin-film electro-optical device into the receiver substrate.
- integrating the at least one thin-film electro-optical device comprises forming an optical path for the micro device through all or some layers of the at least one electro-optical device.
- integrating the at least one thin-film electro-optical device is such that an optical path for the micro device is through a surface or area of the integrated device other than a surface or area of the electro-optical device.
- Some embodiments further comprise fabricating an electrode of the thin-film electro-optical device, the electrode of the thin-film electro-optical device defining an active area of at least one of a pixel and a sub-pixel.
- Some embodiments further comprise fabricating an electrode which serves as a shared electrode of both the thin-film electro-optical device and the light emitting micro device.
- one of the micro device electrodes can serve as the reflective layer.
- the active area can consist of a few sub-pixels or pixels.
- the active area can be larger, smaller, or the same size as the pixel (or sub-pixel) area.
- pixel active area and sub-pixel active area are used interchangeably.
- the pixel and/or sub-pixel can be used in all the embodiments described here.
- thin film electro-optical devices are deposited onto the receiver substrate after the micro devices are integrated into the receiver substrate.
- an optical path is developed for the micro device to emits (or absorb) light through all or some layers of the electro-optical device.
- the optical path for the micro device is not through all or some layers of the electro-optical device.
- the electro-optical device is a thin film device.
- the electrode of the electro-optical device is used to define the active area of the pixel (or sub-pixel).
- At least one of the electro-optical device electrodes is shared with the micro-device electrode.
- color conversion material covers the surface and surrounds partially (or fully) the body of the micro device.
- the bank structure separates the color conversion materials.
- color conversion material covers the surface (and/or partially or fully the body of) the active area.
- the micro devices on donor substrate are patterned to match the array structure in the receiver (system) substrate. In this case, all the devices in part (or all) of the donor substrate are transferred to the receiver substrate.
- VIAs are created in the donor substrate to couple the micro devices on the donor substrate with the receiver substrate.
- the donor substrate has more than one micro device type and at least in one direction the pattern of the micro device types on the donor substrate matches partially or fully the pattern of the corresponding areas (or pads) on the system substrate.
- the donor substrate has more than one micro device type and at least in one direction the pitch between different micro devices in donor substrate is a multiple of the pitch of the corresponding areas (or pads) on the system substrate.
- the donor substrate has more than one micro device type. At least in one direction, the pitch between two different micro devices matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate.
- the pattern of different micro device types on the donor substrate creates a two dimensional array of each type where the pitch between each array of different types matches the pitch of the corresponding areas on the system substrate.
- the pattern of different micro device types on the donor substrate creates a one dimensional array where the pitch of the arrays matches the pitch of the corresponding areas (or pads) on the system substrate.
- FIG. 1 shows a receiver substrate with contact pads, and an array of transferred micro-devices attached to the receiver substrate.
- FIG. 2A shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, and conformal dielectric and reflective layers on top.
- FIG. 2B shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, and patterned conformal dielectric and reflective layers.
- FIG. 2C shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, patterned conformal dielectric and reflective layers, and a black matrix layer formed between adjacent micro-devices.
- FIG. 3A shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, patterned conformal dielectric and reflective layers, a black matrix layer, and a transparent conductive layer deposited on the substrate.
- FIG. 3B shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate and optical reflective components for light outcoupling enhancement.
- FIG. 3C shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate and concave contact pads for light outcoupling enhancement.
- FIG. 3D shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate in a bottom emission configuration.
- FIG. 3E shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate.
- FIG. 4A shows a receiver substrate with transferred micro-devices, a conformal dielectric layer, and a connected reflective layer.
- FIG. 4B shows a receiver substrate with transferred micro-devices, conformal dielectric layer, connected reflective layer, and a transparent conductive layer deposited on the substrate.
- FIG. 5 shows a receiver substrate with transferred micro-devices and a patterned filler which defines the pixels (or sub-pixels).
- FIG. 6A shows a pixelated filler structure covering all sub-pixels in at least one pixel (for example covering both sub-pixels for a pixel made of two sub-pixels).
- FIG. 6B shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, and patterned conformal dielectric and reflective layers around the pixel.
- FIG. 6C shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, patterned conformal dielectric and reflective layers around the pixel, and a black matrix layer wrapped around the pixel.
- FIG. 6D shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, patterned conformal dielectric and reflective layers around the pixel, a black matrix layer wrapped around the pixel, and a transparent conductive layer deposited on the substrate.
- FIG. 6E shows a pixel made of two sub-pixels with reflective optical components on the receiver substrate for better light outcoupling.
- FIG. 6F shows a pixel made of two sub-pixels with concave contact pads on the receiver substrate.
- FIG. 6G shows a pixel made of two sub-pixels with a bottom emission configuration.
- FIG. 6H shows a pixel made of two sub-pixels with a bottom emission configuration, a common top electrode, and side reflectors.
- FIG. 7 shows a receiver substrate with two contact pads.
- FIG. 8 shows a receiver substrate with a transferred micro device bonded to one of the contact pads.
- FIG. 9 shows the integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure.
- FIG. 10 shows another example of an integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure.
- FIG. 11 shows an example of the integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure with a common top electrode.
- FIG. 12 shows an embodiment for the integration of a transferred micro-device with an electro-optical thin film device in a dual surface hybrid structure with both top and bottom transparent electrodes.
- FIG. 13A shows another embodiment for a system substrate and an integrated micro device with thin film electro-optical device.
- FIG. 13B shows another embodiment of a system substrate and an integrated micro device with a thin film electro-optical device.
- FIG. 14A shows a modified embodiment of a system substrate and an integrated micro device with two thin film electro-optical devices.
- FIG. 14B shows an example of a system substrate and an integrated micro device with two thin film electro-optical devices and a reflective layer on the receiver substrate.
- FIG. 15 illustrates a cross section of a system substrate and a micro device substrate.
- FIG. 16 shows the alignment step for a system substrate and a micro device substrate in a transfer process.
- FIG. 17 shows the bonding step for a system substrate and a micro device substrate in a transfer process.
- FIG. 18 shows the micro device substrate removal step for a system substrate and a micro device substrate in a transfer process.
- FIG. 19 shows the sacrificial layer removal step for a system substrate and a micro device substrate in a transfer process.
- FIG. 20 shows the common electrode formation step for a system substrate and a micro device substrate in a transfer process.
- FIG. 21 is a cross section of a micro device substrate with a filler layer(s).
- FIG. 22 is a cross section of a micro device substrate covered with a support layer.
- FIG. 23 shows the micro device substrate removal step for a micro device substrate in a transfer process.
- FIG. 24A shows the sacrificial/buffer layer removal step for a micro device substrate in a transfer process. A system substrate with contact pads is shown as well.
- FIG. 24B shows the exposed micro devices after removal of the sacrificial/buffer layer.
- FIG. 25 shows the bonding step for a system substrate and a micro device substrate in a transfer process.
- FIG. 26A shows the supporting layer removal step for a micro device substrate in a transfer process. A system substrate with contact pads and transferred micro devices is shown as well.
- FIG. 26B shows the exposed micro devices after removal of the supporting layer and the filler layer.
- FIG. 27 is a cross section of a micro device substrate covered with a filler layer.
- FIG. 28A is a cross section of a micro device substrate with via holes in the substrate and the sacrificial layer.
- FIG. 28B is the cross section shown in FIG. 28A , after removal of the buffer layer.
- FIG. 29 is a cross section of a micro device substrate with via holes in the substrate and the sacrificial layer covered by an insulating layer.
- FIG. 30 is a cross section of a micro device substrate with a conductive layer filled via holes in the substrate and the sacrificial layer.
- FIG. 31 is a cross section of a micro device substrate with a common top electrode.
- FIG. 32 is a cross section of an integrated system substrate with a common top electrode.
- FIG. 33A shows a two dimensional arrangement of micro devices in a donor substrate.
- FIG. 33B is a cross section of a system substrate and a micro device substrate.
- FIG. 34 is a cross section of a bonded system substrate and micro device substrate.
- FIG. 35 shows the laser lift-off step for a micro device substrate in a transfer process.
- FIG. 36 is a cross section of a system substrate and a micro device substrate after the selective transfer process.
- FIG. 37 shows an integrated system substrate with a common top electrode.
- FIG. 38A is a cross section of a micro device substrate with micro devices having different heights.
- FIG. 38B is the cross section shown in FIG. 38A after the buffer layer has been patterned.
- FIG. 39 is a cross section of a micro device substrate with a filler layer.
- FIG. 40 shows the alignment step for a system substrate with grip mechanisms and a micro device substrate in a transfer process.
- FIG. 41A shows a two dimensional arrangement of micro devices in a donor substrate.
- FIG. 41B is a cross section of a system substrate and a micro device substrate with different pitches.
- FIG. 42 shows the selective micro device transfer process for a system substrate and a micro device substrate with different pitches.
- FIG. 43 is a cross section of a system substrate and a micro device substrate with different pitches.
- FIG. 44 shows the selective micro device transfer process for a system substrate and a micro device substrate with different pitches.
- FIG. 45 shows an integrated micro device substrate.
- FIG. 46A shows the transfer process of micro devices to a system substrate with a planarization layer, a common top electrode, bank structures, and color conversion elements.
- FIG. 46B shows the structure of FIG. 46A with the addition of a common electrode formed on the planarization layer.
- FIG. 47 shows a structure with color conversion for defining the color of pixels.
- FIG. 48 shows a structure with conformal common electrode and color conversion separated by a bank layer.
- FIG. 49 shows a structure with conformal color conversion separated by a bank layer.
- FIG. 50 shows a structure with color conversion elements on the common electrode without the bank layer.
- FIG. 51 shows a structure with conformal common electrode and color conversion.
- FIG. 52 shows a structure with conformal color conversion elements formed directly on the micro devices.
- FIG. 53A shows a structure with color conversion for defining pixel color, a planarization layer, and a common transparent electrode.
- FIG. 53B shows the structure of FIG. 53A after forming the encapsulation layer.
- FIG. 54A shows a structure with color conversion for defining pixel color and a separate substrate for encapsulation.
- FIG. 54B shows the structure of FIG. 54B after the substrate coated with the encapsulation layer is bonded to the integrated system substrate.
- FIG. 55A shows a structure with a system substrate with contact pads, and a separate donor substrate with micro devices.
- FIG. 55B shows the structure of FIG. 55A after transfer of the micro devices to the system substrate.
- FIG. 55C shows the structure of FIG. 55B after post processing to deposit a common electrode and color conversion layers.
- the process of developing a system based on micro devices consists of pre-processing the devices on a donor substrate (or a temporary substrate), transferring the micro devices from the donor substrate to the receiver substrate, and post processing to enable device functionality.
- the pre-processing step may include patterning and adding bonding elements.
- the transfer process may involve bonding of a pre-selected array of micro devices to the receiver substrate followed by removing the donor substrate.
- Several different selective transfer processes have already been developed for micro devices. After the integration of the micro devices into the receiving substrate, additional post processes may be performed to make required functional connections.
- emissive device is used to describe different integration and post processing methods.
- other devices such as sensors can be used in these embodiments.
- the optical path will be similar to emissive micro devices but in reverse direction.
- the micro device array may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, MEMS (micro-electro-mechanical systems), and/or other electronic components.
- the receiving substrate may be, but is not no limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical micro devices such as LEDs, a component of a display, for example a driving circuitry backplane.
- PCB printed circuit board
- thin film transistor backplane integrated circuit substrate
- optical micro devices such as LEDs
- a component of a display for example a driving circuitry backplane.
- post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling of the generated LED light.
- dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices.
- the active area of the pixel is extended to be larger than the micro device by using fillers (or dielectric).
- the filler is patterned to define the pixel's active area (the active area is the area that emits light or is absorbing input light).
- reflective layers are used to confine the light within the active area.
- the reflective layer can be one of the micro device electrodes.
- the active area can consist of a few sub-pixels or pixels.
- the active area can be larger, smaller, or the same size as the pixel (sub-pixel) area.
- thin film electro-optical devices are deposited into the receiver substrate after the micro devices are integrated into the receiver substrate.
- an optical path is developed for the micro device to emit (or absorb) light through all or some layers of the electro-optical device.
- the optical path for the micro device is not through all or some layers of the optoelectronic device.
- the optoelectronic device is a thin film device.
- the electrode of the electro-optical device is used to define the active area of the pixel (or sub-pixel).
- At least one of the electro-optical device electrodes is shared with the micro-device electrode.
- color conversion material covers the surface and surrounds partially (or fully) the body of the micro device.
- the bank structure separates the color conversion materials.
- color conversion material covers the surface (and/or partially or fully the body of) the active area.
- the micro devices on donor substrate are patterned to match the array structure in the receiver (system) substrate. In this case, all the devices in part (or all) of the donor substrate are transferred to the receiver substrate.
- VIAs are created in the donor substrate to couple the micro devices on the donor substrate with the receiver substrate.
- the donor substrate has more than one micro device types and at least in one direction the pattern of the micro device types on the donor substrate matches partially or fully the pattern of the corresponding areas (or pads) on the system substrate.
- the donor substrate has more than one micro device types and at least in one direction the pitch between different micro devices in donor substrate is a multiple of the pitch of the corresponding area (or pads) on the system substrate.
- the donor substrate has more than one micro device type. At least in one direction, the pitch between two different micro devices matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate.
- the pattern of different micro device types on the donor substrate creates a two dimensional array of each type where the pitch between each array of different types matches the pitch of the corresponding areas on the system substrate.
- the pattern of different micro device types on the donor substrate creates a one dimensional array where the pitch of the arrays matches the pitch of the corresponding areas (or pads) on the system substrate.
- FIG. 1 shows a receiver substrate 100 , contact pads 101 a and 101 b , and micro devices 102 a and 102 b , being in an array attached to the receiver substrate 100 .
- Contact pads 101 where micro devices 102 have been transferred are located in an array on receiver substrate 100 .
- Micro devices 102 are transferred from a donor substrate and bonded to the contact pads 101 .
- Micro devices 102 can be any micro device that may typically be manufactured in planar batches including but not limited to LEDs, OLEDs, sensors, solid state devices, integrated circuits, MEMS, and/or other electronic components.
- a conformal dielectric layer 201 and a reflective layer 202 may be formed over the bonded micro LEDs.
- the conformal dielectric layer 201 is approximately 0.1-1 ⁇ m thick and it may be deposited by any of a number of different thin film deposition techniques.
- the conformal dielectric layer 201 isolates the micro LED sidewalls from the reflective layer 202 .
- the dielectric layer 201 passivates and protects the micro LED sidewalls.
- the conformal dielectric layer 201 may also cover the top surface of the receiver substrate 100 between adjacent micro LED devices 102 a and 102 b .
- the conformal reflective layer 202 may be deposited over the dielectric layer 201 .
- the reflective layer 202 may be a single layer or made up of multiple layers.
- a variety of conductive materials may be used as the reflective layer 202 .
- the conformal reflective layer 202 may be a metallic bilayer with a total thickness up to 0.5 ⁇ m.
- the dielectric layer 201 and reflective layer 202 may then be patterned by using for example lithographic patterning and etching to partially expose the top surface of micro LEDs 102 .
- a black matrix 203 may be formed between adjacent micro LEDs 102 and on the reflective layer 202 to reduce the reflection of the ambient light.
- the black matrix 203 may be a layer of resins such as polyimide or polyacrylic in which particles of black pigment such as carbon black have been dispersed.
- the thickness of the black matrix 203 may be 0.01-2 ⁇ m.
- This layer may be patterned and etched so as to expose the top surface of the micro LEDs 102 as shown in FIG. 2C .
- the thickness of the black matrix 203 may be engineered to planarize the integrated substrate 100 .
- a planarization layer which may be made of organic insulating material is formed and patterned to planarize the backplane substrate.
- a transparent conductive layer 301 may be conformally deposited on the substrate, covering the black matrix 203 and the top surface of micro LEDs 102 .
- the transparent electrode 301 may be 0.1-1 um thick layers of oxides, including but not limited to indium tin oxide (ITO) and Aluminum doped Zinc Oxide.
- the transparent electrode 301 may be the common electrode of the micro LED devices 102 .
- the reflective layer 202 may be used as a conductivity booster for the transparent electrode 301 .
- part of the reflective layer may not be covered with black matrix 203 , or other planarization layers, so that the transparent electrode layer 301 may connect to the reflective layer 202 .
- a reflective or other type of optical component 302 may be formed on the substrate 100 to enhance outcoupling of light produced by micro devices 102 a and 102 b .
- the common contact 301 is transparent to allow light output through this layer. These structures may be referred as top emission structures.
- the contact pad 101 may be formed to have a concave or other shaped structure to enhance the outcoupling of light produced by microdevices 102 .
- the contact pad form is not limited to the concave form and may have other forms depending on the micro device light emission characteristics.
- the structure is designed to output light from the substrate.
- the substrate 100 may be transparent and the common electrode 303 is designed to be reflective for better light extraction.
- the reflective layer 202 may be extended to cover the micro devices and act as the common top electrode as well.
- the dielectric layer 201 may be deposited and patterned before forming the reflective layer 202 . As shown in FIG. 4 , this may allow a direct contact between micro LEDs 102 and the reflective layer 202 which may be used as a common top contact for the micro devices 102 . Black matrix 203 or alternatively a planarization layer may be used.
- a common transparent electrode 301 or/and other optical layers may be deposited on top of the substrate 100 to enhance conductivity and/or light out coupling.
- the micro device sizes may be optically extended to be the same or larger than the micro device size.
- transparent filler 501 is deposited and patterned to define the pixel (or sub-pixel).
- the filler size can be the smaller or the maximum size possible in a pixel (or sub-pixel) area.
- the filler size may be larger than the pixel or sup-pixel area.
- the filler may have a different or a similar shape as the pixel area on the system substrate. The processes illustrated in FIG. 3 and FIG. 4 may then be applied to improve the light extraction from the micro devices.
- the filler 501 is patterned to define the active area of the pixel 601 (active area being defined as the area from which the display emits light).
- the active area can be smaller, larger, or the same size as the pixel (or sub-pixel) area.
- FIG. 6B , FIG. 6C , and FIG. 6D processes mentioned in FIG. 2 and FIG. 3 may be applied. This configuration manages the discoloration at the edges due to the separation between sub-pixels
- a dielectric layer 201 and a reflective layer 202 may be formed around over pixel 601 .
- a black matrix 203 may be formed between adjacent pixels and around each pixel to reduce the reflection of the ambient light.
- a transparent conductive layer 301 may be deposited on the substrate, covering the black matrix 203 and the top surface of micro LEDs 601 a and 601 b.
- reflective or other optical component 602 may be formed on the substrate 100 to enhance outcoupling of light produced by micro devices 601 a and 601 b .
- the common contact 301 is transparent for the light to output through this layer. These structures may be referred to as top emission structures.
- the contact pad 101 may be formed to have a concave structure to enhance the outcoupling of light produced by micro devices 601 .
- the contact pad form is not limited to the concave form and may have other forms depending on the micro device light emission characteristics.
- the structure is designed to output light from the substrate.
- the substrate 100 may be transparent and the common electrode 303 is designed to be reflective for better light extraction.
- the reflective layer 202 may be extended to cover the micro devices and act as the common top electrode as well.
- the aforementioned pixel definition structure can cover more than one pixel (or sub-pixel).
- a reflective layer or the contact pads on the receiving substrate may be used to cover the receiving substrate and create a reflective area before transferring the micro devices for better light out coupling.
- the reflective layer can also be opaque.
- the reflective layers can be used as one of the micro device electrodes or as one of the system substrate connections (electrode, signal, or power line).
- the reflective layer can be used as a touch electrode.
- the reflective layers can be patterned to act as a touch screen electrode. In one case, they can be patterned in vertical and horizontal directions to form the touch screen crossing electrode. In this case, one can use a dielectric between vertical and horizontal traces.
- a thin film electro-optical device is integrated into the receiver substrate after the micro device arrays have been transferred to the receiver substrate.
- FIG. 7 shows a receiver substrate 100 and contact pads 702 upon which the micro device arrays are transferred and into which the thin film electro-optical device is integrated in a number of hybrid structure embodiments.
- micro device 801 may be transferred and bonded to the bonding pad 702 a of the receiver substrate 100 .
- a dielectric layer 901 is formed over the substrate 100 to cover the exposed electrodes and conductive layers. Lithography and etching may be used to pattern the dielectric layer 901 .
- Conductive layer 902 is then deposited and patterned to form the bottom electrode of the thin film electro-optical device 904 . If there is no risk of unwanted coupling between bottom electrode 902 and other conductive layers in the receiver substrate, the dielectric layer 901 may be eliminated. However, this dielectric layer can act as planarization layer as well to offer better fabrication of electro-optical devices 904 .
- a bank layer 903 is deposited on the substrate 100 to cover the edges of the electrode 902 and the micro device 801 .
- Thin film electro-optical device 904 is then formed over this structure.
- Organic LED (OLED) devices are an example of such a thin film electro-optical device which may be formed using different techniques such as but not limited to shadow mask, lithography, and printing patterning.
- the top electrode 905 of the electro-optical thin film device 904 is deposited and patterned if needed.
- a planarization layer may be used in conjunction with or without the dielectric layer 901 to address this issue.
- the micro device 801 can have a device electrode 1001 .
- This electrode can be common between other micro devices in the system substrate.
- the planarization layer (if present) and/or bank layer 903 covers the electrode 1001 to avoid any shorts between the electro-optical device 904 and device electrode 1001 .
- top electrode 905 of the thin film electro-optical device 904 may be connected to the micro device 801 through an opening in the planarization layer.
- the electro-optical device 904 may be formed selectively so that it is not covering this opening.
- the bottom electrode of the micro device can be shared between the thin film electro-optical device and the transferred micro device.
- the bottom electrode 902 of the thin film electro-optical device 904 can be expanded over the micro device 801 .
- the bottom electrode 902 (if not transparent) needs to have an opening over the micro device (for example as shown in FIG. 13A in association with another embodiment).
- the opening can be covered by the bank layer 903 as well.
- the opening is not limited to the specific structure illustrated in FIG. 12 and can be developed with different methods.
- the micro device 801 can have a transparent path through the substrate 100 if electrode 702 is transparent.
- either the bottom electrode 902 and the micro device top electrode need to be transparent or there needs to be opening in the bottom electrode 902 .
- FIG. 13A shows a layout structure where the bottom electrode 902 has an opening to allow a transparent path through the top electrode 905 .
- the top electrode 905 is also opaque, an opening in the top electrode 905 is also needed for top emission.
- the bottom electrode 902 does not cover the micro device 801 .
- the contact of the thin film electro-optical device can be extended to act as reflective layer.
- the two side-by-side pixels can act to confine the light generated by the micro device 801 in the pixel.
- the reflective layer 1401 on the surface of the substrate 100 can reflect more of the lights toward the top electrode 905 .
- the out coupling of the light generated by the micro device 801 is enhanced.
- the best practice is either to make both top and bottom electrode of the thin film electro-optical device transparent, or make openings if these electrodes are opaque.
- the thin film electro-optical devices and micro devices can be on two opposite sides of the system substrate.
- the system substrate circuitry can either be on one side of the system substrate and connected to the other side through contact holes or, the circuits can be on both sides of the system substrate.
- the micro device can be on one system substrate and the thin film electro-optical device on another system substrate. These two substrates may then be bonded together.
- the circuit can be on one of the system substrates or on both substrates.
- This document also discloses various methods for the integration of a monolithic array of micro devices into a system substrate or selective transferring of an array of micro devices to a system substrate.
- the proposed processes are divided into two categories.
- the pitch of the bonding pads on the system substrate is the same as the pitch of the bonding pads of the micro devices.
- bonding pads on the system substrate have a larger pitch compared to that of the micro devices.
- three different schemes of integration or transfer are presented
- micro-devices may be of the same type or different types in terms of functionality.
- micro-devices are micro-LEDs of the same color or of a number of different colors (e.g., Red, Green, and Blue), and the system substrate is the backplane, controlling individual micro-LEDs.
- Such multi-color LED arrays are fabricated directly on a substrate or transferred to a temporary substrate from the growth substrate.
- RGB micro-LED devices 1503 , 1504 , and 1505 were grown on a sacrificial/buffer layer 1502 and the substrate 1501 .
- the system substrate 1506 having contact pads 1507 can be aligned ( FIG.
- a filler dielectric coating 2001 e.g., Polyimide resist
- a filler dielectric coating 2001 may be spin-coated/deposited on the integrated sample ( FIG. 20 ). This step may be followed by an etching process to reveal the tops of the micro-LED devices.
- a common transparent electrode 2002 may be deposited on the sample.
- a top electrode may be deposited and patterned to isolate micro devices for subsequent processes.
- the micro devices 1503 , 1504 , and 1505 are grown on a buffer/sacrificial layer 1502 .
- a dielectric filler layer 2101 is deposited/spin-coated on the substrate to fully cover the micro devices.
- this step is followed by an etching process to reveal the tops of the micro devices 1503 , 1504 , and 1505 to form the top common contact and seeding layer for subsequent processes (e.g. electroplating).
- a thick mechanical supporting layer 2102 is then deposited, grown or bonded on the tops of the sample.
- the filler layer 2101 can be a black matrix layer or a reflective material.
- the mechanical support before depositing the mechanical support, one can deposit an electrode (either as a patterned or a common layer). The mechanical support layer is then deposited. In the case of optoelectronic devices such as LEDs, the mechanical support layer needs to be transparent.
- the micro device substrate 1501 or sacrificial/buffer layer is then removed using various processes such as laser lift-off or etching. In one case, the thickness of the substrate is initially reduced to a few micrometers by processes such as but not limited to deep reactive ion etching (DRIE). The remaining substrate then is removed by processes such as but not limited to a wet chemical etching process.
- DRIE deep reactive ion etching
- the buffer/sacrificial layer 1502 may act as an etch-stop layer to ensure a uniform etched sub-surface and to avoid any damage to the micro devices.
- another etching e.g., RIE
- the system substrate 1506 having contact pads 1507 can then be aligned and bonded to the micro device array as shown in FIG. 25 .
- the mechanical supporting layer 2102 and filler layer 2101 may be then removed as shown in FIG. 26A and FIG. 26B .
- through substrate vias are implemented to make contacts to the back of the micro devices.
- the micro devices 1503 , 1504 , and 1505 may be multicolor micro-LEDs grown on an insulating buffer layer 1502 .
- This buffer layer may function as an etch-stop layer as well.
- a dielectric layer 2701 is deposited as a filler layer.
- patterns are formed on the backside of the substrate 1501 .
- a method such as DRIE is used to make through substrate holes in the substrate 1501 .
- Buffer layer 1502 which may act as an etchstop layer may be removed using for example a wet-etch process, as illustrated in FIG. 28B .
- an insulating film 2901 is deposited on the back of the substrate 1501 .
- This insulating layer 2901 may be partially removed from back side of the micro devices 1503 , 1504 , and 1505 to allow formation of electrical contacts to these micro devices.
- the through holes are filled with a conductive material 3001 using processes such as but not limited to electroplating.
- the vias may act as the micro device contacts and bonding pads.
- a common front contact 3101 of the micro devices 1503 , 1504 , and 1505 is formed by performing an etching process (e.g., using RIE) to reveal the tops of the micro-devices followed by the deposition of a transparent conductive layer to form the front contact 3101 .
- an etching process e.g., using RIE
- the micro device substrate 1501 is then aligned and bonded to the system substrate 1506 having contact pads 1507 which in this example may be a backplane controlling individual devices.
- micro devices have been fabricated on a substrate with arbitrary pitch length to maximize the production yield.
- the micro devices may be multi-color micro-LEDs (e.g., RGB).
- the system substrate for this example may be a display backplane with contact pads having a pitch length different than those of the micro-LEDs.
- the donor substrate 1501 has micro device types 3301 , 3302 , and 3303 and they are patterned in the form of one dimensional arrays 3304 in which for each micro device 3301 , 3302 , or 3303 from one type, there is at least a micro device from another type that their pitch 3305 matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate.
- the pitch 3404 of contact pads 1507 is two times larger than the pitch 3402 of the micro devices 3401 as shown in FIG. 33 .
- system substrate 1506 and micro device substrate 1501 are brought together, aligned and put in contact.
- LLO laser lift-off
- a buffer layer 3801 is necessary as a material template for the fabrication of micro devices 1503 , 1504 , and 1505 .
- the buffer layer 3801 is deposited on the sacrificial layer 1502 and patterned to isolate micro devices 1503 , 1504 , and 1505 .
- the sacrificial layer 1502 may be patterned as well.
- groups of micro devices may be isolated from one another (as shown in FIG. 38 ) to facilitate the transfer process.
- a filling material 3901 such as but not limited to polyimide may be spin coated on the substrate to fill the gap between the individual micro devices. This filling step insures the mechanical strength during the transfer process. This is particularly important when a process like laser lift-off is used to detach micro devices from the carrier substrate.
- micro devices may not have the same height which make it difficult to bond them to the system substrate.
- the grip mechanism may be local for micro devices or a global grip for a group of micro devices as in the case of same-pitch transfer for the whole wafer.
- the grip mechanism may be on a layer above the contact electrode. In this case, a planarization layer may be used.
- the pattern of different micro device types 3301 , 3302 , and 3303 on donor substrate create a two dimensional array of each type (for example array 4100 ) where the pitch between the arrays 4101 defined as the center-to-center distance between adjacent arrays) matches the pitch of the corresponding area on the system substrate.
- micro device substrate 1501 is laid out in the form of two-dimensional single color arrays.
- the contact pad pitch 4102 and the micro device array pitch 4103 are the same. Using this technique, one may relax the micro device fabrication requirements and reduce the selective transferring process as compared to that described above.
- FIG. 43 and FIG. 44 shows an alternative pattern where micro devices are not formed in two-dimensional groups and the different micro devices uniformly placed across the substrate as it shown in FIG. 43 for three different micro devices.
- micro devices are first transferred to a conductive semi-transparent common substrate 4501 , then they are bonded to a system substrate 4502 .
- the micro devices are optical devices such as LEDs
- two or more contact pads on the system substrate are populated with the same type of optical device. Once in place, the devices on the system substrates are then differentiated by different color conversion layers.
- the whole structure is covered by a planarization layer 4601 .
- a common electrode 4602 is then formed on the planarization layer 4601 .
- the planarization layer can be the same height as, taller than, or shorter than the stacked devices. If the planarization layer is shorter (or there is no planarization layer) the wall of the device can be conformally covered by passivation materials.
- a bank structure 4701 is developed (especially if a printing process is used to deposit the color conversion layers).
- the bank can separate each pixel or just separate different color conversion materials 4702 .
- FIG. 48 shows an integrated structure where the color conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.
- Bank 4701 separates the color conversion layers 4702 and the electrode 4602 is a common contact for all transferred micro devices.
- FIG. 49 shows an integrated structure where the color conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.
- Bank 4701 separates the color conversion layers and contacts to the micro devices are made only through the system substrate 1506 .
- FIG. 50 shows an integrated structure where the color conversion layer is directly formed on the common electrode 4602 . In this case no bank layer is used.
- FIG. 51 shows an integrated structure where the color conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.
- the electrode 4602 is a common contact for all transferred micro devices. In this case no bank layer is used.
- FIG. 52 shows an integrated structure where the color conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.
- the contacts to the micro devices are made only through the system substrate. In this case no bank layer is used.
- a planarization layer 5301 is deposited on the structure.
- an encapsulation layer 5302 is formed over the whole structure. It should be noted that the encapsulation layer 5302 may be formed from a stack of different layers to effectively protect the integrated substrate from environmental conditions
- a separate substrate 5401 coated with the encapsulation layer 5302 may be bonded to the integrated system substrate.
- FIG. 53 and FIG. 54 may be combined in which encapsulation layer 5302 is formed both on the structure and the separate substrate for more effective capsulation.
- the common electrode is a transparent conductive layer deposited on the substrate in the form of a blanket.
- this layer can act a planarization layer.
- the thickness of this layer is chosen to satisfy both optical and electrical requirements.
- the distance between the optical devices may be chosen to be large enough so as to reduce cross-talk between the optical devices or a blocking layer is deposited between the optical devices to achieve this.
- the planarization layer functions also as a blocking layer.
- color conversion layers After the color conversion layers are deposited, different layers such as polarizers can be deposited.
- color filters are deposited on the color conversion layers. In this case wider color gamut and higher efficiency may be achieved.
- the color filters can be larger than the color conversion layer to block any light leakage. Moreover, a black matrix can be formed between the color conversion islands or color filters.
- FIGS. 55A, 55B, and 55C illustrate structures where the device is shared between a few pixels (or sub-pixels).
- the micro device 1503 is not fully patterned but the horizontal condition is engineered so that the contacts 1507 define the area allocated to each pixel.
- FIG. 55A shows the system substrate 1506 with contact pads 1507 and a donor substrate 1501 with micro devices 1503 .
- the micro devices 1503 are transferred to system substrate (shown in FIG. 55B )
- one can do post processing FIG. 55C ) such as depositing common electrode 4602 , color conversion layers 4702 , color filters and so on.
- FIG. 55C shows one example of depositing color conversion layers 4702 on top of the micro device 1503 .
- the methods described in this disclosure and other possible method can be used.
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Abstract
Description
- This application is a continuation under 35 U.S.C. § 120 of co-pending U.S. application Ser. No. 15/060,942 (3USP1) filed on Mar. 4, 2016, which in turn is a continuation-in-part to U.S. application Ser. No. 15/002,662, filed Jan. 21, 2016 (3USPT), which claims priority to Canadian Application No. 2,890,398, filed May 4, 2015 (129CAPL), Canadian Application No. 2,883,914, filed Mar. 4, 2015 (128CAPL), Canadian Application No. 2,880,718, filed Jan. 28, 2015 (127CAPL), Canadian Application No. 2,879,465, filed Jan. 23, 2015 (125CAPL), and Canadian Application No. 2,879,627, filed Jan. 23, 2015 (99CAPL), each of which is hereby incorporated by reference herein in its entirety. This application also claims priority to Canadian Application No. 2,898,735, filed Jul. 29, 2015 (8CAP2) and Canadian Application No. 2,887,186, filed Apr. 8, 2015 (128CAP2), each of which is hereby incorporated by reference herein in its entirety.
- The present disclosure relates to the transferred micro device system integration on a receiver substrate. More specifically, the present disclosure relates to the post processing steps for enhancing the performance of micro-devices after transferring into a receiver substrate including the development of optical structure, the integration of electro-optical thin film devices, the addition of color conversion layers, and the proper patterning of devices on a donor substrate.
- A few embodiments of this description are related to post-processing steps for improving the performance of the micro devices. For example, in some embodiments, the micro device array may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, (micro-electro-mechanical systems) MEMS, and/or other electronic components. The receiving substrate may be, but is not no limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical micro devices such as LEDs, a component of a display, for example a driving circuitry backplane. In these embodiments, in addition to interconnecting the micro devices, post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices.
- In one embodiment, the active area of the pixel (or sub-pixel) is extended to be larger than the micro device by using fillers, for example, a dielectric. Here, the filler is patterned to define the pixel active area. Herein a pixel (or sub-pixel) active area is defined as the area that emits from the pixel (or sub-pixel), light produced by the light emitting micro device (or devices) or in the case of a sensor serves to gather and direct received light to a light sensing micro device of the pixel (or sub-pixel). In another embodiment reflective layers are used to confine the light within the active area.
- According to one aspect, there is provided a method of integrated device fabrication, the integrated device comprising a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising: extending an active area of a first sub-pixel to an area larger than an area of a first micro device of the first sub-pixel by patterning of a filler layer about the first micro device and between the first micro device and at least one second micro device.
- One embodiment includes fabricating at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light within the active area of the sub-pixel.
- In one case, the reflective layer is fabricated as an electrode of the micro device
- In one case, the patterning of the filler layer further patterns the filler layer about a further sub-pixel.
- In another embodiment, the patterning of the filler layer further is performed with a dielectric filler material.
- According to another aspect, there is provided an integrated device comprising: a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate; and a patterned filler layer formed about a first micro device of a first sub-pixel and between the first micro device and at least one second micro device, the patterned filler layer extending an active area of the first sub-pixel to an area larger than an area of the first micro device.
- In one case, the integrated device further comprises: at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light to the active area of the first sub-pixel.
- In one case, the reflective layer is an electrode of the micro device.
- In one embodiment, the patterned filler layer is formed about a further sub-pixel.
- According to a further aspect there is provided a method of integrated device fabrication, the device comprising a plurality of pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising: integrating at least one micro device into a receiver substrate; and subsequently to the integration of the at least one micro device, integrating at least one thin-film electro-optical device into the receiver substrate.
- In some embodiments integrating the at least one thin-film electro-optical device comprises forming an optical path for the micro device through all or some layers of the at least one electro-optical device.
- In some embodiments integrating the at least one thin-film electro-optical device is such that an optical path for the micro device is through a surface or area of the integrated device other than a surface or area of the electro-optical device.
- Some embodiments further comprise fabricating an electrode of the thin-film electro-optical device, the electrode of the thin-film electro-optical device defining an active area of at least one of a pixel and a sub-pixel.
- Some embodiments further comprise fabricating an electrode which serves as a shared electrode of both the thin-film electro-optical device and the light emitting micro device.
- In one embodiment, one of the micro device electrodes can serve as the reflective layer.
- In another embodiment, the active area can consist of a few sub-pixels or pixels.
- The active area can be larger, smaller, or the same size as the pixel (or sub-pixel) area.
- In this description pixel active area and sub-pixel active area are used interchangeably. However, it is clear to one skilled in the art that the pixel and/or sub-pixel can be used in all the embodiments described here.
- In another embodiment, thin film electro-optical devices are deposited onto the receiver substrate after the micro devices are integrated into the receiver substrate.
- In one embodiment, an optical path is developed for the micro device to emits (or absorb) light through all or some layers of the electro-optical device.
- In another embodiment, the optical path for the micro device is not through all or some layers of the electro-optical device.
- In one embodiment, the electro-optical device is a thin film device.
- In another embodiment, the electrode of the electro-optical device is used to define the active area of the pixel (or sub-pixel).
- In another embodiment, at least one of the electro-optical device electrodes is shared with the micro-device electrode.
- In one embodiment, color conversion material covers the surface and surrounds partially (or fully) the body of the micro device.
- In one embodiment, the bank structure separates the color conversion materials.
- In another embodiment, color conversion material covers the surface (and/or partially or fully the body of) the active area.
- In one embodiment, the micro devices on donor substrate are patterned to match the array structure in the receiver (system) substrate. In this case, all the devices in part (or all) of the donor substrate are transferred to the receiver substrate.
- In another embodiment, VIAs are created in the donor substrate to couple the micro devices on the donor substrate with the receiver substrate.
- In another embodiment, the donor substrate has more than one micro device type and at least in one direction the pattern of the micro device types on the donor substrate matches partially or fully the pattern of the corresponding areas (or pads) on the system substrate.
- In another embodiment, the donor substrate has more than one micro device type and at least in one direction the pitch between different micro devices in donor substrate is a multiple of the pitch of the corresponding areas (or pads) on the system substrate.
- In another embodiment, the donor substrate has more than one micro device type. At least in one direction, the pitch between two different micro devices matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate.
- In one embodiment, the pattern of different micro device types on the donor substrate creates a two dimensional array of each type where the pitch between each array of different types matches the pitch of the corresponding areas on the system substrate.
- In another embodiment, the pattern of different micro device types on the donor substrate creates a one dimensional array where the pitch of the arrays matches the pitch of the corresponding areas (or pads) on the system substrate.
- The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.
- The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.
-
FIG. 1 shows a receiver substrate with contact pads, and an array of transferred micro-devices attached to the receiver substrate. -
FIG. 2A shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, and conformal dielectric and reflective layers on top. -
FIG. 2B shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, and patterned conformal dielectric and reflective layers. -
FIG. 2C shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, patterned conformal dielectric and reflective layers, and a black matrix layer formed between adjacent micro-devices. -
FIG. 3A shows a receiver substrate with contact pads, an array of transferred micro-devices attached to the receiver substrate, patterned conformal dielectric and reflective layers, a black matrix layer, and a transparent conductive layer deposited on the substrate. -
FIG. 3B shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate and optical reflective components for light outcoupling enhancement. -
FIG. 3C shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate and concave contact pads for light outcoupling enhancement. -
FIG. 3D shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate in a bottom emission configuration. -
FIG. 3E shows a receiver substrate with an integrated array of transferred micro-devices attached to the receiver substrate. -
FIG. 4A shows a receiver substrate with transferred micro-devices, a conformal dielectric layer, and a connected reflective layer. -
FIG. 4B shows a receiver substrate with transferred micro-devices, conformal dielectric layer, connected reflective layer, and a transparent conductive layer deposited on the substrate. -
FIG. 5 shows a receiver substrate with transferred micro-devices and a patterned filler which defines the pixels (or sub-pixels). -
FIG. 6A shows a pixelated filler structure covering all sub-pixels in at least one pixel (for example covering both sub-pixels for a pixel made of two sub-pixels). -
FIG. 6B shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, and patterned conformal dielectric and reflective layers around the pixel. -
FIG. 6C shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, patterned conformal dielectric and reflective layers around the pixel, and a black matrix layer wrapped around the pixel. -
FIG. 6D shows a pixel made of two sub-pixels, a filler layer which is patterned to define the pixel, patterned conformal dielectric and reflective layers around the pixel, a black matrix layer wrapped around the pixel, and a transparent conductive layer deposited on the substrate. -
FIG. 6E shows a pixel made of two sub-pixels with reflective optical components on the receiver substrate for better light outcoupling. -
FIG. 6F shows a pixel made of two sub-pixels with concave contact pads on the receiver substrate. -
FIG. 6G shows a pixel made of two sub-pixels with a bottom emission configuration. -
FIG. 6H shows a pixel made of two sub-pixels with a bottom emission configuration, a common top electrode, and side reflectors. -
FIG. 7 shows a receiver substrate with two contact pads. -
FIG. 8 shows a receiver substrate with a transferred micro device bonded to one of the contact pads. -
FIG. 9 shows the integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure. -
FIG. 10 shows another example of an integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure. -
FIG. 11 shows an example of the integration of a transferred micro-device with an electro-optical thin film device in a hybrid structure with a common top electrode. -
FIG. 12 shows an embodiment for the integration of a transferred micro-device with an electro-optical thin film device in a dual surface hybrid structure with both top and bottom transparent electrodes. -
FIG. 13A shows another embodiment for a system substrate and an integrated micro device with thin film electro-optical device. -
FIG. 13B shows another embodiment of a system substrate and an integrated micro device with a thin film electro-optical device. -
FIG. 14A shows a modified embodiment of a system substrate and an integrated micro device with two thin film electro-optical devices. -
FIG. 14B shows an example of a system substrate and an integrated micro device with two thin film electro-optical devices and a reflective layer on the receiver substrate. -
FIG. 15 illustrates a cross section of a system substrate and a micro device substrate. -
FIG. 16 shows the alignment step for a system substrate and a micro device substrate in a transfer process. -
FIG. 17 shows the bonding step for a system substrate and a micro device substrate in a transfer process. -
FIG. 18 shows the micro device substrate removal step for a system substrate and a micro device substrate in a transfer process. -
FIG. 19 shows the sacrificial layer removal step for a system substrate and a micro device substrate in a transfer process. -
FIG. 20 shows the common electrode formation step for a system substrate and a micro device substrate in a transfer process. -
FIG. 21 is a cross section of a micro device substrate with a filler layer(s). -
FIG. 22 is a cross section of a micro device substrate covered with a support layer. -
FIG. 23 shows the micro device substrate removal step for a micro device substrate in a transfer process. -
FIG. 24A shows the sacrificial/buffer layer removal step for a micro device substrate in a transfer process. A system substrate with contact pads is shown as well. -
FIG. 24B shows the exposed micro devices after removal of the sacrificial/buffer layer. -
FIG. 25 shows the bonding step for a system substrate and a micro device substrate in a transfer process. -
FIG. 26A shows the supporting layer removal step for a micro device substrate in a transfer process. A system substrate with contact pads and transferred micro devices is shown as well. -
FIG. 26B shows the exposed micro devices after removal of the supporting layer and the filler layer. -
FIG. 27 is a cross section of a micro device substrate covered with a filler layer. -
FIG. 28A is a cross section of a micro device substrate with via holes in the substrate and the sacrificial layer. -
FIG. 28B is the cross section shown inFIG. 28A , after removal of the buffer layer. -
FIG. 29 is a cross section of a micro device substrate with via holes in the substrate and the sacrificial layer covered by an insulating layer. -
FIG. 30 is a cross section of a micro device substrate with a conductive layer filled via holes in the substrate and the sacrificial layer. -
FIG. 31 is a cross section of a micro device substrate with a common top electrode. -
FIG. 32 is a cross section of an integrated system substrate with a common top electrode. -
FIG. 33A shows a two dimensional arrangement of micro devices in a donor substrate. -
FIG. 33B is a cross section of a system substrate and a micro device substrate. -
FIG. 34 is a cross section of a bonded system substrate and micro device substrate. -
FIG. 35 shows the laser lift-off step for a micro device substrate in a transfer process. -
FIG. 36 is a cross section of a system substrate and a micro device substrate after the selective transfer process. -
FIG. 37 shows an integrated system substrate with a common top electrode. -
FIG. 38A is a cross section of a micro device substrate with micro devices having different heights. -
FIG. 38B is the cross section shown inFIG. 38A after the buffer layer has been patterned. -
FIG. 39 is a cross section of a micro device substrate with a filler layer. -
FIG. 40 shows the alignment step for a system substrate with grip mechanisms and a micro device substrate in a transfer process. -
FIG. 41A shows a two dimensional arrangement of micro devices in a donor substrate. -
FIG. 41B is a cross section of a system substrate and a micro device substrate with different pitches. -
FIG. 42 shows the selective micro device transfer process for a system substrate and a micro device substrate with different pitches. -
FIG. 43 is a cross section of a system substrate and a micro device substrate with different pitches. -
FIG. 44 shows the selective micro device transfer process for a system substrate and a micro device substrate with different pitches. -
FIG. 45 shows an integrated micro device substrate. -
FIG. 46A shows the transfer process of micro devices to a system substrate with a planarization layer, a common top electrode, bank structures, and color conversion elements. -
FIG. 46B shows the structure ofFIG. 46A with the addition of a common electrode formed on the planarization layer. -
FIG. 47 shows a structure with color conversion for defining the color of pixels. -
FIG. 48 shows a structure with conformal common electrode and color conversion separated by a bank layer. -
FIG. 49 shows a structure with conformal color conversion separated by a bank layer. -
FIG. 50 shows a structure with color conversion elements on the common electrode without the bank layer. -
FIG. 51 shows a structure with conformal common electrode and color conversion. -
FIG. 52 shows a structure with conformal color conversion elements formed directly on the micro devices. -
FIG. 53A shows a structure with color conversion for defining pixel color, a planarization layer, and a common transparent electrode. -
FIG. 53B shows the structure ofFIG. 53A after forming the encapsulation layer. -
FIG. 54A shows a structure with color conversion for defining pixel color and a separate substrate for encapsulation. -
FIG. 54B shows the structure ofFIG. 54B after the substrate coated with the encapsulation layer is bonded to the integrated system substrate. -
FIG. 55A shows a structure with a system substrate with contact pads, and a separate donor substrate with micro devices. -
FIG. 55B shows the structure ofFIG. 55A after transfer of the micro devices to the system substrate. -
FIG. 55C shows the structure ofFIG. 55B after post processing to deposit a common electrode and color conversion layers. - While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.
- The process of developing a system based on micro devices consists of pre-processing the devices on a donor substrate (or a temporary substrate), transferring the micro devices from the donor substrate to the receiver substrate, and post processing to enable device functionality. The pre-processing step may include patterning and adding bonding elements. The transfer process may involve bonding of a pre-selected array of micro devices to the receiver substrate followed by removing the donor substrate. Several different selective transfer processes have already been developed for micro devices. After the integration of the micro devices into the receiving substrate, additional post processes may be performed to make required functional connections.
- In this disclosure, “emissive device” is used to describe different integration and post processing methods. However, it is clear for one skilled in the art that other devices such as sensors can be used in these embodiments. For example, in case of sensor micro devices, the optical path will be similar to emissive micro devices but in reverse direction.
- Some embodiments of this disclosure are related to post-processing steps for improving the performance of the micro devices. For example, in some embodiments, the micro device array may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, MEMS (micro-electro-mechanical systems), and/or other electronic components. The receiving substrate may be, but is not no limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical micro devices such as LEDs, a component of a display, for example a driving circuitry backplane. In these embodiments, in addition to interconnecting the micro devices, post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices.
- In one embodiment, the active area of the pixel (or sub-pixel) is extended to be larger than the micro device by using fillers (or dielectric). Here, the filler is patterned to define the pixel's active area (the active area is the area that emits light or is absorbing input light). In another embodiment, reflective layers are used to confine the light within the active area.
- In one embodiment, the reflective layer can be one of the micro device electrodes.
- In another embodiment, the active area can consist of a few sub-pixels or pixels.
- The active area can be larger, smaller, or the same size as the pixel (sub-pixel) area.
- In another embodiment, thin film electro-optical devices are deposited into the receiver substrate after the micro devices are integrated into the receiver substrate.
- In one embodiment, an optical path is developed for the micro device to emit (or absorb) light through all or some layers of the electro-optical device.
- In another embodiment, the optical path for the micro device is not through all or some layers of the optoelectronic device.
- In one embodiment, the optoelectronic device is a thin film device.
- In another embodiment, the electrode of the electro-optical device is used to define the active area of the pixel (or sub-pixel).
- In another embodiment, at least one of the electro-optical device electrodes is shared with the micro-device electrode.
- In one embodiment color conversion material covers the surface and surrounds partially (or fully) the body of the micro device.
- In one embodiment, the bank structure separates the color conversion materials.
- In another embodiment color conversion material covers the surface (and/or partially or fully the body of) the active area.
- In one embodiment, the micro devices on donor substrate are patterned to match the array structure in the receiver (system) substrate. In this case, all the devices in part (or all) of the donor substrate are transferred to the receiver substrate.
- In another embodiment, VIAs are created in the donor substrate to couple the micro devices on the donor substrate with the receiver substrate.
- In another embodiment, the donor substrate has more than one micro device types and at least in one direction the pattern of the micro device types on the donor substrate matches partially or fully the pattern of the corresponding areas (or pads) on the system substrate.
- In another embodiment, the donor substrate has more than one micro device types and at least in one direction the pitch between different micro devices in donor substrate is a multiple of the pitch of the corresponding area (or pads) on the system substrate.
- In another embodiment, the donor substrate has more than one micro device type. At least in one direction, the pitch between two different micro devices matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate.
- In one embodiment, the pattern of different micro device types on the donor substrate creates a two dimensional array of each type where the pitch between each array of different types matches the pitch of the corresponding areas on the system substrate.
- In another embodiment, the pattern of different micro device types on the donor substrate creates a one dimensional array where the pitch of the arrays matches the pitch of the corresponding areas (or pads) on the system substrate.
-
FIG. 1 shows areceiver substrate 100,contact pads micro devices receiver substrate 100. Contact pads 101 where micro devices 102 have been transferred, are located in an array onreceiver substrate 100. Micro devices 102 are transferred from a donor substrate and bonded to the contact pads 101. Micro devices 102 can be any micro device that may typically be manufactured in planar batches including but not limited to LEDs, OLEDs, sensors, solid state devices, integrated circuits, MEMS, and/or other electronic components. - As depicted in
FIG. 2A , in one embodiment where the micro devices 102 are micro LEDs, aconformal dielectric layer 201 and areflective layer 202 may be formed over the bonded micro LEDs. In some embodiments, theconformal dielectric layer 201 is approximately 0.1-1 μm thick and it may be deposited by any of a number of different thin film deposition techniques. Theconformal dielectric layer 201 isolates the micro LED sidewalls from thereflective layer 202. In addition, thedielectric layer 201 passivates and protects the micro LED sidewalls. Theconformal dielectric layer 201 may also cover the top surface of thereceiver substrate 100 between adjacentmicro LED devices reflective layer 202 may be deposited over thedielectric layer 201. Thereflective layer 202 may be a single layer or made up of multiple layers. A variety of conductive materials may be used as thereflective layer 202. In some embodiments, the conformalreflective layer 202 may be a metallic bilayer with a total thickness up to 0.5 μm. - Referring to
FIG. 2B , thedielectric layer 201 andreflective layer 202 may then be patterned by using for example lithographic patterning and etching to partially expose the top surface of micro LEDs 102. In one embodiment where the micro LEDs are integrated into a backplane of a display system, referring also toFIG. 2C , ablack matrix 203 may be formed between adjacent micro LEDs 102 and on thereflective layer 202 to reduce the reflection of the ambient light. In one example theblack matrix 203 may be a layer of resins such as polyimide or polyacrylic in which particles of black pigment such as carbon black have been dispersed. In some embodiments, the thickness of theblack matrix 203 may be 0.01-2 μm. This layer may be patterned and etched so as to expose the top surface of the micro LEDs 102 as shown inFIG. 2C . Optionally, the thickness of theblack matrix 203 may be engineered to planarize theintegrated substrate 100. In another embodiment, a planarization layer which may be made of organic insulating material is formed and patterned to planarize the backplane substrate. - Referring to
FIG. 3A , a transparentconductive layer 301 may be conformally deposited on the substrate, covering theblack matrix 203 and the top surface of micro LEDs 102. In some embodiments, thetransparent electrode 301 may be 0.1-1 um thick layers of oxides, including but not limited to indium tin oxide (ITO) and Aluminum doped Zinc Oxide. In a case where the integrated assembly is a display structure, thetransparent electrode 301 may be the common electrode of the micro LED devices 102. - Optionally, the
reflective layer 202 may be used as a conductivity booster for thetransparent electrode 301. In this case, part of the reflective layer may not be covered withblack matrix 203, or other planarization layers, so that thetransparent electrode layer 301 may connect to thereflective layer 202. - In another embodiment shown in
FIG. 3B , a reflective or other type ofoptical component 302 may be formed on thesubstrate 100 to enhance outcoupling of light produced bymicro devices common contact 301 is transparent to allow light output through this layer. These structures may be referred as top emission structures. - Referring to
FIG. 3C , the contact pad 101 may be formed to have a concave or other shaped structure to enhance the outcoupling of light produced by microdevices 102. The contact pad form is not limited to the concave form and may have other forms depending on the micro device light emission characteristics. - In an embodiment, referring to
FIG. 3D , the structure is designed to output light from the substrate. In these bottom emission structures, thesubstrate 100 may be transparent and thecommon electrode 303 is designed to be reflective for better light extraction. - In another embodiment shown in
FIG. 3E , thereflective layer 202 may be extended to cover the micro devices and act as the common top electrode as well. - Referring to
FIG. 4A , in another embodiment, thedielectric layer 201 may be deposited and patterned before forming thereflective layer 202. As shown inFIG. 4 , this may allow a direct contact between micro LEDs 102 and thereflective layer 202 which may be used as a common top contact for the micro devices 102.Black matrix 203 or alternatively a planarization layer may be used. - Referring to
FIG. 4B , in other embodiments, a commontransparent electrode 301 or/and other optical layers may be deposited on top of thesubstrate 100 to enhance conductivity and/or light out coupling. - One of the main challenges with micro optoelectronic devices is the empty space between adjacent micro devices. Display systems with this structural characteristic may create an image artifact called the “screen door effect.” In one embodiment, the micro device sizes may be optically extended to be the same or larger than the micro device size. In one embodiment shown in
FIG. 5 , after transferring the array of micro devices 102 from the donor to thereceiver substrate 100,transparent filler 501 is deposited and patterned to define the pixel (or sub-pixel). In one example, the filler size can be the smaller or the maximum size possible in a pixel (or sub-pixel) area. In another example, the filler size may be larger than the pixel or sup-pixel area. The filler may have a different or a similar shape as the pixel area on the system substrate. The processes illustrated inFIG. 3 andFIG. 4 may then be applied to improve the light extraction from the micro devices. - Referring to
FIG. 6A , in an embodiment where the pixel 601 is made of twosub-pixels filler 501 is patterned to define the active area of the pixel 601 (active area being defined as the area from which the display emits light). Here, the active area can be smaller, larger, or the same size as the pixel (or sub-pixel) area. As shown inFIG. 6B ,FIG. 6C , andFIG. 6D processes mentioned inFIG. 2 andFIG. 3 may be applied. This configuration manages the discoloration at the edges due to the separation between sub-pixels - Referring to
FIG. 6B , adielectric layer 201 and areflective layer 202 may be formed around over pixel 601. - Referring also to
FIG. 6C , ablack matrix 203 may be formed between adjacent pixels and around each pixel to reduce the reflection of the ambient light. - Referring to
FIG. 6D , a transparentconductive layer 301 may be deposited on the substrate, covering theblack matrix 203 and the top surface ofmicro LEDs - In another embodiment shown in
FIG. 6E , reflective or otheroptical component 602 may be formed on thesubstrate 100 to enhance outcoupling of light produced bymicro devices common contact 301 is transparent for the light to output through this layer. These structures may be referred to as top emission structures. - Referring to
FIG. 6F , the contact pad 101 may be formed to have a concave structure to enhance the outcoupling of light produced by micro devices 601. The contact pad form is not limited to the concave form and may have other forms depending on the micro device light emission characteristics. - Referring to
FIG. 6G , in another embodiment, the structure is designed to output light from the substrate. In these bottom emission structures, thesubstrate 100 may be transparent and thecommon electrode 303 is designed to be reflective for better light extraction. - In another embodiment shown in
FIG. 6H , thereflective layer 202 may be extended to cover the micro devices and act as the common top electrode as well. - In other embodiments, the aforementioned pixel definition structure can cover more than one pixel (or sub-pixel).
- In another case, a reflective layer or the contact pads on the receiving substrate may be used to cover the receiving substrate and create a reflective area before transferring the micro devices for better light out coupling.
- In all aforementioned embodiments, the reflective layer can also be opaque. In addition, the reflective layers can be used as one of the micro device electrodes or as one of the system substrate connections (electrode, signal, or power line). In another embodiment, the reflective layer can be used as a touch electrode. The reflective layers can be patterned to act as a touch screen electrode. In one case, they can be patterned in vertical and horizontal directions to form the touch screen crossing electrode. In this case, one can use a dielectric between vertical and horizontal traces.
- In another embodiment, a thin film electro-optical device is integrated into the receiver substrate after the micro device arrays have been transferred to the receiver substrate.
-
FIG. 7 shows areceiver substrate 100 and contact pads 702 upon which the micro device arrays are transferred and into which the thin film electro-optical device is integrated in a number of hybrid structure embodiments. - Referring to
FIG. 8 ,micro device 801 may be transferred and bonded to thebonding pad 702 a of thereceiver substrate 100. In one case, as shown inFIG. 9 adielectric layer 901 is formed over thesubstrate 100 to cover the exposed electrodes and conductive layers. Lithography and etching may be used to pattern thedielectric layer 901.Conductive layer 902 is then deposited and patterned to form the bottom electrode of the thin film electro-optical device 904. If there is no risk of unwanted coupling betweenbottom electrode 902 and other conductive layers in the receiver substrate, thedielectric layer 901 may be eliminated. However, this dielectric layer can act as planarization layer as well to offer better fabrication of electro-optical devices 904. - Still referring to
FIG. 9 , abank layer 903 is deposited on thesubstrate 100 to cover the edges of theelectrode 902 and themicro device 801. Thin film electro-optical device 904 is then formed over this structure. Organic LED (OLED) devices are an example of such a thin film electro-optical device which may be formed using different techniques such as but not limited to shadow mask, lithography, and printing patterning. Finally, thetop electrode 905 of the electro-opticalthin film device 904 is deposited and patterned if needed. - In an embodiment where the micro devices' 801 thickness is significantly high, cracks or other structural problems may occur within the
bottom electrode 902. In these embodiments, a planarization layer may be used in conjunction with or without thedielectric layer 901 to address this issue. - In another embodiment shown in
FIG. 10 , themicro device 801 can have adevice electrode 1001. This electrode can be common between other micro devices in the system substrate. In this case, the planarization layer (if present) and/orbank layer 903 covers theelectrode 1001 to avoid any shorts between the electro-optical device 904 anddevice electrode 1001. - Referring to
FIG. 11 , in one embodiment,top electrode 905 of the thin film electro-optical device 904 may be connected to themicro device 801 through an opening in the planarization layer. In this case, the electro-optical device 904 may be formed selectively so that it is not covering this opening. - In another case, the bottom electrode of the micro device can be shared between the thin film electro-optical device and the transferred micro device.
- Referring to
FIG. 12 , in another example, thebottom electrode 902 of the thin film electro-optical device 904 can be expanded over themicro device 801. In case themicro device 801 needs to have a transparent path to the outside through its top electrode, the bottom electrode 902 (if not transparent) needs to have an opening over the micro device (for example as shown inFIG. 13A in association with another embodiment). In this case, the opening can be covered by thebank layer 903 as well. The opening is not limited to the specific structure illustrated inFIG. 12 and can be developed with different methods. - Still referring to
FIG. 12 , themicro device 801 can have a transparent path through thesubstrate 100 if electrode 702 is transparent. In a case where a transparent path is required through its top electrode, either thebottom electrode 902 and the micro device top electrode need to be transparent or there needs to be opening in thebottom electrode 902.FIG. 13A shows a layout structure where thebottom electrode 902 has an opening to allow a transparent path through thetop electrode 905. There can be anopening 1301 in thebank layer 903 for the commontop electrode 905. If there is no commontop electrode 905 and if thebank layer 903 is transparent, the opening in thebank layer 903 is not needed. In some embodiments, if thetop electrode 905 is also opaque, an opening in thetop electrode 905 is also needed for top emission. - Referring to
FIG. 13B , in another embodiment, to provide a transparent path for themicro device 801, thebottom electrode 902 does not cover themicro device 801. There can be anopening 1301 in thebank layer 903 for a common top electrode. If there is no common electrode and thebank layer 903 is transparent, the opening in thebank layer 903 is not needed. - In another case, the contact of the thin film electro-optical device can be extended to act as reflective layer. As can be seen in
FIG. 14A , the two side-by-side pixels can act to confine the light generated by themicro device 801 in the pixel. In another embodiment shown inFIG. 14B , thereflective layer 1401 on the surface of thesubstrate 100 can reflect more of the lights toward thetop electrode 905. As a result, the out coupling of the light generated by themicro device 801 is enhanced. In this case, the best practice is either to make both top and bottom electrode of the thin film electro-optical device transparent, or make openings if these electrodes are opaque. - In another embodiment, the thin film electro-optical devices and micro devices can be on two opposite sides of the system substrate. In this case, the system substrate circuitry can either be on one side of the system substrate and connected to the other side through contact holes or, the circuits can be on both sides of the system substrate.
- In another case, the micro device can be on one system substrate and the thin film electro-optical device on another system substrate. These two substrates may then be bonded together. In this case, the circuit can be on one of the system substrates or on both substrates.
- This document also discloses various methods for the integration of a monolithic array of micro devices into a system substrate or selective transferring of an array of micro devices to a system substrate. Here, the proposed processes are divided into two categories. In the first category, the pitch of the bonding pads on the system substrate is the same as the pitch of the bonding pads of the micro devices. In the second category, bonding pads on the system substrate have a larger pitch compared to that of the micro devices. For the first category, three different schemes of integration or transfer are presented
- 1. Front-side Bonding
- 2. Back-side bonding
- 3. Substrate Through via Bonding.
- In this embodiment micro-devices may be of the same type or different types in terms of functionality. In one embodiment, micro-devices are micro-LEDs of the same color or of a number of different colors (e.g., Red, Green, and Blue), and the system substrate is the backplane, controlling individual micro-LEDs. Such multi-color LED arrays are fabricated directly on a substrate or transferred to a temporary substrate from the growth substrate. In one example shown in
FIG. 15 ,RGB micro-LED devices buffer layer 1502 and thesubstrate 1501. In one case, thesystem substrate 1506 havingcontact pads 1507 can be aligned (FIG. 16 ) and bonded to themicro device substrate 1501 as shown inFIG. 17 . After removing the micro-device substrate 1501 (FIG. 18 ) and sacrificial/buffer layer 1502 (FIG. 19 ), a filler dielectric coating 2001 (e.g., Polyimide resist) may be spin-coated/deposited on the integrated sample (FIG. 20 ). This step may be followed by an etching process to reveal the tops of the micro-LED devices. In the case of micro-LED devices, a commontransparent electrode 2002 may be deposited on the sample. In another embodiment, a top electrode may be deposited and patterned to isolate micro devices for subsequent processes. - In another embodiment, as shown in
FIG. 21 themicro devices sacrificial layer 1502. Adielectric filler layer 2101 is deposited/spin-coated on the substrate to fully cover the micro devices. In one example illustrated inFIG. 21 , this step is followed by an etching process to reveal the tops of themicro devices FIG. 22 , a thick mechanical supportinglayer 2102 is then deposited, grown or bonded on the tops of the sample. Here, thefiller layer 2101 can be a black matrix layer or a reflective material. Also, before depositing the mechanical support, one can deposit an electrode (either as a patterned or a common layer). The mechanical support layer is then deposited. In the case of optoelectronic devices such as LEDs, the mechanical support layer needs to be transparent. As shown inFIG. 23 andFIG. 24 , themicro device substrate 1501 or sacrificial/buffer layer is then removed using various processes such as laser lift-off or etching. In one case, the thickness of the substrate is initially reduced to a few micrometers by processes such as but not limited to deep reactive ion etching (DRIE). The remaining substrate then is removed by processes such as but not limited to a wet chemical etching process. In this case, the buffer/sacrificial layer 1502 may act as an etch-stop layer to ensure a uniform etched sub-surface and to avoid any damage to the micro devices. After removing thebuffer layer 1502 as shown inFIG. 24 , another etching (e.g., RIE) is performed to expose the micro devices. One may deposit and pattern a metallic layer to serve as the upper contact and bond pads for the micro-devices if they haven't been formed during the micro device fabrication. Thesystem substrate 1506 havingcontact pads 1507 can then be aligned and bonded to the micro device array as shown inFIG. 25 . Depending on the type and functionality of the micro devices, themechanical supporting layer 2102 andfiller layer 2101 may be then removed as shown inFIG. 26A andFIG. 26B . - In another embodiment, through substrate vias are implemented to make contacts to the back of the micro devices.
- Referring to
FIG. 27 , in one embodiment, themicro devices buffer layer 1502. This buffer layer may function as an etch-stop layer as well. Adielectric layer 2701 is deposited as a filler layer. - Referring to
FIG. 28A andFIG. 28B , using processes such as but not limited to photolithography, patterns are formed on the backside of thesubstrate 1501. In one embodiment, a method such as DRIE is used to make through substrate holes in thesubstrate 1501.Buffer layer 1502 which may act as an etchstop layer may be removed using for example a wet-etch process, as illustrated inFIG. 28B . - Referring to
FIG. 29 , an insulatingfilm 2901 is deposited on the back of thesubstrate 1501. This insulatinglayer 2901 may be partially removed from back side of themicro devices - Referring to
FIG. 30 , the through holes are filled with aconductive material 3001 using processes such as but not limited to electroplating. Here, the vias may act as the micro device contacts and bonding pads. - As illustrated in
FIG. 31 , acommon front contact 3101 of themicro devices front contact 3101. - Referring to
FIG. 32 , themicro device substrate 1501 is then aligned and bonded to thesystem substrate 1506 havingcontact pads 1507 which in this example may be a backplane controlling individual devices. - In another embodiment, micro devices have been fabricated on a substrate with arbitrary pitch length to maximize the production yield. For example the micro devices may be multi-color micro-LEDs (e.g., RGB). The system substrate for this example may be a display backplane with contact pads having a pitch length different than those of the micro-LEDs.
- Referring to
FIG. 33A , in one embodiment, thedonor substrate 1501 hasmicro device types dimensional arrays 3304 in which for eachmicro device pitch 3305 matches the pitch of the corresponding areas (or pads) on the receiver (or system) substrate. - As an example, in one embodiment shown in
FIG. 33B , thepitch 3404 ofcontact pads 1507 is two times larger than thepitch 3402 of themicro devices 3401 as shown inFIG. 33 . - Referring to
FIG. 34 , thesystem substrate 1506 andmicro device substrate 1501 are brought together, aligned and put in contact. - As shown in
FIG. 35 andFIG. 36 , methods such as laser lift-off (LLO) may be used to selectively transfer themicro devices 3401 to thecontact pads 3403 on thesystem substrate 1506. As shown inFIG. 37 , transfer may be followed by depositing afiller layer 3701 and a conformalconductive layer 3702 on top of the system substrate as the common electrode. - In another embodiment shown in
FIG. 38 , abuffer layer 3801 is necessary as a material template for the fabrication ofmicro devices - Still referring to
FIG. 38A andFIG. 38B , thebuffer layer 3801 is deposited on thesacrificial layer 1502 and patterned to isolatemicro devices sacrificial layer 1502 may be patterned as well. - In one embodiment, instead of isolating individual micro devices, groups of micro devices may be isolated from one another (as shown in
FIG. 38 ) to facilitate the transfer process. - Referring to
FIG. 39 , a fillingmaterial 3901 such as but not limited to polyimide may be spin coated on the substrate to fill the gap between the individual micro devices. This filling step insures the mechanical strength during the transfer process. This is particularly important when a process like laser lift-off is used to detach micro devices from the carrier substrate. - Referring to
FIG. 40 , micro devices may not have the same height which make it difficult to bond them to the system substrate. In these cases, one can implement anelectrostatic grip mechanism 4001 or other grip mechanisms in the system substrate to temporarily keep the micro devices on the system substrate for the final bonding steps. The grip mechanism may be local for micro devices or a global grip for a group of micro devices as in the case of same-pitch transfer for the whole wafer. The grip mechanism may be on a layer above the contact electrode. In this case, a planarization layer may be used. - In one embodiment, referring to
FIG. 41A , the pattern of differentmicro device types arrays 4101 defined as the center-to-center distance between adjacent arrays) matches the pitch of the corresponding area on the system substrate. - In one embodiment shown in
FIG. 41B andFIG. 42 , whensub-device pitch 4101 is larger than the normal distance between fabricated individual micro devices on their substrate (e.g., in large displays),micro device substrate 1501 is laid out in the form of two-dimensional single color arrays. Here, thecontact pad pitch 4102 and the microdevice array pitch 4103 are the same. Using this technique, one may relax the micro device fabrication requirements and reduce the selective transferring process as compared to that described above. -
FIG. 43 andFIG. 44 shows an alternative pattern where micro devices are not formed in two-dimensional groups and the different micro devices uniformly placed across the substrate as it shown inFIG. 43 for three different micro devices. - Referring to
FIG. 45 , in another embodiment, micro devices are first transferred to a conductive semi-transparentcommon substrate 4501, then they are bonded to asystem substrate 4502. - In some embodiments where the micro devices are optical devices such as LEDs, one can use either color conversion or color filters to define different functionality (different colors in the case of pixels). In this embodiment, two or more contact pads on the system substrate are populated with the same type of optical device. Once in place, the devices on the system substrates are then differentiated by different color conversion layers.
- Referring to
FIG. 46A andFIG. 46B , in one embodiment, after transferringmicro devices 1503 to thesystem substrate 1506, the whole structure is covered by aplanarization layer 4601. Acommon electrode 4602 is then formed on theplanarization layer 4601. The planarization layer can be the same height as, taller than, or shorter than the stacked devices. If the planarization layer is shorter (or there is no planarization layer) the wall of the device can be conformally covered by passivation materials. - Referring to
FIG. 47 , abank structure 4701 is developed (especially if a printing process is used to deposit the color conversion layers). The bank can separate each pixel or just separate differentcolor conversion materials 4702. -
FIG. 48 shows an integrated structure where thecolor conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.Bank 4701 separates thecolor conversion layers 4702 and theelectrode 4602 is a common contact for all transferred micro devices. -
FIG. 49 shows an integrated structure where thecolor conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides.Bank 4701 separates the color conversion layers and contacts to the micro devices are made only through thesystem substrate 1506. -
FIG. 50 shows an integrated structure where the color conversion layer is directly formed on thecommon electrode 4602. In this case no bank layer is used. -
FIG. 51 shows an integrated structure where thecolor conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides. Theelectrode 4602 is a common contact for all transferred micro devices. In this case no bank layer is used. -
FIG. 52 shows an integrated structure where thecolor conversion layer 4702 fully covers the top of the transferred micro devices and partially covers their sides. The contacts to the micro devices are made only through the system substrate. In this case no bank layer is used. - In one embodiment, shown in
FIG. 53A andFIG. 53B , after forming thecolor conversion material 4702 on theintegrated system substrate 1506, aplanarization layer 5301 is deposited on the structure. In some cases where the color conversion material and/or other components of the integrated substrate need to be protected from environmental conditions, anencapsulation layer 5302 is formed over the whole structure. It should be noted that theencapsulation layer 5302 may be formed from a stack of different layers to effectively protect the integrated substrate from environmental conditions - Referring to
FIG. 54A andFIG. 54B , in another embodiment aseparate substrate 5401 coated with theencapsulation layer 5302 may be bonded to the integrated system substrate. - The embodiments depicted in
FIG. 53 andFIG. 54 may be combined in whichencapsulation layer 5302 is formed both on the structure and the separate substrate for more effective capsulation. - The common electrode is a transparent conductive layer deposited on the substrate in the form of a blanket. In one embodiment, this layer can act a planarization layer. In some embodiments, the thickness of this layer is chosen to satisfy both optical and electrical requirements.
- The distance between the optical devices may be chosen to be large enough so as to reduce cross-talk between the optical devices or a blocking layer is deposited between the optical devices to achieve this. In one case, the planarization layer functions also as a blocking layer.
- After the color conversion layers are deposited, different layers such as polarizers can be deposited.
- In another aspect, color filters are deposited on the color conversion layers. In this case wider color gamut and higher efficiency may be achieved. One can use a planarization layer and/or bank layer after the color conversion layer before depositing the color filter layers.
- The color filters can be larger than the color conversion layer to block any light leakage. Moreover, a black matrix can be formed between the color conversion islands or color filters.
-
FIGS. 55A, 55B, and 55C illustrate structures where the device is shared between a few pixels (or sub-pixels). Here themicro device 1503 is not fully patterned but the horizontal condition is engineered so that thecontacts 1507 define the area allocated to each pixel.FIG. 55A shows thesystem substrate 1506 withcontact pads 1507 and adonor substrate 1501 withmicro devices 1503. After themicro devices 1503 are transferred to system substrate (shown inFIG. 55B ), one can do post processing (FIG. 55C ) such as depositingcommon electrode 4602,color conversion layers 4702, color filters and so on.FIG. 55C shows one example of depositingcolor conversion layers 4702 on top of themicro device 1503. However, the methods described in this disclosure and other possible method can be used. - It is possible to add the color conversion layers as described into pixel (or sub-pixel) active areas after formation of the active area. This can offer a higher fill factor and higher performance and also avoid color leaking from the side pixel (or sub-pixel) if the active area of the pixel (or sub-pixel) is covered by reflective layers.
- While particular implementations and applications of the present disclosure have been illustrated and described, it is to be understood that the present disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of an invention as defined in the appended claims.
Claims (9)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022221950A1 (en) * | 2021-04-21 | 2022-10-27 | Vuereal Inc. | Integrating color conversion material in a microdevice |
US11664358B2 (en) | 2020-06-05 | 2023-05-30 | Au Optronics Corporation | Display apparatus |
US11777059B2 (en) | 2019-11-20 | 2023-10-03 | Lumileds Llc | Pixelated light-emitting diode for self-aligned photoresist patterning |
US12034013B2 (en) | 2020-12-21 | 2024-07-09 | Beijing Boe Display Technology Co., Ltd. | Array substrate, display panel, and electronic device |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10910350B2 (en) * | 2014-05-24 | 2021-02-02 | Hiphoton Co., Ltd. | Structure of a semiconductor array |
TWI820033B (en) * | 2015-01-23 | 2023-11-01 | 加拿大商弗瑞爾公司 | Micro device integration into system substrate |
US10700120B2 (en) * | 2015-01-23 | 2020-06-30 | Vuereal Inc. | Micro device integration into system substrate |
WO2017109768A1 (en) | 2015-12-24 | 2017-06-29 | Vuereal Inc. | Vertical solid state devices |
JP6919647B2 (en) * | 2016-03-31 | 2021-08-18 | ソニーグループ株式会社 | Display devices and electronic devices |
KR102542853B1 (en) * | 2016-04-25 | 2023-06-14 | 삼성전자주식회사 | Led display module, display apparatus and controlling method thereof |
CN109314164B (en) * | 2016-05-25 | 2022-04-15 | 朱振甫 | Semiconductor continuous array layer |
US10304375B2 (en) * | 2016-09-23 | 2019-05-28 | Hong Kong Beida Jade Bird Display Limited | Micro display panels with integrated micro-reflectors |
US10998352B2 (en) | 2016-11-25 | 2021-05-04 | Vuereal Inc. | Integration of microdevices into system substrate |
US10722729B2 (en) * | 2017-01-11 | 2020-07-28 | International Business Machines Corporation | Probe for localized neural optogenetics stimulation and neurochemistry recordings |
US11205677B2 (en) * | 2017-01-24 | 2021-12-21 | Goertek, Inc. | Micro-LED device, display apparatus and method for manufacturing a micro-LED device |
CN110709989B (en) | 2017-03-30 | 2023-12-01 | 维耶尔公司 | vertical solid state device |
US11600743B2 (en) | 2017-03-30 | 2023-03-07 | Vuereal Inc. | High efficient microdevices |
US11721784B2 (en) | 2017-03-30 | 2023-08-08 | Vuereal Inc. | High efficient micro devices |
CN109037261A (en) * | 2017-06-09 | 2018-12-18 | 美商晶典有限公司 | The manufacturing method of micro- light-emitting diode display module |
TWI633681B (en) * | 2017-06-09 | 2018-08-21 | 美商晶典有限公司 | Micro led display module manufacturing method |
TWI611573B (en) * | 2017-06-09 | 2018-01-11 | 晶典有限公司 | Micro led display module and manufacturing method thereof |
US20190058081A1 (en) * | 2017-08-18 | 2019-02-21 | Khaled Ahmed | Micro light-emitting diode (led) display and assembly apparatus |
CA2985264A1 (en) * | 2017-11-14 | 2019-05-14 | Vuereal Inc. | Integration of touch and sensing |
FR3076075B1 (en) * | 2017-12-22 | 2020-01-24 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR MANUFACTURING AN ELECTROLUMINESCENT DEVICE |
CN110612607B (en) * | 2018-03-29 | 2022-04-22 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
US10627673B2 (en) * | 2018-04-06 | 2020-04-21 | Glo Ab | Light emitting diode array containing a multilayer bus electrode and method of making the same |
TWI845621B (en) * | 2019-02-21 | 2024-06-21 | 加拿大商弗瑞爾公司 | Microdisplay and method to fabricate a microdevice array |
US11552163B2 (en) | 2019-02-22 | 2023-01-10 | Vuereal Inc. | Staggered and tile stacked microdevice integration and driving |
WO2020170222A1 (en) * | 2019-02-22 | 2020-08-27 | Vuereal Inc. | Staggered and tile stacked microdevice integration and driving |
TW202105671A (en) * | 2019-02-22 | 2021-02-01 | 加拿大商弗瑞爾公司 | Microdevice cartridge structure |
US11637219B2 (en) | 2019-04-12 | 2023-04-25 | Google Llc | Monolithic integration of different light emitting structures on a same substrate |
CN110265522B (en) * | 2019-06-28 | 2021-01-08 | 上海天马微电子有限公司 | Display panel, display device, and method for manufacturing display panel |
CN110416245B (en) * | 2019-07-31 | 2021-11-02 | 成都辰显光电有限公司 | Display panel, display device and manufacturing method of display panel |
TWI715155B (en) | 2019-08-16 | 2021-01-01 | 錼創顯示科技股份有限公司 | Micro light emitting device display apparatus and method of fabricating the same |
CN110767646B (en) * | 2019-10-31 | 2021-02-09 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
KR20220107212A (en) * | 2019-12-02 | 2022-08-02 | 뷰리얼 인크. | Creating staging on the backplane for microdevice integration |
CN111161641B (en) * | 2019-12-30 | 2021-11-23 | 重庆康佳光电技术研究院有限公司 | Narrow-frame display backboard, preparation method thereof and display |
DE112021002047T5 (en) * | 2020-03-30 | 2023-04-13 | Vuereal Inc | OFFSET ALIGNMENT AND REPAIR IN MICRO DEVICE TRANSFER |
CN112968119B (en) * | 2020-12-18 | 2022-02-18 | 重庆康佳光电技术研究院有限公司 | Chip transfer method |
CN112802940B (en) * | 2021-01-05 | 2022-03-11 | 苏州芯聚半导体有限公司 | Display substrate, manufacturing method and display device |
CN113782553B (en) * | 2021-09-01 | 2024-07-23 | 吉安市木林森光电有限公司 | Huge transfer Micro LED module, display screen and manufacturing method |
US20230335518A1 (en) * | 2022-04-13 | 2023-10-19 | Meta Platforms Technologies, Llc | Aln-based hybrid bonding |
WO2024021757A1 (en) * | 2022-07-26 | 2024-02-01 | 海信视像科技股份有限公司 | Full-color display device |
WO2024077393A1 (en) * | 2022-10-13 | 2024-04-18 | Vuereal Inc. | Black matrix integration |
CN116224650A (en) * | 2022-12-15 | 2023-06-06 | 安徽立光电子材料股份有限公司 | Light source assembly for Mini LED backlight module and manufacturing method thereof |
WO2024130438A1 (en) * | 2022-12-23 | 2024-06-27 | Vuereal Inc. | Micro-led with integrated transportation vehicles sensors |
WO2024130437A1 (en) * | 2022-12-23 | 2024-06-27 | Vuereal Inc. | Micro-leds for vehicle interior light |
WO2024130407A1 (en) * | 2022-12-23 | 2024-06-27 | Vuereal Inc. | Micro-led light strips or fixtures for the transportation industry |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130214302A1 (en) * | 2012-02-17 | 2013-08-22 | Industrial Technology Research Institute | Light emitting element and fabricating method thereof |
US20140367633A1 (en) * | 2013-06-18 | 2014-12-18 | LuxVue Technology Corporation | Led display with wavelength conversion layer |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5782399A (en) | 1995-12-22 | 1998-07-21 | Tti Testron, Inc. | Method and apparatus for attaching spherical and/or non-spherical contacts to a substrate |
US6159822A (en) * | 1999-06-02 | 2000-12-12 | Vanguard International Semiconductor Corporation | Self-planarized shallow trench isolation |
KR100853410B1 (en) | 2001-04-11 | 2008-08-21 | 소니 가부시키가이샤 | Element transfer method, element arrangement method using the same, and image display apparatus production method |
FR2838561B1 (en) | 2002-04-12 | 2004-09-17 | Commissariat Energie Atomique | PHOTODECTOR MATRIX, PIXEL ISOLATED BY WALLS, HYBRIDED ON A READING CIRCUIT |
US7053412B2 (en) * | 2003-06-27 | 2006-05-30 | The Trustees Of Princeton University And Universal Display Corporation | Grey scale bistable display |
US7307327B2 (en) | 2005-08-04 | 2007-12-11 | Micron Technology, Inc. | Reduced crosstalk CMOS image sensors |
WO2007054869A1 (en) * | 2005-11-11 | 2007-05-18 | Koninklijke Philips Electronics N.V. | Method of manufacturing a plurality of semiconductor devices and carrier substrate |
CN100576492C (en) * | 2006-09-30 | 2009-12-30 | 中芯国际集成电路制造(上海)有限公司 | Form the method for device isolation region |
CN102097357A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for making isolation structure |
JP5458307B2 (en) | 2010-03-05 | 2014-04-02 | 株式会社ジャパンディスプレイ | Electro-optic display |
CN103688385B (en) * | 2011-07-19 | 2016-05-11 | 株式会社日立制作所 | The manufacture method of organic illuminating element, light supply apparatus and organic illuminating element |
CN102683534B (en) * | 2012-05-21 | 2015-02-25 | 厦门市三安光电科技有限公司 | Vertical type alternating-current light-emitting diode device and manufacturing method thereof |
US9159700B2 (en) * | 2012-12-10 | 2015-10-13 | LuxVue Technology Corporation | Active matrix emissive micro LED display |
JP6173556B2 (en) | 2013-03-13 | 2017-08-02 | キャボット コーポレイションCabot Corporation | COATING COMPRISING FILLER-POLYMER COMPOSITION HAVING COMBINED LOW DIELECTRICITY, HIGH RESISTOR AND OPTICAL DENSITY CHARACTERISTICS, AND CONTROLLED ELECTRICAL RESISTOR, DEVICE PRODUCED THEREFROM, AND METHOD FOR PRODUCING THE SAME |
US9728124B2 (en) * | 2013-05-08 | 2017-08-08 | Apple Inc. | Adaptive RGB-to-RGBW conversion for RGBW display systems |
US8928021B1 (en) * | 2013-06-18 | 2015-01-06 | LuxVue Technology Corporation | LED light pipe |
JP2015050011A (en) * | 2013-08-30 | 2015-03-16 | 株式会社ジャパンディスプレイ | Electroluminescence device and method for manufacturing the same |
US9871350B2 (en) * | 2014-02-10 | 2018-01-16 | Soraa Laser Diode, Inc. | Manufacturable RGB laser diode source |
CN107851586B (en) * | 2015-01-23 | 2021-07-06 | 维耶尔公司 | Selective micro device transfer to a receptor substrate |
CA2887186A1 (en) | 2015-05-12 | 2016-11-12 | Ignis Innovation Inc. | Selective transferring and bonding of pre-fabricated micro-devices |
CA2890398A1 (en) | 2015-05-04 | 2016-11-04 | Ignis Innovation Inc. | Selective and non-selective micro-device transferring |
CA2880718A1 (en) | 2015-01-28 | 2016-07-28 | Ignis Innovation Inc. | Selective transfer of semiconductor device to a system substrate |
EP3387882B1 (en) * | 2015-12-07 | 2021-05-12 | Glo Ab | Laser lift-off on isolated iii-nitride light islands for inter-substrate led transfer |
-
2016
- 2016-03-04 US US15/060,942 patent/US10134803B2/en active Active
-
2017
- 2017-03-06 CN CN201780013977.9A patent/CN109075119B/en active Active
-
2018
- 2018-08-21 US US16/107,680 patent/US20180358404A1/en not_active Abandoned
-
2021
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130214302A1 (en) * | 2012-02-17 | 2013-08-22 | Industrial Technology Research Institute | Light emitting element and fabricating method thereof |
US20140367633A1 (en) * | 2013-06-18 | 2014-12-18 | LuxVue Technology Corporation | Led display with wavelength conversion layer |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11777059B2 (en) | 2019-11-20 | 2023-10-03 | Lumileds Llc | Pixelated light-emitting diode for self-aligned photoresist patterning |
US11664358B2 (en) | 2020-06-05 | 2023-05-30 | Au Optronics Corporation | Display apparatus |
US12034013B2 (en) | 2020-12-21 | 2024-07-09 | Beijing Boe Display Technology Co., Ltd. | Array substrate, display panel, and electronic device |
WO2022221950A1 (en) * | 2021-04-21 | 2022-10-27 | Vuereal Inc. | Integrating color conversion material in a microdevice |
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US20160218143A1 (en) | 2016-07-28 |
CN109075119A (en) | 2018-12-21 |
US10134803B2 (en) | 2018-11-20 |
US20210202572A1 (en) | 2021-07-01 |
CN109075119B (en) | 2023-05-26 |
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