CA2898735A1 - Hybrid calibration of bias current - Google Patents
Hybrid calibration of bias current Download PDFInfo
- Publication number
- CA2898735A1 CA2898735A1 CA2898735A CA2898735A CA2898735A1 CA 2898735 A1 CA2898735 A1 CA 2898735A1 CA 2898735 A CA2898735 A CA 2898735A CA 2898735 A CA2898735 A CA 2898735A CA 2898735 A1 CA2898735 A1 CA 2898735A1
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- CA
- Canada
- Prior art keywords
- pixel
- sub
- micro device
- integrated
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000945 filler Substances 0.000 claims abstract 11
- 239000000758 substrate Substances 0.000 claims abstract 8
- 239000010409 thin film Substances 0.000 claims abstract 7
- 238000000034 method Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 3
- 230000003287 optical effect Effects 0.000 claims 2
- 230000010354 integration Effects 0.000 claims 1
- 238000012805 post-processing Methods 0.000 abstract 2
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 238000005259 measurement Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/50—Wavelength conversion elements
Abstract
Post-processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structures such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. Dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with transferred micro devices. Color conversion layers may be integrated into the system substrate to create different outputs from the micro devices.
Description
IGNIS IGNIS
Patents Hybrid Calibration of Bias Current , IGNIS
Innovation Inc.
IGNIS Patents HYBRID CALIBRATION OF BIAS
CURRENT
Revision: 1.0 2015 IGNIS Innovation Inc., 1 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current I. Introduction Driver Figure 1: An embodiment of current-bias voltage-programmed (CBVP) display.
Figure 1 demonstrates an embodiment of current-bias voltage-programmed display. The pixel is biased with a current and programmed with video data through a driver. The main challenge is to have uniform current sources and lower cost and integrated into the display panel.
This document describe a family of current source and method of making them uniform using existing displays components.
2015 IGNIS Innovation Inc., 2 It' IC NIS IGNIS
Patents Hybrid Calibration of Bias Current Ref/Monitor =
Driver Figure 2: An embodiment of current-bias voltage-programmed (CBVP) display using display drivers to calibrate and control the current sources.
Here, the reference signal used to program (through voltage or reference current) is used to also measure the current of each current source. here the ref/monitor line is coupled to the source or drain of the transistor (or cascaded transistor structure). The gate of said transistor (or cascaded transistor structure) is coupled to the voltage (or current or charge) lines that can be controlled individually.
In one method, these lines can be connected to the source driver lines of the panel. As a result, the display timing controller program the display with one extra line.
One current sink based on this structure is demonstrated in Figure 3 based on PMOS transistors.
Using similar principle one can easily make current source with PMOS
transistor. These 2015 IGNIS Innovation Inc., 3 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current structure can be easily replaced with different types of transistor (PMOS, NMOS or CMOS) and different semiconductor materials (e.g. LTPS, Metal Oxide, etc. ).
During the programming, T3 connects the reference line (can be voltage or current) to the source of Ti and T2 connects a bias line to the gate of Ti. As a result, the storage capacitance get charged to defined value. In one method, after programming the circuit is reconfigured to discharge some of the voltage (charge) stored in the at least one of the storage capacitor as a function of the main element of the current source (sink) Ti or its related components. The calibration time in the Figure 3(b) is foi the discharge purpose. This can be also eliminated.
!bias EN __________________________________ T4 CAL
Ref/Monitor WR =
CS
Vbias = Ti VSS
Figure 3(a): An embodiment of a current sink using PMOS transistors.
In another method, the output current of the current sink/source can be measured through the ref/
monitor line. Here, T3 turns ON and redirect the current to the ref/monitor line which can be measured outside. Since ref/monitor line can be shared between different current sink/source, during measurement all the embodiments are set to zero current except the one intended for the measurement.
2015 IGNIS Innovation Inc., 4 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current Programming >:
WR
CAL
EN
Calibration Figure 3(b): An example of timing for controlling the current sink.
Figure 4 shows an example of current source using PMOS transistors. similar timing as that shown in Figure 3(b) can be used for this embodiment as well.
2015 IGNIS Innovation Inc., 5 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current Vdd = =
CS
= Ti CAL
Ref/Monitor ________________________________ = ______ EN
!bias Figure 4: An embodiment of a current source using PMOS transistors.
2015 IGNIS Innovation Inc., 6
Patents Hybrid Calibration of Bias Current , IGNIS
Innovation Inc.
IGNIS Patents HYBRID CALIBRATION OF BIAS
CURRENT
Revision: 1.0 2015 IGNIS Innovation Inc., 1 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current I. Introduction Driver Figure 1: An embodiment of current-bias voltage-programmed (CBVP) display.
Figure 1 demonstrates an embodiment of current-bias voltage-programmed display. The pixel is biased with a current and programmed with video data through a driver. The main challenge is to have uniform current sources and lower cost and integrated into the display panel.
This document describe a family of current source and method of making them uniform using existing displays components.
2015 IGNIS Innovation Inc., 2 It' IC NIS IGNIS
Patents Hybrid Calibration of Bias Current Ref/Monitor =
Driver Figure 2: An embodiment of current-bias voltage-programmed (CBVP) display using display drivers to calibrate and control the current sources.
Here, the reference signal used to program (through voltage or reference current) is used to also measure the current of each current source. here the ref/monitor line is coupled to the source or drain of the transistor (or cascaded transistor structure). The gate of said transistor (or cascaded transistor structure) is coupled to the voltage (or current or charge) lines that can be controlled individually.
In one method, these lines can be connected to the source driver lines of the panel. As a result, the display timing controller program the display with one extra line.
One current sink based on this structure is demonstrated in Figure 3 based on PMOS transistors.
Using similar principle one can easily make current source with PMOS
transistor. These 2015 IGNIS Innovation Inc., 3 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current structure can be easily replaced with different types of transistor (PMOS, NMOS or CMOS) and different semiconductor materials (e.g. LTPS, Metal Oxide, etc. ).
During the programming, T3 connects the reference line (can be voltage or current) to the source of Ti and T2 connects a bias line to the gate of Ti. As a result, the storage capacitance get charged to defined value. In one method, after programming the circuit is reconfigured to discharge some of the voltage (charge) stored in the at least one of the storage capacitor as a function of the main element of the current source (sink) Ti or its related components. The calibration time in the Figure 3(b) is foi the discharge purpose. This can be also eliminated.
!bias EN __________________________________ T4 CAL
Ref/Monitor WR =
CS
Vbias = Ti VSS
Figure 3(a): An embodiment of a current sink using PMOS transistors.
In another method, the output current of the current sink/source can be measured through the ref/
monitor line. Here, T3 turns ON and redirect the current to the ref/monitor line which can be measured outside. Since ref/monitor line can be shared between different current sink/source, during measurement all the embodiments are set to zero current except the one intended for the measurement.
2015 IGNIS Innovation Inc., 4 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current Programming >:
WR
CAL
EN
Calibration Figure 3(b): An example of timing for controlling the current sink.
Figure 4 shows an example of current source using PMOS transistors. similar timing as that shown in Figure 3(b) can be used for this embodiment as well.
2015 IGNIS Innovation Inc., 5 IGNIS IGNIS
Patents Hybrid Calibration of Bias Current Vdd = =
CS
= Ti CAL
Ref/Monitor ________________________________ = ______ EN
!bias Figure 4: An embodiment of a current source using PMOS transistors.
2015 IGNIS Innovation Inc., 6
Claims (14)
1. A method of integrated device fabrication, the integrated device comprising a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising:
extending an active area of a first sub-pixel to an area larger than an area of a first micro device of the first sub-pixel by patterning of a filler layer about the first micro device and between the first micro device and at least one second micro device.
extending an active area of a first sub-pixel to an area larger than an area of a first micro device of the first sub-pixel by patterning of a filler layer about the first micro device and between the first micro device and at least one second micro device.
2. A method according to claim 1 further comprising:
fabricating at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light within the active area of the sub-pixel.
fabricating at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light within the active area of the sub-pixel.
3. A method according to claim 2 wherein the reflective layer is fabricated as an electrode of the micro device.
4. A method according to claim 1 wherein the patterning of the filler layer further patterns the filler layer about a further sub-pixel.
5. A method according to claim 1 wherein the patterning of the filler layer further is performed with a dielectric filler material.
6. An integrated device comprising:
a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate; and a patterned filler layer formed about a first micro device of a first sub-pixel and between the first micro device and at least one second micro device, the patterned filler layer extending an active area of the first sub-pixel to an area larger than an area of the first micro device.
a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate; and a patterned filler layer formed about a first micro device of a first sub-pixel and between the first micro device and at least one second micro device, the patterned filler layer extending an active area of the first sub-pixel to an area larger than an area of the first micro device.
7. An integrated device according to claim 6 further comprising:
at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light to the active area of the first sub-pixel.
at least one reflective layer covering at least a portion of one side of the patterned filler layer, the reflective layer for confining at least a portion of incoming or outgoing light to the active area of the first sub-pixel.
8. An integrated device according to claim 7 wherein the reflective layer is an electrode of the micro device.
9. An integrated device according to claim 7 wherein the patterned filler layer is formed about a further sub-pixel.
10. A method of integrated device fabrication, the device comprising a plurality pixels each comprising at least one sub-pixel comprising a micro device integrated on a substrate, the method comprising:
integrating at least one micro device into a receiver substrate; and subsequently to the integration of the at least one micro device, integrating at least one thin-film electro-optical device into the receiver substrate.
integrating at least one micro device into a receiver substrate; and subsequently to the integration of the at least one micro device, integrating at least one thin-film electro-optical device into the receiver substrate.
11. A method according to claim 10, wherein integrating the at least one thin-film electro-optical device comprises forming an optical path for the micro device through all or some layers of the at least one electro-optical device.
12. A method according to claim 10 wherein integrating the at least one thin-film electro-optical device is such that an optical path for the micro device is through a surface or area of the integrated device other than a surface or area of the electro-optical device.
13. A method according to claim 10, further comprising fabricating an electrode of the thin-film electro-optical device, the electrode of the thin-film electro-optical device defining an active area of at least one of a pixel and a sub-pixel.
14.
A method of according to claim 10, further comprising fabricating an electrode which serves as a shared electrode of both the thin-film electro-optical device and the light emitting micro device.
A method of according to claim 10, further comprising fabricating an electrode which serves as a shared electrode of both the thin-film electro-optical device and the light emitting micro device.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2898735A CA2898735A1 (en) | 2015-07-29 | 2015-07-29 | Hybrid calibration of bias current |
| US15/060,942 US10134803B2 (en) | 2015-01-23 | 2016-03-04 | Micro device integration into system substrate |
| CN201780013977.9A CN109075119B (en) | 2015-01-23 | 2017-03-06 | Integrated device manufacturing method |
| CN202310495809.5A CN116525532A (en) | 2015-01-23 | 2017-03-06 | Integrated device manufacturing method |
| US16/107,680 US20180358404A1 (en) | 2015-01-23 | 2018-08-21 | Micro device integration into system substrate |
| US16/107,692 US10847571B2 (en) | 2015-01-23 | 2018-08-21 | Micro device integration into system substrate |
| US17/200,467 US20210202572A1 (en) | 2015-01-23 | 2021-03-12 | Micro device integration into system substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA2898735A CA2898735A1 (en) | 2015-07-29 | 2015-07-29 | Hybrid calibration of bias current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2898735A1 true CA2898735A1 (en) | 2017-01-29 |
Family
ID=57937666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2898735A Pending CA2898735A1 (en) | 2015-01-23 | 2015-07-29 | Hybrid calibration of bias current |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2898735A1 (en) |
-
2015
- 2015-07-29 CA CA2898735A patent/CA2898735A1/en active Pending
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