CN112968119B - Chip transfer method - Google Patents
Chip transfer method Download PDFInfo
- Publication number
- CN112968119B CN112968119B CN202011514635.5A CN202011514635A CN112968119B CN 112968119 B CN112968119 B CN 112968119B CN 202011514635 A CN202011514635 A CN 202011514635A CN 112968119 B CN112968119 B CN 112968119B
- Authority
- CN
- China
- Prior art keywords
- substrate
- bonding
- layer
- metal
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 229910052751 metal Inorganic materials 0.000 claims abstract description 142
- 239000002184 metal Substances 0.000 claims abstract description 142
- 239000000463 material Substances 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 7
- 239000007769 metal material Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
The invention relates to a chip transfer method. The transfer method comprises the following steps: providing a first substrate, wherein the first side of the first substrate comprises a functional area and a non-functional area, the functional area is provided with a chip, a first metal layer is formed in the non-functional area, and a first insulating medium layer covering the chip is formed on the functional area; providing a second substrate, wherein a first side of the second substrate is provided with a first bonding region corresponding to the non-functional region and a second bonding region corresponding to the functional region, a second metal layer is formed on the first bonding region, and a second insulating medium layer is formed on the second bonding region; bonding the first metal layer and the second metal layer to form a first bonding structure, and bonding the first insulating medium layer and the second insulating medium layer to form a second bonding structure; the first substrate is peeled from the first side of the second substrate and the first bonding structure is removed to transfer the chip to the second substrate. By combining the metal bonding and the insulating medium material bonding, the yield of the bonded chip is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a chip transfer method.
Background
At present, chip transfer processes of micro light emitting devices and the like generally adopt a single insulating medium, which is generally silicon dioxide (SiO), to perform a bonding process to transfer a chip on a first wafer to a second wafer2)。
However, in the current wafer bonding process, the bonded wafer is subjected to a large stress due to a large warpage of the wafer, so that the process conditions in the wafer bonding process are difficult to control, and the yield of the bonded chip is reduced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a chip transfer method, which aims to solve the problem of the prior art that the chip transfer process causes the yield of the bonded chip to be reduced.
A chip transfer method comprises the following steps:
providing a first substrate, wherein the first side of the first substrate comprises a functional area and a non-functional area, the functional area is provided with a chip, a first metal layer is formed in the non-functional area, and a first insulating medium layer is formed on the functional area;
providing a second substrate, wherein a first side of the second substrate is provided with a first bonding region corresponding to the non-functional region and a second bonding region corresponding to the functional region, a second metal layer is formed on the first bonding region, and a second insulating medium layer is formed on the second bonding region;
bonding the first metal layer and the second metal layer to form a first bonding structure, and bonding the first insulating medium layer and the second insulating medium layer to form a second bonding structure;
the first substrate is peeled from the first side of the second substrate and the first bonding structure is removed to transfer the chip to the second substrate.
Compared with the chip transfer process which only adopts a single insulating medium for bonding in the prior art, the invention adopts the metal and the insulating medium material for bonding between the substrates in the chip transfer process, and the metal bonding has the advantages of lower process requirements of a larger process window, large bonding force during bonding, smaller bonding pressure and excellent bonding yield, so that the warpage of the substrates is effectively reduced by combining the metal bonding and the insulating medium material bonding, the difficulty of the bonding process is reduced, and the bonding yield between the substrates is improved.
Optionally, the first metal layer has a first metal surface far away from the first substrate, and a maximum distance between the first metal surface and the first substrate is H1The first insulating medium layer has a first medium surface far away from the first substrate, and the maximum distance between the first medium surface and the first substrate is H2(ii) a The second metal layer has a second metal surface far away from the second substrate, and the maximum distance between the second metal surface and the second substrate is H3The second insulating medium layer has a second medium surface far away from the second substrate, and the maximum distance between the second medium surface and the second substrate is H4；H1+H3＝H2+H4. By making the first metal layer, the second metal layer, the first insulating medium layer and the second insulating medium layer satisfy the thickness relationship described above, the second metal layer, the first insulating medium layer and the second insulating medium layer can be formedIn the bonding process of the first substrate and the second substrate, the bonding pressure between the first metal layer and the second metal layer and between the first insulating medium layer and the second insulating medium layer is more uniform, the bonding yield is further improved, and the first substrate can be parallel to the second substrate after bonding, thereby being beneficial to the subsequent stripping process of the first substrate. The equality is not absolutely equal but may vary within a certain tolerance, for example, a difference of about 10%.
Alternatively, H1＝H3And H is2＝H4. The thickness relation among the first metal layer, the second metal layer, the first insulating medium layer and the second insulating medium layer is satisfied, so that the uniformity of bonding pressure among the substrates can be further ensured, and the bonding yield is further improved. The equality is not absolutely equal but may vary within a certain tolerance, for example, a difference of about 10%.
Optionally, the first metal layer has a first projected area on the first substrate, the first insulating medium layer has a second projected area on the first substrate, and a ratio of the first projected area to the second projected area is 1:10 to 10: 1. By enabling the projection area of the first metal layer and the first insulating medium layer to meet the relation, the bonding yield between the first substrate and the second substrate can be further increased by bonding the metal bonding and the insulating medium material to be combined.
Optionally, the thickness ratio of the first metal layer to the second metal layer is 1:10 to 10: 1. The thickness relationship enables the first substrate to be bonded to the second substrate more firmly through the first metal layer and the second metal layer.
Optionally, the first metal layer includes a plurality of first sub-metal layers, each first sub-metal layer is independently located on any one side of the first insulating medium layer, the second metal layer includes a plurality of second sub-metal layers, each second sub-metal layer is independently located on any one side of the second insulating medium layer, and the first sub-metal layers located on at least one side of the first insulating medium layer and the second sub-metal layers located on at least one side of the second insulating medium layer are correspondingly disposed. By providing a plurality of first sub-metal layers over the first substrate and by providing a plurality of second sub-metal layers over the second substrate, respectively, the bonding strength between the first substrate and the second substrate can be further increased.
Optionally, the first sub-metal layers are symmetrically disposed on at least one set of opposite sides of the first insulating medium layer, and the second sub-metal layers are symmetrically disposed on at least one set of opposite sides of the second insulating medium layer. The first sub-metal layer and the second sub-metal layer are arranged in a mode that bonding pressure between the first substrate and the second substrate is more uniform.
Optionally, the first metal layer surrounds the first insulating dielectric layer. The arrangement mode can more effectively prevent the wafer from warping in the bonding process.
Optionally, the materials of the first metal layer and the second metal layer are the same. And the same kind of metal materials are used for bonding, so that the first substrate and the second substrate can realize firmer metal bonding.
Optionally, the materials of the first metal layer and the second metal layer are independently selected from any one or more of gold, silver and indium. The metal material can enable the first substrate and the second substrate to achieve firm metal bonding.
Optionally, the first insulating medium layer and the second insulating medium layer are made of the same material. And the same kind of insulating dielectric materials are used for bonding, so that the first substrate and the second substrate can be firmly bonded.
Optionally, the first insulating dielectric layer and/or the second insulating dielectric layer is silicon oxide. The first substrate and the second substrate can be firmly bonded by adopting the insulating dielectric material and combining metal for bonding.
Drawings
FIG. 1 is a flow chart illustrating a chip transfer method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a chip transfer method according to an embodiment of the present invention, in which a first substrate and a second substrate are provided, a first metal layer is formed on a non-functional region of the first substrate, and a second metal layer is formed on a first bonding region of the second substrate;
fig. 3 is a schematic structural diagram after a first insulating dielectric layer covering the chip is formed on the functional region of the first substrate shown in fig. 2, and a second insulating dielectric layer is formed on the second bonding region of the second substrate;
fig. 4 is a schematic structural diagram of the first metal layer and the second metal layer shown in fig. 3 bonded to form a first bonding structure, and the first insulating medium layer and the second insulating medium layer bonded to form a second bonding structure;
FIG. 5 is a schematic view of the structure of FIG. 4 after the first substrate is peeled from the first side of the second substrate;
fig. 6 is a schematic structural diagram of the first bonding structure shown in fig. 5 removed to transfer the chip to the second substrate.
Description of reference numerals:
10-a first bonding structure; 20-a second bonding structure; 100-a first substrate; 110 — a first metal layer; 120-a first insulating dielectric layer; 200-a second substrate; 210-a second metal layer; 220-a second insulating dielectric layer; 300-chip.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
As described in the background section, in the current wafer bonding process, the warpage of the wafer is large, so that the bonded wafer is subjected to a large stress, the process conditions in the wafer bonding process are difficult to control, and the yield of the bonded chip is reduced.
Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.
The inventors of the present application have studied in view of the above problems and have proposed a chip transfer method, as shown in fig. 1, which includes the steps of:
providing a first substrate, wherein the first substrate comprises a functional area and a non-functional area, the functional area is provided with a chip, a first metal layer is formed in the non-functional area, and a first insulating medium layer covering the chip is formed on the functional area;
providing a second substrate, wherein a first side of the second substrate is provided with a first bonding region corresponding to the non-functional region and a second bonding region corresponding to the functional region, a second metal layer is formed on the first bonding region, and a second insulating medium layer is formed on the second bonding region;
bonding the first metal layer and the second metal layer to form a first bonding structure, and bonding the first insulating medium layer and the second insulating medium layer to form a second bonding structure;
the first substrate is peeled from the first side of the second substrate and the first bonding structure is removed to transfer the chip to the second substrate.
Compared with the chip transfer process which only adopts a single insulating medium for bonding in the prior art, the invention adopts the metal and the insulating medium material for bonding between the substrates in the chip transfer process, and the metal bonding has the advantages of lower process requirements of a larger process window, large bonding force during bonding, smaller bonding pressure and excellent bonding yield, so that the warpage of the substrates is effectively reduced by combining the metal bonding and the insulating medium material bonding, the difficulty of the bonding process is reduced, and the bonding yield between the substrates is improved.
Exemplary embodiments of a chip transfer method provided according to the present application will be described in more detail below with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a first substrate 100 and a second substrate 200 are provided, a first side of the first substrate 100 includes a functional region having a chip 300 and a non-functional region, and a first side of the second substrate 200 has a first bonding region corresponding to the non-functional region and a second bonding region corresponding to the functional region, as shown in fig. 2.
For example, the first substrate 100 may be a growth substrate with a chip 300 grown on a surface thereof, such as a gallium arsenide substrate, a sapphire substrate, a silicon substrate, and the like, and the chip 300 may be a Micro Light Emitting device, such as a Micro Light Emitting Diode (Micro-LED), and may also be a nano Light Emitting Diode.
Illustratively, the second substrate 200 may be a rigid substrate, such as a glass plate, a quartz plate, a sapphire substrate, and the like.
After the steps of providing the first substrate 100 and the second substrate 200, a first metal layer 110 is formed on a non-functional region of the first substrate 100, a first insulating dielectric layer 120 covering the chip 300 is formed on a functional region of the first substrate 100, a second metal layer 210 is formed on a first bonding region of the second substrate 200, and a second insulating dielectric layer 220 is formed on a second bonding region of the second substrate 200, as shown in fig. 2 and 3.
In some embodiments, the first metal layer 110 and the second metal layer 210 may be formed by an evaporation process.
In the above embodiment, in order to form the first metal layer 110 in the non-functional region and the second metal layer 210 in the first bonding region, the first substrate 100 and the second substrate 200 may be respectively covered with photoresist by a photolithography process, and the photoresist may be patterned, so that the photoresist on the first substrate 100 forms a first opening corresponding to the non-functional region and the photoresist on the second substrate 200 forms a second opening corresponding to the first bonding region, so that metal materials are evaporated on the first substrate 100 and the second substrate 200 respectively, so that a portion of the metal materials is filled in the first opening and the second opening, and then the photoresist and the metal materials above the photoresist are removed, so as to obtain the first metal layer 110 in the non-functional region and the second metal layer 210 in the first bonding region.
In some embodiments, the first insulating dielectric layer 120 and the second insulating dielectric layer 220 may be formed by a deposition process.
In the above embodiment, the first substrate 100 and the second substrate 200 may be covered with photoresist respectively through a photolithography process, and the photoresist may be patterned, so that the photoresist on the first substrate 100 forms a first opening corresponding to the functional region, and the photoresist on the second substrate 200 forms a second opening corresponding to the second bonding region, so as to deposit insulating dielectric materials on the first substrate 100 and the second substrate 200 respectively, so that a part of the insulating dielectric materials is filled in the first opening and the second opening, and then the photoresist and the insulating dielectric materials above the photoresist are removed, so as to obtain the first insulating dielectric layer 120 located in the functional region and the second insulating dielectric layer 220 located in the second bonding region.
In some embodiments, the first metal layer 110 has a first metal surface far away from the first substrate 100, and the maximum distance between the first metal surface and the first substrate 100 is H1The first insulating medium layer 120 has a first medium surface far from the first substrate 100, and the maximum distance between the first medium surface and the first substrate 100 is H2(ii) a The second metal layer 210 has a second metal surface far from the second substrate 200, and the maximum distance between the second metal surface and the second substrate 200 is H3The second insulating dielectric layer 220 has a second dielectric surface far from the second substrate 200, and the maximum distance between the second dielectric surface and the second substrate 200 is H4；H1And H3Sum and H2And H4The sum is equal. The equality is not absolutely equal but may be at oneThe determined error is allowed to vary, such as a difference of about 10%.
In the above embodiment, by making the first metal layer 110, the second metal layer 210, the first insulating dielectric layer 120, and the second insulating dielectric layer 220 satisfy the thickness relationship, in the bonding process of the first substrate 100 and the second substrate 200, the bonding pressure between the first metal layer 110 and the second metal layer 210 and between the first insulating dielectric layer 120 and the second insulating dielectric layer 220 can be made more uniform, the bonding yield is further improved, and the first substrate 100 can be parallel to the second substrate 200 after bonding, which is beneficial to the subsequent stripping process of the first substrate 100.
In the above embodiment, H may be added1Is equal to H3，H2Is equal to H4. The thickness relation among the first metal layer, the second metal layer, the first insulating medium layer and the second insulating medium layer is satisfied, so that the uniformity of bonding pressure among the substrates can be further ensured, and the bonding yield is further improved. The equality is not absolutely equal but may vary within a certain tolerance, for example, a difference of about 10%.
In order to further improve the bonding yield between the first substrate 100 and the second substrate 200, in some embodiments, the first metal layer 110 has a first projected area on the first substrate 100, the first insulating medium layer 120 has a second projected area on the first substrate 100, and a ratio of the first projected area to the second projected area is 1:10 to 10: 1.
In order to achieve a stronger bond between the first substrate 100 and the second substrate 200, in some embodiments, a thickness ratio of the first metal layer 110 to the second metal layer 210 is 1:10 to 10: 1.
In some embodiments, the first metal layer 110 includes a plurality of first sub-metal layers, each of the first sub-metal layers is independently located at any one side of the first insulating medium layer 120, the second metal layer 210 includes a plurality of second sub-metal layers, each of the second sub-metal layers is independently located at any one side of the second insulating medium layer 220, and the first sub-metal layers located at least one side of the first insulating medium layer 120 are disposed corresponding to the second sub-metal layers located at least one side of the second insulating medium layer 220.
In the above embodiment, by providing a plurality of first sub-metal layers on the first substrate 100 and by providing a plurality of second sub-metal layers on the second substrate 200, respectively, the bonding strength between the first substrate 100 and the second substrate 200 can be further increased.
In the above embodiment, the first sub-metal layers may be symmetrically disposed on at least one set of opposite sides of the first insulating dielectric layer 120, and the second sub-metal layers may be symmetrically disposed on at least one set of opposite sides of the second insulating dielectric layer 220. The first sub-metal layer and the second sub-metal layer are disposed in such a manner that the bonding pressure between the first substrate 100 and the second substrate 200 is more uniform.
In order to more effectively prevent the wafer from warping during the bonding process, in some embodiments, the first metal layer 110 surrounds the first insulating medium layer 120.
In some embodiments, the material of the first metal layer 110 and the second metal layer 210 is the same. The bonding using the same kind of metal material enables the first substrate 100 and the second substrate 200 to be more firmly bonded.
Illustratively, the material of the first metal layer 110 and the second metal layer 210 is independently selected from any one or more of Au, Ag, and In. The above materials enable the first substrate 100 and the second substrate 200 to achieve a strong metallic bonding.
In some embodiments, the material of the first insulating dielectric layer 120 and the second insulating dielectric layer 220 is the same. The same kind of insulating dielectric material is used for bonding, so that the first substrate 100 and the second substrate 200 can realize firm metal bonding.
Illustratively, the first insulating dielectric layer 120 and/or the second insulating dielectric layer 220 are silicon oxide, such as silicon dioxide (SiO)2). The use of the above-mentioned insulating dielectric material in combination with metal for bonding enables the first substrate 100 and the second substrate 200 to be firmly bonded.
After the steps of forming the first metal layer 110 and the first insulating medium layer 120 on the first substrate 100 and forming the second metal layer 210 and the second insulating medium layer 220 on the second substrate 200, the first metal layer 110 and the second metal layer 210 are bonded to form a first bonding structure 10, and the first insulating medium layer 120 and the second insulating medium layer 220 are bonded to form a second bonding structure 20, as shown in fig. 4.
The bonding process for forming the first bonding structure 10 and the second bonding structure 20 may be a conventional bonding process in the prior art, such as a thermal compression bonding process.
After the steps of forming the above-described first and second bonding structures 10 and 20, the first substrate 100 is peeled off from the first side of the second substrate 200 to completely separate the first substrate 100 from the chip 300, the first and second bonding structures 10 and 20, as shown in fig. 5, and then the first bonding structure 10 is removed to transfer the chip 300 to the second substrate 200, as shown in fig. 6.
The process of peeling the first substrate 100 may be a peeling process, such as a laser peeling process, which is conventional in the art.
The process of removing the first bonding structure 10 may be a conventional etching process in the prior art, and those skilled in the art can reasonably select the type of etching gas or etching solution and the process conditions thereof according to the types of materials of the first metal layer 110 and the second metal layer 210.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A chip transfer method is characterized by comprising the following steps:
providing a first substrate, wherein the first side of the first substrate comprises a functional area and a non-functional area, the functional area is provided with a chip, a first metal layer is formed in the non-functional area, and a first insulating medium layer is formed on the functional area;
providing a second substrate, wherein a first side of the second substrate is provided with a first bonding area corresponding to the non-functional area and a second bonding area corresponding to the functional area, a second metal layer is formed on the first bonding area, and a second insulating medium layer is formed on the second bonding area;
bonding the first metal layer and the second metal layer to form a first bonding structure, and bonding the first insulating medium layer and the second insulating medium layer to form a second bonding structure;
and peeling the first substrate from the first side of the second substrate, and removing the first bonding structure to transfer the chip to the second substrate.
2. The transfer method according to claim 1,
the first metal layer has a first metal surface far away from the first substrate, and the maximum distance between the first metal surface and the first substrate is H1The first insulating medium layer is provided with a first medium surface far away from the first substrate, and the maximum distance between the first medium surface and the first substrate is H2；
The second metal layer has a second metal surface far away from the second substrate, and the maximum distance between the second metal surface and the second substrate is H3The second insulating medium layer is provided with a second medium surface far away from the second substrate, and the maximum distance between the second medium surface and the second substrate is H4；
H1+H3＝H2+H4。
3. The transfer method of claim 2 wherein H is1＝H3And H is2＝H4。
4. The transfer method of claim 1, wherein the first metal layer comprises a plurality of first sub-metal layers, each of the first sub-metal layers being independently located on either side of the first dielectric layer, the second metal layer comprises a plurality of second sub-metal layers, each of the second sub-metal layers being independently located on either side of the second dielectric layer, the first sub-metal layers located on at least one side of the first dielectric layer being disposed in correspondence with the second sub-metal layers located on at least one side of the second dielectric layer.
5. The transfer method of claim 4, wherein the first sub-metal layers are symmetrically disposed on at least one set of opposing sides of the first dielectric layer and the second sub-metal layers are symmetrically disposed on at least one set of opposing sides of the second dielectric layer.
6. The transfer method of claim 1, wherein the first metal layer surrounds the first dielectric layer.
7. The transfer method according to any one of claims 1 to 6, wherein the material of the first metal layer and the second metal layer is the same.
8. The transfer method according to any one of claims 1 to 6, wherein the material of the first metal layer and the second metal layer is independently selected from any one or more of gold, silver and indium.
9. The transfer method according to any one of claims 1 to 6, wherein the first insulating medium layer and the second insulating medium layer are the same in material.
10. The transfer method according to any one of claims 1 to 6, wherein the first insulating dielectric layer and/or the second insulating dielectric layer is silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011514635.5A CN112968119B (en) | 2020-12-18 | 2020-12-18 | Chip transfer method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011514635.5A CN112968119B (en) | 2020-12-18 | 2020-12-18 | Chip transfer method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112968119A CN112968119A (en) | 2021-06-15 |
| CN112968119B true CN112968119B (en) | 2022-02-18 |
Family
ID=76271175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011514635.5A Active CN112968119B (en) | 2020-12-18 | 2020-12-18 | Chip transfer method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112968119B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919426A (en) * | 2016-08-24 | 2018-04-17 | 浙江德汇电子陶瓷有限公司 | UV LED inorganic encapsulated base of ceramic and preparation method thereof |
| TW201901784A (en) * | 2017-05-24 | 2019-01-01 | 日商富士軟片股份有限公司 | Method for manufacturing treated member and laminated body |
| TW201907511A (en) * | 2017-05-05 | 2019-02-16 | 美商庫利克和索夫工業公司 | Method of operating a wire bonding machine to improve clamping of a substrate and wire bonding machine |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200826206A (en) * | 2006-12-08 | 2008-06-16 | Taiwan Solutions Systems Corp | Semiconductor fabrication method and structure thereof |
| TWI447889B (en) * | 2011-08-05 | 2014-08-01 | Chipmos Technologies Inc | Chip package structure |
| JP6197422B2 (en) * | 2013-07-11 | 2017-09-20 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device and wafer with supporting substrate |
| US10134803B2 (en) * | 2015-01-23 | 2018-11-20 | Vuereal Inc. | Micro device integration into system substrate |
| CN105632911A (en) * | 2016-01-02 | 2016-06-01 | 北京工业大学 | Wafer level package method for reducing edge stress |
| CN106449449B (en) * | 2016-11-30 | 2019-04-30 | 新昌县立诺智能科技有限公司 | A kind of manufacturing method of wafer bonding structure |
-
2020
- 2020-12-18 CN CN202011514635.5A patent/CN112968119B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919426A (en) * | 2016-08-24 | 2018-04-17 | 浙江德汇电子陶瓷有限公司 | UV LED inorganic encapsulated base of ceramic and preparation method thereof |
| TW201907511A (en) * | 2017-05-05 | 2019-02-16 | 美商庫利克和索夫工業公司 | Method of operating a wire bonding machine to improve clamping of a substrate and wire bonding machine |
| TW201901784A (en) * | 2017-05-24 | 2019-01-01 | 日商富士軟片股份有限公司 | Method for manufacturing treated member and laminated body |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112968119A (en) | 2021-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10847596B2 (en) | Bendable display panel and fabricating method thereof | |
| US8456004B2 (en) | Template wafer and process for small pitch flip-chip interconnect hybridization | |
| TW202111787A (en) | Method for provisionally bonding semiconductor substrate | |
| US20050250336A1 (en) | Semiconductor device and method for fabricating the same | |
| JP2003023239A (en) | Circuit board and its manufacturing method and high output module | |
| CN109742265A (en) | A kind of preparation method of flexible display substrates | |
| US20080009095A1 (en) | Advanced Thin Flexible Microelectronic Assemblies and Methods for Making Same | |
| US7544611B2 (en) | Method of manufacturing III-V nitride semiconductor device | |
| CN112968119B (en) | Chip transfer method | |
| US20230154903A1 (en) | Light-emitting diode (led) chip assembly and prepraing method thereof, and preparing method of display panel | |
| CN115425122A (en) | LED chip mass transfer method and display panel | |
| WO2021026872A1 (en) | Transfer method for semiconductor thin film layer and manufacturing method for composite wafer | |
| JP3271390B2 (en) | Transmission mask for charged beam exposure and method of manufacturing the same | |
| JP2608658B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN115863382B (en) | Novel GaN epitaxial structure and preparation method and application thereof | |
| JPS62122279A (en) | Manufacture of field effect transistor | |
| CN112968099B (en) | Aluminum oxide patterning method | |
| CN114792637A (en) | Preparation method of solder for eutectic bonding of bump structure | |
| US20240049506A1 (en) | Mask-support assembly and producing method thereof | |
| WO2023002787A1 (en) | Bonded wafer and method for manufacturing bonded wafer | |
| US11406022B2 (en) | Substrate having through via and method of fabricating the same | |
| US20220005977A1 (en) | Method for manufacturing display panel, display panel, and display apparatus | |
| US20240191343A1 (en) | Mask-frame assembly and producing method thereof | |
| CN115425123A (en) | Preparation method of red light micro LED chip, red light micro LED chip and display device | |
| JPS5936923A (en) | Wafer reinforcement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |