US20180024958A1

US20180024958A1 - Techniques to provide a multi-level memory architecture via interconnects

Info

Publication number: US20180024958A1
Application number: US15/476,896
Authority: US
Inventors: Murugasamy K. Nachimuthu; Mohan J. Kumar
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-07-22
Filing date: 2017-03-31
Publication date: 2018-01-25
Also published as: US10735835B2; CN109313582A; DE112017003691T5; US20180027685A1; WO2018017248A1; US20180027058A1; WO2018017266A1; WO2018017230A1; US10823920B2; WO2018017253A1; WO2018017278A1; US20180026654A1; US20180024306A1; CN109328351A; DE112017003711T5; US10033404B2; WO2018017244A1; CN113254381A; EP3488338A4; US20180024776A1

Abstract

Various embodiments are generally directed to an apparatus, method and other techniques to enable memory interfaces to communicate read request, write requests, and data via an interconnect. Embodiments, include processing write requests to write data into memory coupled via an interconnect and processing read requests to read data from memory coupled via an interconnect. In embodiments, the data may be compressed data based on a compression mechanism and communicated in a fabric packet including a compression mechanism indicator, the compressed data, and an address, the compression mechanism indicator to indicate which compression mechanism is applied to the data.

Description

RELATED CASES

This application claims priority to U.S. Provisional Patent Application Number 62/365,969, filed Jul. 22, 2016, U.S. Provisional Patent Application Number 62/376,859, filed Aug. 18, 2016, and U.S. Provisional Patent Application Number 62/427,268, filed Nov. 29, 2016, each of which are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

Embodiments described herein generally include providing a multi-level memory architecture via high speed interconnects. More specifically, embodiments are directed to communicating data via interconnects between physical resources in a multi-level memory architecture.

BACKGROUND

A computing data center may include one or more computing systems including a plurality of compute sleds that may include various compute structures and may be physically located on multiple racks. The sleds may include a number of physical resources and provide processing, memory and storage capabilities. These physical resources may be shared between among the sleds and racks of the compute data center. Thus, these physical resources require interconnects and new ways to communicate data between each other. Embodiments discussed herein are directed to solving these and other problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates an example of a data center.

FIG. 2 illustrates an example of a rack.

FIG. 3 illustrates an example of a data center.

FIG. 4 illustrates an example of a data center.

FIG. 5 illustrates an example of a switching infrastructure.

FIG. 6 illustrates an example of a data center.

FIG. 7 illustrates an example of a sled.

FIG. 8 illustrates an example of a data center.

FIG. 9 illustrates an example of a data center.

FIG. 10 illustrates an example of a sled.

FIG. 11 illustrates an example of a data center.

FIG. 12 illustrates an example of a compute system.

FIG. 13 illustrates an example of a compute system.

FIG. 14A illustrates an example of a fabric packet.

FIG. 14B illustrates and example of a table.

FIG. 15 illustrates an example of memory module.

FIG. 16 illustrates an example of logic flow diagrams.

FIG. 17 illustrates an example of logic flow diagrams.

DETAILED DESCRIPTION

Various embodiments may generally be directed to enabling memory interfaces to communicate read requests, write requests, and data via an interconnect. Embodiments include processing write requests to write data into second level memory and third level memory coupled via an interconnect and processing read requests to read data from the second level memory and the third level memory coupled via the high-speed interconnect. In embodiments, the data may be compressed based on a compression mechanism and communicated in a fabric packet including a compression mechanism indicator, the compressed data, and an address, the compression mechanism indicator may indicate which compression mechanism is applied to the data. Note, some embodiments may only include a second level memory and the same other embodiments may include a multi-level memory architecture having more than three levels of memory. Embodiments are not limited in this manner.
Reference is now made to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are outlined in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives consistent with the claimed subject matter.
FIG. 1 illustrates a conceptual overview of a data center 100 that may generally be representative of a data center or other type of computing network in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 1, data center 100 may generally contain a plurality of racks, each of which may house computing equipment comprising a respective set of physical resources. In the particular non-limiting example depicted in FIG. 1, data center 100 contains four racks 102A to 102D, which house computing equipment comprising respective sets of physical resources (PCRs) 105A to 105D. According to this example, a collective set of physical resources 106 of data center 100 includes the various sets of physical resources 105A to 105D that are distributed among racks 102A to 102D. Physical resources 106 may include resources of multiple types, such as—for example—processors, co-processors, accelerators, field-programmable gate arrays (FPGAs), memory, and storage. The embodiments are not limited to these examples.
The illustrative data center 100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance. In particular, in the illustrative embodiment, the sleds are shallower than typical printed circuit boards (PCBs). In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the board. Further, the components on the sled are spaced further apart than in typical PCBs, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while memory modules, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.
Furthermore, in the illustrative embodiment, the data center 100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures which may be in accordance to standards, such as Institute of Electrical and Electronics Engineers (IEEE) 802.3-2015 standard (Ethernet) or any predecessors, revisions, or variants thereof, and other architectures, such as Intel® Omni-Path®. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twister pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center 100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, field-programmable gate arrays (FPGAs), application specific intergrated circuits (ASICs), etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. The illustrative data center 100 additionally receives usage information for the various resources, predicts resource usage for different types of workloads based on past resource usage, and dynamically reallocates the resources based on this information.
The racks 102A, 102B, 102C, 102D of the data center 100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example, data center 100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulable resource sleds. Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C, 102D include integrated power sources that receive a greater voltage than is typical for power sources. The increased voltage enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies. FIG. 2 illustrates an exemplary logical configuration of a rack 202 of the data center 100. As shown in FIG. 2, rack 202 may generally house a plurality of sleds, each of which may comprise a respective set of physical resources. In the particular non-limiting example depicted in FIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective sets of physical resources 205-1 to 205-4, each of which constitutes a portion of the collective set of physical resources 206 comprised in rack 202. With respect to FIG. 1, if rack 202 is representative of—for example—rack 102A, then physical resources 206 may correspond to the physical resources 105A comprised in rack 102A.
In the context of this example, physical resources 105A may thus be made up of the respective sets of physical resources, including physical storage resources 205-1, physical accelerator resources 205-2, physical memory resources 204-3, and physical compute resources 205-5 comprised in the sleds 204-1 to 204-4 of rack 202. The embodiments are not limited to this example. Each sled may contain a pool of each of the various types of physical resources (e.g., compute, memory, accelerator, storage). By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate.
FIG. 3 illustrates an example of a data center 300 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. In the particular non-limiting example depicted in FIG. 3, data center 300 comprises racks 302-1 to 302-32. In various embodiments, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate various access pathways. For example, as shown in FIG. 3, the racks of data center 300 may be arranged in such fashion as to define and/or accommodate access pathways 311A, 311B, 311C, and 311D. In some embodiments, the presence of such access pathways may generally enable automated maintenance equipment, such as robotic maintenance equipment, to physically access the computing equipment housed in the various racks of data center 300 and perform automated maintenance tasks (e.g., replace a failed sled, upgrade a sled). In various embodiments, the dimensions of access pathways 311A, 311B, 311C, and 311D, the dimensions of racks 302-1 to 302-32, and/or one or more other aspects of the physical layout of data center 300 may be selected to facilitate such automated operations. The embodiments are not limited in this context.
FIG. 4 illustrates an example of a data center 400 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As shown in FIG. 4, data center 400 may feature an optical fabric 412. Optical fabric 412 may generally comprise a combination of optical signaling media (such as optical cabling) and optical switching infrastructure via which any particular sled in data center 400 can send signals to (and receive signals from) each of the other sleds in data center 400. The signaling connectivity that optical fabric 412 provides to any given sled may include connectivity both to other sleds in a same rack and sleds in other racks. In the particular non-limiting example depicted in FIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to 402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and 404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example, data center 400 comprises a total of eight sleds. Via optical fabric 412, each such sled may possess signaling connectivity with each of the seven other sleds in data center 400. For example, via optical fabric 412, sled 404A-1 in rack 402A may possess signaling connectivity with sled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2, 404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the other racks 402B, 402C, and 402D of data center 400. The embodiments are not limited to this example.
FIG. 5 illustrates an overview of a connectivity scheme 500 that may generally be representative of link-layer connectivity that may be established in some embodiments among the various sleds of a data center, such as any of example data centers 100, 300, and 400 of FIGS. 1, 3, and 4. Connectivity scheme 500 may be implemented using an optical fabric that features a dual-mode optical switching infrastructure 514. Dual-mode optical switching infrastructure 514 may generally comprise a switching infrastructure that is capable of receiving communications according to multiple link-layer protocols via a same unified set of optical signaling media, and properly switching such communications. In various embodiments, dual-mode optical switching infrastructure 514 may be implemented using one or more dual-mode optical switches 515. In various embodiments, dual-mode optical switches 515 may generally comprise high-radix switches. In some embodiments, dual-mode optical switches 515 may comprise multi-ply switches, such as four-ply switches. In various embodiments, dual-mode optical switches 515 may feature integrated silicon photonics that enable them to switch communications with significantly reduced latency in comparison to conventional switching devices. In some embodiments, dual-mode optical switches 515 may constitute leaf switches 530 in a leaf-spine architecture additionally including one or more dual-mode optical spine switches 520.
In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel®'s Omni-Path Architecture®'s, Infiniband®) via optical signaling media of an optical fabric. As reflected in FIG. 5, with respect to any particular pair of sleds 504A and 504B possessing optical signaling connectivity to the optical fabric, connectivity scheme 500 may thus provide support for link-layer connectivity via both Ethernet links and HPC links. Thus, both Ethernet and HPC communications can be supported by a single high-bandwidth, low-latency switch fabric. The embodiments are not limited to this example.
FIG. 6 illustrates a general overview of a rack architecture 600 that may be representative of an architecture of any particular one of the racks depicted in FIGS. 1 to 4 according to some embodiments. As reflected in FIG. 6, rack architecture 600 may generally feature a plurality of sled spaces into which sleds may be inserted, each of which may be robotically-accessible via a rack access region 601. In the particular non-limiting example depicted in FIG. 6, rack architecture 600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5 feature respective multi-purpose connector modules (MPCMs) 616-1 to 616-5. In some instances, when a sled is inserted into any given one of sled spaces 603-1 to 603-5, the corresponding MPCM may couple with a counterpart MPCM of the inserted sled. This coupling may provide the inserted sled with connectivity to both signaling infrastructure and power infrastructure of the rack in which it is housed.
Included among the types of sleds to be accommodated by rack architecture 600 may be one or more types of sleds that feature expansion capabilities. FIG. 7 illustrates an example of a sled 704 that may be representative of a sled of such a type. As shown in FIG. 7, sled 704 may comprise a set of physical resources 705, as well as an MPCM 716 designed to couple with a counterpart MPCM when sled 704 is inserted into a sled space such as any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may also feature an expansion connector 717. Expansion connector 717 may generally comprise a socket, slot, or other type of connection element that is capable of accepting one or more types of expansion modules, such as an expansion sled 718. By coupling with a counterpart connector on expansion sled 718, expansion connector 717 may provide physical resources 705 with access to supplemental computing resources 705B residing on expansion sled 718. The embodiments are not limited in this context.
FIG. 8 illustrates an example of a rack architecture 800 that may be representative of a rack architecture that may be implemented in order to provide support for sleds featuring expansion capabilities, such as sled 704 of FIG. 7. In the particular non-limiting example depicted in FIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7, which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to 803-7 include respective primary regions 803-1A to 803-7A and respective expansion regions 803-1B to 803-7B. With respect to each such sled space, when the corresponding MPCM is coupled with a counterpart MPCM of an inserted sled, the primary region may generally constitute a region of the sled space that physically accommodates the inserted sled. The expansion region may generally constitute a region of the sled space that can physically accommodate an expansion module, such as expansion sled 718 of FIG. 7, in the event that the inserted sled is configured with such a module.
FIG. 9 illustrates an example of a rack 902 that may be representative of a rack implemented according to rack architecture 800 of FIG. 8 according to some embodiments. In the particular non-limiting example depicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7, which include respective primary regions 903-1A to 903-7A and respective expansion regions 903-1B to 903-7B. In various embodiments, temperature control in rack 902 may be implemented using an air cooling system. For example, as reflected in FIG. 9, rack 902 may feature a plurality of fans 919 that are generally arranged to provide air cooling within the various sled spaces 903-1 to 903-7. In some embodiments, the height of the sled space is greater than the conventional “1U” server height. In such embodiments, fans 919 may generally comprise relatively slow, large diameter cooling fans as compared to fans used in conventional rack configurations. Running larger diameter cooling fans at lower speeds may increase fan lifetime relative to smaller diameter cooling fans running at higher speeds while still providing the same amount of cooling. The sleds are physically shallower than conventional rack dimensions. Further, components are arranged on each sled to reduce thermal shadowing (i.e., not arranged serially in the direction of air flow). As a result, the wider, shallower sleds allow for an increase in device performance because the devices can be operated at a higher thermal envelope (e.g., 250 Watts (W) due to improved cooling (i.e., no thermal shadowing, more space between devices, more room for larger heat sinks, etc.).
MPCMs 916-1 to 916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules 920-1 to 920-7, each of which may draw power from an external power source 921. In various embodiments, external power source 921 may deliver alternating current (AC) power to rack 902, and power modules 920-1 to 920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules 920-1 to 920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.
MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-mode optical switching infrastructure 914, which may be the same as—or similar to—dual-mode optical switching infrastructure 514 of FIG. 5. In various embodiments, optical connectors contained in MPCMs 916-1 to 916-7 may be designed to couple with counterpart optical connectors contained in MPCMs of inserted sleds to provide such sleds with optical signaling connectivity to dual-mode optical switching infrastructure 914 via respective lengths of optical cabling 922-1 to 922-7. In some embodiments, each such length of optical cabling may extend from its corresponding MPCM to an optical interconnect loom 923 that is external to the sled spaces of rack 902. In various embodiments, optical interconnect loom 923 may be arranged to pass through a support post or other type of load-bearing element of rack 902. The optical interconnect loom 923 may include cabling conduit and other cable management hardware, such as cable rings, cable panels, cable brackets, pass through panels, and so forth. The embodiments are not limited in this context. These cable management features can save time because inserted sleds connect to an optical switching infrastructure via MPCMs, the resources typically spent in manually configuring the rack cabling to accommodate a newly inserted sled can be saved.
FIG. 10 illustrates an example of a sled 1004 that may be representative of a sled designed for use in conjunction with rack 902 of FIG. 9 according to some embodiments. Sled 1004 may feature an MPCM 1016 that comprises an optical connector 1016A and a power connector 1016B, and that is designed to couple with a counterpart MPCM of a sled space in conjunction with insertion of MPCM 1016 into that sled space. Coupling MPCM 1016 with such a counterpart MPCM may cause power connector 1016 to couple with a power connector comprised in the counterpart MPCM. This may generally enable physical resources 1005 of sled 1004 to source power from an external source, via power connector 1016 and power transmission media 1024 that conductively couples power connector 1016 to physical resources 1005.
Sled 1004 may also include dual-mode optical network interface circuitry 1026. Dual-mode optical network interface circuitry 1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-mode optical switching infrastructure 914 of FIG. 9. In some embodiments, dual-mode optical network interface circuitry 1026 may be capable both of Ethernet protocol communications and of communications according to a second, high-performance protocol. In various embodiments, dual-mode optical network interface circuitry 1026 may include one or more optical transceiver modules 1027, each of which may be capable of transmitting and receiving optical signals over each of one or more optical channels. The embodiments are not limited in this context.
Coupling MPCM 1016 with a counterpart MPCM of a sled space in a given rack may cause optical connector 1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode optical network interface circuitry 1026, via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 may communicate with the physical resources 1005 of sled 1004 via electrical signaling media 1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250W), as described above with reference to FIG. 9, in some embodiments, a sled may include one or more additional features to facilitate air cooling, such as a heatpipe and/or heat sinks arranged to dissipate heat generated by physical resources 1005. It is worthy of note that although the example sled 1004 depicted in FIG. 10 does not feature an expansion connector, any given sled that features the design elements of sled 1004 may also feature an expansion connector according to some embodiments. The embodiments are not limited in this context.
FIG. 11 illustrates an example of a data center 1100 that may generally be representative of one in/for which one or more techniques described herein may be implemented according to various embodiments. As reflected in FIG. 11, a physical infrastructure management framework 1150A may be implemented to facilitate management of a physical infrastructure 1100A of data center 1100. In various embodiments, one function of physical infrastructure management framework 1150A may be to manage automated maintenance functions within data center 1100, such as the use of robotic maintenance equipment to service computing equipment within physical infrastructure 1100A. In some embodiments, physical infrastructure 1100A may feature an advanced telemetry system that performs telemetry reporting that is sufficiently robust to support remote automated management of physical infrastructure 1100A. In various embodiments, telemetry information provided by such an advanced telemetry system may support features such as failure prediction/prevention capabilities and capacity planning capabilities. In some embodiments, physical infrastructure management framework 1150A may also be configured to manage authentication of physical infrastructure components using hardware attestation techniques. For example, robots may verify the authenticity of components before installation by analyzing information collected from a radio frequency identification (RFID) tag associated with each component to be installed. The embodiments are not limited in this context.
As shown in FIG. 11, the physical infrastructure 1100A of data center 1100 may comprise an optical fabric 1112, which may include a dual-mode optical switching infrastructure 1114. Optical fabric 1112 and dual-mode optical switching infrastructure 1114 may be the same as—or similar to—optical fabric 412 of FIG. 4 and dual-mode optical switching infrastructure 514 of FIG. 5, respectively, and may provide high-bandwidth, low-latency, multi-protocol connectivity among sleds of data center 1100. As discussed above, with reference to FIG. 1, in various embodiments, the availability of such connectivity may make it feasible to disaggregate and dynamically pool resources such as accelerators, memory, and storage. In some embodiments, for example, one or more pooled accelerator sleds 1130 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of accelerator resources—such as co-processors and/or field-programmable gate arrays (FPGAs), for example—that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114.
In another example, in various embodiments, one or more pooled storage sleds 1132 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of storage resources that is available globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage sleds 1132 may comprise pools of storage devices such as solid-state drives (SSDs), hard disk drives (HDD), hard drive, disk drive, fixed disk drives, and so forth. In various embodiments, one or more high-performance processing sleds 1134 may be included among the physical infrastructure 1100A of data center 1100. In some embodiments, high-performance processing sleds 1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250 Watts (W) or more. In various embodiments, any given high-performance processing sled 1134 may feature an expansion connector 1117 that can accept a multi-level memory expansion sled, such that the memory that is locally available to that high-performance processing sled 1134 is disaggregated from the processors and first level memory, such as cache, comprised on that sled. In some embodiments, such a high-performance processing sled 1134 may be configured with memory using an expansion sled that comprises low-latency SSD storage. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or storage resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps, e.g. remote resources connected through a single or two switches, away in the spine-leaf network architecture described above with reference to FIG. 5. The embodiments are not limited in this context.
In various embodiments, one or more layers of abstraction may be applied to the physical resources of physical infrastructure 1100A in order to define a virtual infrastructure, such as a software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure (SDI) 1100B may be allocated to support the provision of cloud services 1140. In various embodiments, particular sets of virtual computing resources 1136 may be grouped for provision to cloud services 1140 in the form of SDI services 1138. Examples of cloud services 1140 may include—without limitation—software as a service (SaaS) services 1142, platform as a service (PaaS) services 1144, and infrastructure as a service (IaaS) services 1146.
In some embodiments, management of software-defined infrastructure 1100B may be conducted using a virtual infrastructure management framework 1150B. In various embodiments, virtual infrastructure management framework 1150B may be designed to implement workload fingerprinting techniques and machine-learning techniques in conjunction with managing allocation of virtual computing resources 1136 and/or SDI services 1138 to cloud services 1140. In some embodiments, virtual infrastructure management framework 1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework 1150C may be implemented to provide quality of service (QoS) management capabilities for cloud services 1140. The embodiments are not limited in this context.
FIG. 12 illustrates an example of a compute system 1200 that includes sleds 1204-1 and 1204-2 coupled via an interconnect 1251. The sleds may include a number of components and resources that may be shared via the interconnect 1251. The compute system 1200 may include a multi-level memory architecture that shares physical memory resources between sleds, such as sleds 1204-1 and 1204-2 via the interconnect 1251. For example, the physical memory resources 1205-3-1 of sled 1204-1 may be a first level of memory for sled 1204-1. This first level may be made of memory modules 1211-1-1 through 1211-1-x, where x may be any positive integer. The memory module may be a Dual Inline Memory Module (DIMM) and include volatile memory. In some embodiments, the first level memory may be cache local to the physical compute resources 1205-4-1. The memory modules 1211-1-1 through 1211-1-x may include volatile memory, e.g. dynamic random access memory (DRAM), double data rate (DDR) DRAM, synchronous dynamic random-access memory (SDRAM), DDR SDRAM, and so forth. In some embodiments, the memory modules 1211-1 may include one or more byte addressable write-in-place non-volatile memory devices. The memory devices may also include future generation non-volatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory devices may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory devices may refer to the die itself and/or to a packaged memory product.
Embodiments also include providing a second layer of memory and, in some instances, a third layer of memory by the physical memory resources 1205-3-2 of sled 1204-2 for sled 1204-1 coupled via an interconnect 1251, which may be a fabric interconnect and include high speed serial links. For example, the memory modules 1211-2-1 through 1211-2-y, where y may be any positive integer, may provide a second layer and third layer of memory for sled 1204-1 via the interconnect 1251. In one example, the second layer may be one or more of the memory modules 1211-2-y made up of volatile memory, such as dynamic random access memory (DRAM), double data rate (DDR) DRAM, synchronous dynamic random-access memory (SDRAM), DDR SDRAM, and so forth. The third layer may be one or more of the memory modules 1211-2-y made up of byte addressable write-in-place non-volatile memory devices. The memory devices may also include future generation non-volatile devices, such as a three dimensional crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory devices may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory devices may refer to the die itself and/or to a packaged memory product. However, embodiments are not limited in this manner and embodiments may include any type of memory device for the memory modules 1211.
In some embodiments, the second level memory and third level memory is presented as “main memory” to a host operating system (OS), while the first level memory is a cache for the second and third level memory that is transparent to the OS, thus appearing to the OS the same as typical main memory solutions. In one example, physical memory resources 1205-3-1 may be presented as main memory to sled 1204-1 and physical compute resources 1205-4-1, while physical memory resources 1205-3-2 may be presented as cache to physical compute resources 1205-4-1. The management of the multi-level memory may be done by a combination of logic and modules executed via the host computer processor unit, e.g. physical compute resources 1205-4-1.
As to be discussed in more detail below, one or more embodiments may include compressing/decompressing data to transfer for storage in the second level memory or the third level memory, e.g. physical memory resources 1205-3-2, coupled via an interconnect 1251. In these instances, the memory access performance may not be uniform across address space. Thus, the OS may be notified during part of the boot process of the compression/decompression logic as well as an amount of memory available as first level memory and second and third level memory. For example, the basic input/output system (BIOS) and advanced configuration and power interface (ACPI) tables may be used to notify the OS during boot of the memory configuration, memory size, caching policy, and so forth to utilize the memory to maximize the performance. These tables include the static resource affinity table (SRAT), system locality information table (SLIT), HMAT, and in some instances, the unified extensible firmware interface (UEFI) memory attributes. Embodiments are not limited in this manner.
In embodiments, each of the sleds 1204-1 and 1204-2 may include components and other processing structures similarly discussed with other sleds discussed herein, such as sled 1004 illustrated in FIG. 10. For example, the physical compute resource 1205-4 may be implemented as a microprocessor, a processor, a central processing unit, a multi-core processor, a mobile device processor, a single core processor, a system-on-chip (SoC) device, and so forth. The physical compute resource 1205-4 may be integrated on a single die or multiple dies in a single chip package. Moreover, each of the cores 1207 of the physical compute resources 1205-4 may be independent processing units capable of reading and executing program instructions. The instructions are ordinary instructions that can be executed at the same time or in parallel. In embodiments, the physical compute resource 1205-4 may be coupled with other components of the sled 1204 via one or more interconnects or links, such as interconnect 1253 coupled with the physical memory resources 1205-3, the interconnect may be a high speed bus, trace, and so forth. The physical compute resources may further include other components, such as the one or more cores 1207, a memory controller 1236, and a memory interface 1234.
In embodiments, the memory controller 1236, may be an integrated memory controller, e.g., on the same die as the cores 1207. In other instances, the memory controller 1236 may be integrated in a different die on a different chipset and coupled with the cores 1207 by a bus or link, for example. The memory controller 1236 may receive read requests and memory address(es) to read data from memory, e.g. the physical memory resources 1205-3-1 and 1205-3-2. In some instances, the memory controller 1236 may provide the read request to the memory interface 1234 to retrieve the data for memory. Once the data is returned, the memory controller 1236 may provide the data to the cores 1207. Further, the memory controller 1236 may also receive write requests and memory address(es) and associated data to write to memory, such as physical memory resources 1205-3-1 and 1205-3-2. Similarly, the memory controller 1236 may provide the data and address(es) to the memory interface 1234 to write to memory.
In embodiments, the memory interface 1234 may send read and write requests to memory, such as physical memory resources 1205-3-1 and 1205-3-2, which may be based on the address(es) provided by the memory controller 1236. Further, the memory interface 1234 may include additional circuitry and components, which may be utilized to read and write data in memory coupled via an interconnect 1251. In one example, the memory interface 1234-1 may receive, from a memory controller 1236-1, a write request with data and address(es) to write the data in memory coupled via the interconnect 1251, e.g. second level and third level memory. The memory interface 1234-1 may compress the data using a compression mechanism, generate a fabric packet including the compressed data, a compression mechanism indicator to indicate the compression mechanism, the address(es) and other information. The other information may be header information including a compression indicator to indicate whether the data is compressed or not compressed, a write indicator, and error correction information. The memory interface 1234-1 may send the fabric packet via the interconnect 1251 to write data in level two or level three memory to another memory interface 1234-2.
In another example, the memory interface 1234-1 may receive a read request from a memory controller 1236-1 including one or more address(es). In some instances, the memory interface 1234-1 may compress the address(es) using a compression mechanism, generate a fabric packet including the compressed address(es), a compression mechanism indicator, and other information. The other information may be header information including a compression indicator to indicate whether the address(es) is compressed or not compressed, a read indicator, and error correction information The memory interface 1234-1 may send the read request via the interconnect 1251 to retrieve data via a second level memory or a third level memory. In response to the read request, the memory interface 1234-1 receives a fabric packet including the requested data (compressed), a compression mechanism indicator from the memory interface 1234-2, and a compression indicator. The memory interface 1234-1 may decompress the compressed data based on the compression mechanism indicator and send the data to the cores 107 for processing.
Moreover, a memory interface 1234 may process read and write requests received via an interconnect 1251, e.g. from another memory interface 1234. In one example, the memory interface 1234-2 may receive a read request from memory interface 1234-1 in a fabric packet via the interconnect 1251. The fabric packet may include one or more compressed address(es), a compression mechanism indicator to indicate the compressed address, and other information. The other information may be header information including a compression indicator to indicate whether the data is compressed or not compressed, a read indicator, and error correction information. The memory interface 1234-2 may decompress the one or more address(es) based on the compression mechanism indicator, and send them to circuitry to perform a read operation of level two or level three memory based on the address(es). The memory interface 1234-2 may return the data back to the other memory interface 1234-1 via the interconnect 1251 by compressing the data. The memory interface 1234-2 may generate a fabric packet including a compression mechanism indicator, compressed data, and other information, such as a header including a compression indicator, a read indicator, and error correction information.
Similarly, a memory interface 1234 may receive and process a write request received via an interconnect 1251. In one example, the memory interface 1234-2 may receive the write request in a fabric packet from another memory interface 1234-1 and include a compression mechanism indicator, compressed data, one or more address(es), and other information, e.g. a header having a compression indicator, a write indicator, and error correction information. The memory interface 1234-2 may decompress the data and send the data and address(es) to circuitry to write the data in level two or level three memory, for example.
In some embodiments, the interconnect 1251 may be a high-speed serial link and the memory interfaces 1234 may include circuitry to serialize and deserialize, e.g. SerDes circuitry. In embodiments, the memory interfaces 1234 support various interfaces including, but not limited to serial AT Attachment (SATA), a micro SATA (mSATA), SATA3, SATA4, SATA express (SATAe), universal serial bus (USB), Thunderbolt® 1, 2, and 3, an interface in accordance with the Joint Electronic Device Engineering Council (JEDEC) defined technical standard, such as the MO-297 standard, and the MO-300 standard. Other examples, may include a Next Generation Form Factor (NGFF) interface or an M.2 interface. Embodiments are not limited to these examples and other high speed serial interfaces may be utilized for memory interface 1234 coupled via the interconnect 1251.
In embodiments, the interconnect 1251 may be an optical fabric interconnect or an electrical fabric interconnect. Examples of the interconnect 1251 may include Intel's® scalable memory interconnect (SMI), Quick-Path interconnect (QPI), and Ultra-Path interconnect (UPI). As one skilled in the can appreciate, one or more of these fabric interconnects 1251 may be bandwidth limited. For example, the interconnect 1251 bandwidth may be limited to twenty-five to thirty GigaBytes (GB)/second (s) for UPI or SMI, which may effectively reduce the total bandwidth for a system. Thus, as discussed herein, embodiments include compressing/decompressing data communicated via the interconnect 1251 to reduce the number of bytes for communication. However, embodiments are not limited in this manner.
FIG. 13 illustrates an example of a compute system 1300 that may be similar to compute system 1200, discussed in the FIG. 12. In the illustrated example, the memory interfaces 1334-1 and 1334-2 are illustrated as having components that may be capable of performing one or operations to enable the multi-level memory architecture, as previously discussed. Moreover, liked name components of FIG. 13 may perform similarly or the same as liked named components of FIG. 12. Embodiments are not limited in this manner.
In embodiments, sled 1304-1 may include one or more components including physical compute resources 1305-4-1, such as one or more cores 1307-1, a memory controller 1336-1, and a memory interface 1334-1. The memory interface 1334-1 may include components including a compression/decompression component 1342-1, a fabric controller 1340-1, and a transceiver 1338-1. The sled 1304-1 may also include physical memory resources 1305-3-1 having one or more memory modules 1311-1-x. Moreover, the physical compute resources 1305-4-1 may be coupled with physical memory resources 1305-3-1 via an interconnect 1353-1, which may be a high speed interconnect, bus, trace, and so forth.
Sled 1304-2 is illustrated as having similar components as sled 1304-1. For example, sled 1304-2 may also include physical compute resources 1305-4-2 including one or more cores 1307-2, a memory controller 1336-2, and a memory interface 1334-2. The memory interface 1334-2 may also include a compression/decompression component 1342-2, a fabric controller 1340-2, and a transceiver 1338-2. The physical compute resources 1305-4-2 may be coupled with physical memory resources 1305-3-1 having one or more memory modules 1311-2-x via an interconnect 1353-2, which may be a high speed interconnect, bus, trace, and so forth. Note that embodiments are not limited to the illustrated configuration. In some instances, the sleds 1304-1 and 1304-2 may include more or fewer components.
In some instances, sled 1304-2 may be a memory expansion sled for sled 1304-1. The sled 1304-2 may include memory modules 1311-2-x that may function as level two memory for sled 1304-1, for example. In another example, the memory modules 1311-2-x may function as level two memory and level three memory for sled 1304-1 in a multi-level memory architecture. These memory modules 1311-2 may include volatile memory device and non-volatile memory devices, as discussed above with respect to memory modules 1211 of FIG. 12. The memory modules 1311-2-x functioning as level two memory may include memory modules having volatile memory devices, while the memory modules 1311-2-x functioning as level three memory may include one or more byte addressable write-in-place non-volatile memory devices. Further and with respect to this example configuration, which embodiments are not limited to, the memory interface 1334-1 of sled 1304-1 may communicate read and write requests with memory interface 1334-2 of sled 1304-2 utilizing the memory modules 1311-2-x as second level memory, and in some instances, third level memory for sled 1334-1.
In embodiments, the memory interface 1334-1 may include a compression/decompression component 1342-1 to perform compression and decompression operations. The compression/decompression component 1342-1 may compress data to send for communication via an interconnect 1351 and decompress data received via the interconnect 1351. For example, a compression/decompression component 1342-1 may determine a compression mechanism to perform on data to send to second level memory or third level memory. The compression mechanism may be based on a repeating pattern in the data and address(es). Thus, the same data may be communicated using less bytes. Prior systems fail to use compression/decompression to write and read information in memory, and therefore, communicate more bytes for the same data.
For example, in prior systems to write zero (0) to a cache line (64 bytes) at an address, the prior system sends information including a header frame, access type, address, data, ECC, and a footer frame. The header frame may be two (2) bytes, the access type may be one (1) byte, the address may be eight (8) bytes, the data may be 64 bytes (64×8 clocks of 0), the ECC may be two (2) bytes, and the footer frame may be two (2) bytes. Thus, a total of 84 bytes may be sent to write zero to a cache line in a prior system. In embodiments discussed herein, the number of bytes may be reduced to communicate the same data. Continuing with the previous example, to write 0 to a cache line, using embodiments discussed herein, 23 bytes may be communicated instead of 84 bytes. More specifically, a byte pattern repeat compression mechanism may be utilized and indicated by an OpCode of zero ( ) as illustrated in FIG. 14B. The header frame may be two (2) bytes, the address may be eight (8) bytes, the access type may be one (1) byte, the data may be 1 byte (8 clocks of 0), the ECC may be eight (8) bytes, and the footer frame may be two (2) bytes.
In embodiments, the interconnect 1351 may be similar to interconnect 1251 and may be an optical fabric interconnect or an electrical fabric interconnect. Examples of the interconnect 1251 may include Intel's® scalable memory interconnect (SMI), Quick-Path interconnect (QPI), and Ultra-Path interconnect (UPI). As one skilled in the can appreciate, one or more of these fabric interconnects 1251 may be bandwidth limited. For example, the interconnect 1251 bandwidth may be limited to twenty-five to thirty GigaBytes (GB)/second (s) for UPI or SMI, which may effectively reduce the total bandwidth for a system. Thus, as discussed herein, embodiments include compressing/decompressing data communicated via the interconnect 1251 to reduce the number of bytes for communication. However, embodiments are not limited in this manner.
FIG. 14A illustrates an example fabric packet 1400 to send and receive data via the interconnect 1351 and FIG. 14B illustrates an example compression mechanism indicator (CMI) table 1450 that may indicate which compression mechanism is used based on the CMI in a CMI field 1408-1 of a fabric packet 1400. For example, a “0” in the CMI field 1408-1 may indicate that a Byte Pattern Repeat compression mechanism is being used and the number of data bytes is one (1) in the fabric packet 1400. In another example, a CMI of “1” in a CMI field 1408-1 may indicate that a Word (2 bytes) Pattern Repeat compression mechanism is being used and the number of data bytes in a fabric packet 1400 is two (2). Compression mechanisms may also include double word (Dword) (4 bytes) Pattern Repeat and quad word (Qword) (8 bytes) Pattern Repeat, as illustrated in the CMI table 1450. Embodiments are not limited in this manner.
In some instances, the compression/decompression component 1342-1 may use compression logic or a compression algorithm as the compression mechanism when sending data via the interconnect 1351. For example, the compression mechanism may be compression logic or an algorithm to perform lossless data compression on the data. In one example, a run-length encoding (RLE) algorithm may be used on the data such that a repeating pattern and the length of the repeating pattern are indicated in the compressed data. Moreover, the compression algorithm may also be indicated by a CMI in a CMI field 1408-1. For example, the CMI table 1450 has compression logic x having a length (data bytes) of n is indicated by CMI of “4”. In example using this compression algorithm, a repeating pattern of 0×55AA_55AA_55AA_55AA may be represented with x being 55AA and n (length of repeat) being 4. The original sequence would require sending 84 bytes of information while using the compression logic would send 24 bytes, e.g. 2 bytes header, 8 bytes address, 1 byte access type, 1 byte Opcode, 2 bytes of data (55AA), 8 bytes ECC, and 2 bytes footer. CMI table 1450 also indicates another compression logic y having a length (data bytes) of m with a CMI of “5” for a different compression logic configuration. Any compression logic or algorithm may be used and indicated by a CMI. Examples of compression algorithms include Lempel-Ziv 1978, Lempel-Ziv Fast (LZF), DEFLATE, bzip2, Lempel-Ziv-Markov chain algorithm, Lempel-Ziv-Oberhumer, and so forth. Note that CMI table 1450 only includes six (0-5) CMIs; however, embodiments are not limited in this manner. In embodiments any number of CMIs may be utilized and defined for use in communicating data via an interconnect 1351.
In embodiments, a compression/decompression component 1342-1 may perform decompression operations to decompress compressed data sent via the interconnect 1351. The compression/decompression component 1342-1 may determine that compression was used based on a compression indicator (CI) in a CI field 1402-1 of the fabric packet 1400. In some instances, the CI field 1402-1 may be a single bit in the header 1402, which may indicate whether compression was used or not when generating the fabric packet 1400. A “1” may indicate that compression was used and a “0” may indicate that compression was not used, or vice versa.
In embodiments, a compression/decompression component 1342-1 may determine which compression mechanism is used based on the CMI in the CMI field 1408-1 of the data 1408. As previously discussed, the CMI may be an OpCode that indicates a compression mechanism, as illustrated in FIG. 14B. The compression mechanism may include a Byte Pattern Repeat, a Word Pattern Repeat, a Dword Pattern Repeat, a Qword Pattern repeat, and one or more compression algorithms. Once the compression/decompression component 1342-1 determines which compression mechanism was utilized, the compression/decompression component 1342-1 may decompress or reconstruct the data, e.g. insert the missing bits in the data based on a repeating pattern or algorithm used. Embodiments are not limited in this manner. Note that memory interface 1334-2 of sled 1304-2 also includes a compression/decompression component 1342-2 capable of performing all of the above-discussed operations.
In embodiments, the memory interface 1334-1 may also include a fabric controller 1340-1 which may be used to generate fabric packets to communicate via the interconnect 1351, such as fabric packet 1400 of FIG. 14A. A fabric packet 1400 may include a header 1402 which may include a destination for the fabric packet 1400. In some instances, the header 1402 may include a “path” which may include devices and controllers to route the fabric packet 1400 the intended destination.
The header 1402 may also include additional information. For example, header 1402 may also include a compression indicator field 1402-1, which may be a bit to indicate whether the data payload of the fabric packet 1400 is compressed or not compressed. In one example, a “1” in the compression indicator field 1402-1 may indicate that the data payload is compressed and a “0” may indicate that the data payload is not compressed. However, embodiments are not limited to this example. In some instances, the opposite may hold true, e.g. a “1” may indicate no compression and a “0” may indicate compression.
In embodiments, the fabric packet 1400 may also include an address field 1404, which may include a location in memory to store the data. In some embodiments, the address field 1404 may include a memory address or a beginning memory address to store the data and may be in a hexadecimal format. In some instances, the address field 1404 may include a range of addresses to store the data in memory. In embodiments, the memory address may be compressed in a similar manner as the data. For example, repeating patterns in the memory address may be replaced by an OpCode or compression logic may be utilized to compress the address. In these embodiments indicators, in the fabric packet 1400 may indicate that the address is compressed, e.g. an address compression indicator, and a mechanism used to compress the address, e.g. an address compression indicator mechanism. The compression mechanisms utilized may be the same as those listed in FIG. 14B.
The fabric packet 1400 may also include an access or a read/write field 1406 that may indicate whether the fabric packet 1400 is a write request or a read request. In some instances, the read/write field 1406 may include a single bit which when set to “1” may indicate the fabric packet 1400 is a write request and when set to “0” may indicate the fabric packet 1400 is a read request, or vice versa. Embodiments are not limited in this manner. In some instances, the read/write field 1406 may be longer than a single bit.
The fabric packet 1400 also includes a data field 1408 to hold a data payload for use in reading and writing information to and from memory. For example, data may be read from memory and communicated via an interconnect 1351 in a fabric packet 1400 to be used by cores 1307. In another example, data may be sent in the data field 1408 for storage in memory for a write request.
In embodiments, the data communicated in the data field 1408 may be compressed for communication via the interconnect 1351. The data field 1408 may include a CMI field 1408-1 to hold a CMI. The CMI may be used to indicate a value, such as an OpCode, which may correspond with a compression mechanism used for compression. FIG. 14B illustrates a number of CMIs (OpCodes) corresponding to a compression mechanism, for example. Embodiments are not limited in this manner.
In embodiments, the fabric packet 1400 may also include an ECC/CRC field 1410 to include error detection and correction information. Typical error correction code techniques may be utilized in embodiments discussed herein. For example, a hash function, parity bits, cyclic redundancy check (CRC), and so forth may be utilized to perform error detection and correction for a fabric packet 1400. This information may be stored in the ECC/CRC field 1410. Moreover, the information may be generated by the fabric controller 1340-1 for communication via the interconnect 1351. Note that the fabric controller 1340-2 of memory interface 1334-2 may perform and generate a fabric packet 1400 as discussed above.
In embodiments, the memory interface 1334-1 may include a transceiver 1338-1 capable of sending and receiving information and data including one or more fabric packets, such as fabric packet 1400. In embodiments, the transceiver 1338-1 may be capable of communicating the information and data optically and include an optical transmitter and receiver. The transceiver 1338-1 may also be capable of communicating information and data via electrically via an electrical transmitter and receiver, e.g. an electrical interconnect. Memory interface 1334-2 of sled 1304 may include circuitry to communicate information and data optically and electrically. Embodiments are not limited in this manner.
In embodiments, the memory interfaces 1334-1 and 1334-2 may also include other circuitry, such as SerDes circuitry, to convert parallel data to serial data, and vice versa for communication via the interconnect 1351. Thus, in one example, read and write request may be converted from parallel data to serial data for communication between the sleds 1304-1 and 1304-2. Further, the data communicated as serial data may be converted back to parallel data by the SerDes circuitry on the receiving end of the data. Embodiments are not limited in this manner.
In some embodiments, the memory interface 1334-1 may communicate information and data including fabric packets using a transaction protocol. The transaction protocol may enable transaction-based data transfers using the interconnect 1351. For example, the interconnect may support a Quick-Path Interconnect transaction protocol that may employ packet-based transfers using a multi-layer protocol architecture. Among its features is support for coherent transactions (e.g., memory coherency). In embodiments, to increase memory transaction bandwidth, a Fully Buffered dual in-line memory module (FB-DIMM) architecture is employed, which introduces an advanced memory buffer (AMB) between the memory controller and a memory module. Unlike the parallel bus architecture of traditional DRAMs, the interconnect 1351 can be a serial interconnect that enables an increase in the width of the memory without increasing the pin count of the memory controller beyond a feasible level. In another example, the interconnect 1351 may be an SMI and include Scalable Memory Buffers (SMB), and an Omnipath Interconnect.
FIG. 15 illustrates an embodiment of a memory module 1511, which may be utilized as one or more of the memory modules discussed herein. In the illustrated embodiment, the memory module 1511 may have a larger form factor then current DIMM form factors, such as Joint Electronic Device Engineering Council (JEDEC) defined technical standard JESD248 (“DDR Non-Volatile Dual In-Line Memory Module (NVDIMM Design Standard”), JEDEC Module 4.20.27 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification”), JESD79-4A (“DDR4 SDRAM Standard”), and JEDEC Module 4.20.28 (“288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification”). The larger form factor may be a size such that it can support and include more data devices than a typical memory module. For example, the memory module 1511 may include thirty-two (32) data memory devices 1517 to store information and data, while current memory modules only have eight (8) data devices. Further, the memory module 1511 may have a size large enough to support eight (8) additional spare devices 1519. However, the memory module 1511 may fit into a current memory slot utilizing connector 1515, such as one or more of slots as defined in one or more JEDEC standards above.
In embodiments, the memory module 1511 may provide multiple channel bandwidth capabilities. The multiple channel bandwidth capabilities may enable each of the multiple channels to be allocated a same size or amount of memory to keep the bandwidth even across all channels and enable interleaving across all channels. For example, the data devices 1517 may provide 96 GigaBytes (GBs) of memory, which may be spread across three (3) channels. Each channel may be allocated 32 GBs of memory, which may be interleaved across each of the channels.
Further, since the memory module 1511 includes a larger amount of data devices 1517 that current solutions, the memory module's 1511 memory controller (not shown) may also have additional choices for error correction coding (ECC) and Chipkill implementations by spreading across more data devices 1517. The ECC and Chipkill support may be provided by the spare devices 1519. The larger number of data devices 1517 also enables cache lines to be accessed in less clock cycles than prior solutions. For example, prior memory solutions may have ×4, ×8, ×16 bit access, and a DIMM in accordance with one or more of the JEDEC standards above, would typically come with 8 or 9 data devices. Thus, the total number of bits that could be accessed in a clock cycle is 8×4=32 (4 bytes). To access 64 bytes, the device to be accessed 16 clocks. However, in the illustrated memory module 151, having 32 data devices, may support a 64 byte cache line may be accessed in 2 clock cycles.
FIG. 16 illustrates an embodiment of logic flow 1600 and logic flow 1650. The logic flows 1600 and 1650 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flows 1600 and 1650 may illustrate operations performed by a memory interface of a sled having physical compute resources. More specifically logic flow 1600 may be directed to a memory interface sending data to a second level memory and third level memory coupled via an interconnect, the data may be written to the second level and third level memory as part of a write request. In some instances, the data may be written to only a second level memory, only a third level memory, or a combination of second level memory and third level memory. Embodiments are not limited in this manner.
Logic flow 1650 is directed to a memory interface receiving data via an interconnect, which may be in response to a read request to read data from a second level memory and third level memory. Similarly, embodiments include sending read request to read data from only a second level memory, only a third level memory, or a combination thereof. Embodiments are not limited in this manner.
With respect to logic flow 1600, embodiments include receiving data to write to second level memory or third level memory at block 1602. In embodiments, the data may be received by a memory interface from a core, via a memory controller. The data may be accompanied by address information to store the data in second level or third level memory, which may be level two memory or level three memory coupled via interconnect.
At block 1604, the logic flow 1600 may include compressing the data to communicating via an interconnect. For example, a compression mechanism, such as one illustrated in FIG. 14B and previously discussed may be utilized to compress the data. In some instances, the data may be compressed in a lossless manner, e.g. no data is lost due to compression, using a compression algorithm. In some embodiments, the data may be compressed by replacing a repeating pattern of bytes, words, Dwords, and Qwords with a compression mechanism indicator (OpCode) and a bit indication of the repeating bits. Embodiments are not limited in this manner.
At block 1606, the logic flow 1600 may generate a fabric packet to communicate via an interconnect. The fabric packet may include a header, an address, a read/write indication, data (compressed), and ECC/CRC information, as illustrated in FIG. 14A. In embodiments, the header of the fabric packet may include a compression indicator (CI) to indicate whether the data in the packet is compressed or not compressed. Further, the data may include a compression mechanism indicator to indicate the mechanism used to compress the data and a bit indication of the repeating bit.
The logic flow 1600 also includes sending the fabric packet via an interconnect to the second level or third level memory. In some embodiments, the second level memory and the third level memory may be in a different sled then the physical processing resources and may be electrically or optically coupled via the interconnect. In embodiments, the memory interface may utilize a transaction protocol and send the fabric packet in a serial data format.
With respect to logic flow 1650, embodiments may include receiving a fabric packet via an interconnect at block 1652. As discussed, the fabric packet may be received in response to sending a read request to read data from a second level memory or third level memory coupled via the interconnect.
At block 1654, the logic flow 1650 includes determining a compression mechanism used to compress the data communicated in the fabric packet. For example, a memory interface may determine the compression mechanism based on a CMI in the fabric packet. Moreover, the memory interface may use the CMI to perform a lookup in a table or file, such as table 1450 of FIG. 14B, to determine the compression mechanism.
In embodiments, the logic flow 1650 may include decompressing the compressed data to generate data requested to be read from memory at block 1656. Moreover, the memory interface may use the compressed data and reconstruct the data based on the compression mechanism. For example, the memory interface may generate the data based on a repeating bit indication indicating which bit is repeating and the CMI indicating a number of bits that are repeating, e.g. a byte, a word, a Dword, or a Qword. At block 1658, the logic flow 1650 may include sending the data to one or more cores for use by the cores in processing.
FIG. 17 illustrates an embodiment of logic flow 1700 and logic flow 1750. The logic flows 1700 and 1750 may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flows 1700 and 1750 may illustrate operations performed by a memory interface of a sled having physical memory resources utilized by physical compute resources of another sled. More specifically logic flow 1700 may be directed to a memory interface receiving data for storage in a second level memory or a third level memory from a sled coupled via an interconnect, the data may be written to the second level or third level memory as part of a write request. Logic flow 1750 is directed to a memory interface sending data via an interconnect which may be in response to a read request to read data from the second level memory or third level memory. However, embodiments are not limited in this manner, and one or more operations may be performed by other components or systems discussed herein, such as a memory controller.
With respect to logic flow 1700, embodiments may include receiving a fabric packet via an interconnect at block 1702. As discussed, the fabric packet may be received as part of a write request to write data into second level and third level memory.
At block 1704, the logic flow 1700 includes determining a compression mechanism used to compress the data communicated in the fabric packet. For example, a memory interface may determine the compression mechanism based on a CMI in the fabric packet. Moreover, the memory interface may use the CMI to perform a lookup in a table or file, such as table 1450 of FIG. 14B, to determine the compression mechanism.
In embodiments, the logic flow 1700 may include decompressing the compressed data to generate data requested to be read from memory at block 1706. Moreover, the memory interface may use the compressed data and reconstruct the data based on the compression mechanism. For example, the memory interface may generate the data based on a repeating bit indication indicating which bit is repeating and the CMI indicating a number of bits that are repeating, e.g. a byte, a word, a Dword, or a Qword. At block 1708, the logic flow 1700 may include sending the data to the second level and third level memory and a memory controller for the second level and third level memory to be written in data devices.
With respect to logic flow 1750, embodiments include receiving a read request via an interconnect to read data from a second level memory or a third level memory at block 1752. In embodiments, the read request may include one or more addresses to identify the data to read from the second level memory or third level memory. The memory interface may send the information to a memory controller which may perform a read operation. In response to the read operation, the memory interface may receive the data at block 1754.
At block 1756, the logic flow 1750 may include compressing the data to communicate via an interconnect. For example, a compression mechanism, such as one illustrated in FIG. 14B and previously discussed, may be utilized to compress the data. In some instances, the data may be compressed in a lossless manner, e.g. no data is lost due to compression, using a compression algorithm. In some embodiments, the data may be compressed by replacing a repeating pattern of bytes, words, Dwords, or Qwords with a compression mechanism indicator (OpCode) and a bit indication of the repeating bits. Embodiments are not limited in this manner.
At block 1758, the logic flow 1750 may generate a fabric packet to communicate via an interconnect. The fabric packet may include a header, an address, a read/write indication, data (compressed), and ECC/CRC information, as illustrated in FIG. 14A. In embodiments, the header of the fabric packet may include a compression indicator (CI) to indicate whether the data in the packet is compressed or not compressed. Further, the data may include a compression mechanism indicator to indicate the mechanism used to compress the data and a bit indication of the repeating bit.
The logic flow 1750 also includes sending the fabric packet via an interconnect to the request sled (and cores). In embodiments, the memory interface may utilize a transaction protocol and send the fabric packet in a serial data format. Embodiments are not limited in this manner.
The detailed disclosure now turns to providing examples that pertain to further embodiments. Examples one through twenty-five (1-25) provided below are intended to be exemplary and non-limiting.
In a first example, embodiments may be directed to a system, a device, an apparatus including a memory interface coupled to a memory controller, the memory interface to generate compressed data based on a compression mechanism to be applied to data, and generate a fabric packet including a compression mechanism indicator, the compressed data, and an address to write the data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate which compression mechanism is applied to the data.
In a second example and in furtherance of the previous example, a system, a device, an apparatus, and so forth include the memory interface to process utilizing the the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and a compression alogrithm.
In a third example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth include the second level memory comprising one or more volatile memory devices and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.
In a fourth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may the memory interface to send the compressed data to the at one of the second level memory and the third level memory via an interconnect comprising one of an optical interconnect and an electrical interconnect.
In a fifth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface to receive another fabric packet comprising compressed data and another compression mechanism indicator, and decompress the received compressed data based on the another compression mechanism indicator.
In a sixth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth include a first level memory comprising volatile memory devices, one or more processing cores, and the memory interface to send the decompressed data to the one or more cores to process.
In a seventh example and in furtherance of any of the previous examples, a method may include generating compressed data based on a compression mechanism to be applied to data , and generating a fabric packet including a compression mechanism indicator, the compressed data, and an address to write the data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate which compression mechanism is applied to the data.
In an eighth example and in furtherance of any of the previous examples, a method to process the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and a compression alogrithm.
In a ninth example and in furtherance of any of the previous examples, a method may include sending the fabric packet to the second level memory comprising one or more volatile memory devices and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices .
In a tenth example and in furtherance of any of the previous examples, a method may include sending the compressed data to the at one of the second level memory and the third level memory via an interconnect comprising one of an optical interconnect and an electrical interconnect.
In an eleventh example and in furtherance of any of the previous examples, a method may include receiving another fabric packet comprising compressed data and another compression mechanism indicator, and decompressing the received compressed data based on the another compression mechanism indicator.
In a twelfth example and in furtherance of any of the previous examples, may include a method including sending the another data to one or more cores of a computer processing unit.
In a thirteenth example and in furtherance of any of the previous examples, may include a system, a device, an apparatus, and so forth may include a memory interface coupled to a memory controller, the memory interface to receive a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and decompress the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator .
In a fourteenth example and in furtherance of any of the previous examples, may include a system, a device, an apparatus, and so forth may include the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and compression alogrithm.
In a fifteenth example and in furtherance of any of the previous examples, may include a system, a device, an apparatus, and so forth may include a memory interface to the memory interface to receive the compressed data via an interconnect comprising one of an optical interconnect and an electrical interconnect.
In a sixteenth example and in furtherance of any of the previous examples, may include a system, a device, an apparatus, and so forth may include receive a read request, retreive data from at least one of the second level memory and the third level memory based on the read request, and generate compressed data based using data received from the at least one of the second level memory and the third level memory.
In a seventeenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the memory interface to generate another fabric packet comprising the compressed data and an another compression mechanism indicator, and send the fabric packet via an interconnect to a computer processing unit.
In an eighteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the second level memory comprising one or more volatil memory devices, and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices .
In a nineteenth example and in furtherance of any of the previous examples, a system, a device, an apparatus, and so forth may include the second level memory and the third level memory.
In a twentieth example and in furtherance of any of the previous examples, a method may include receiving a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and decompressing the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator.
In a twenty-first example and in furtherance of any of the previous examples, a method may include the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and compression alogrithm.
In a twenty-second example and in furtherance of any of the previous examples, a method may include receiving the compressed data via an interconnect comprising one of an optical interconnect and an electrical interconnect.
In a twenty-third example and in furtherance of any of the previous examples, a method to receiving a read request, retreiving data from at least one of the second level memory and the third level memory based on the read request, and generating compressed data based using data received from the at least one of the second level memory and the third level memory.
In a twenty-fourth example and in furtherance of any of the previous examples, a method may include generating another fabric packet comprising the compressed data and an another compression mechanism indicator, and sending the fabric packet via an interconnect to a computer processing unit .
In a twenty-fifth example and in furtherance of any of the previous examples, a method include processing a fabric packet with the second level memory comprising one or more volatil memory devices, and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.
Some embodiments may be described using the expression “one embodiment” or “an embodiment” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Further, some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms “connected” and “coupled” to indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
It is emphasized that the Abstract of the Disclosure is provided to allow a reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the preceding Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are at this moment incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels and are not intended to impose numerical requirements on their objects.
What has been described above includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

Claims

What is claimed is:

1. An apparatus, comprising:

a memory interface coupled to a memory controller, the memory interface to:

generate compressed data based on a compression mechanism to be applied to data, and

generate a fabric packet including a compression mechanism indicator, the compressed data, and an address to write the data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate which compression mechanism is applied to the data.

2. The apparatus of claim 1, the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and a compression alogrithm.

3. The apparatus of claim 1, the second level memory comprising one or more volatile memory devices and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.

4. The apparatus of claim 1, the memory interface to send the compressed data to the at one of the second level memory and the third level memory via an interconnect comprising one of an optical interconnect and an electrical interconnect.

5. The apparatus of claim 1, the memory interface to:

receive another fabric packet comprising compressed data and another compression mechanism indicator; and

decompress the received compressed data based on the another compression mechanism indicator.

6. The apparatus of claim 5, comprising:

a first level memory comprising volatile memory devices;

one or more processing cores; and

the memory interface to send the decompressed data to the one or more cores to process.

7. A computer-implemented method, comprising:

generating compressed data based on a compression mechanism to be applied to data, and

generating a fabric packet including a compression mechanism indicator, the compressed data, and an address to write the data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate which compression mechanism is applied to the data.

8. The computer-implemented method of claim 7, the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and a compression alogrithm.

9. The computer-implemented method of claim 7, the second level memory comprising one or more volatile memory devices and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.

10. The computer-implemented method of claim 7, comprising sending the compressed data to the at one of the second level memory and the third level memory via an interconnect comprising one of an optical interconnect and an electrical interconnect.

11. The computer-implemented method of claim 7, comprising:

receiving another fabric packet comprising compressed data and another compression mechanism indicator; and

decompressing the received compressed data based on the another compression mechanism indicator.

12. The computer-implemented method of claim 11, comprising sending the another data to one or more cores of a computer processing unit.

13. An apparatus, comprising:

a memory interface coupled to a memory controller, the memory interface to:

receive a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and

decompress the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator.

14. The apparatus of claim 13, the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and compression alogrithm.

15. The apparatus of claim 13, the memory interface to receive the compressed data via an interconnect comprising one of an optical interconnect and an electrical interconnect.

16. The apparatus of claim 13, the memory interface to:

receive a read request;

retreive data from at least one of the second level memory and the third level memory based on the read request; and

generate compressed data based using data received from the at least one of the second level memory and the third level memory.

17. The apparatus of claim 16, the memory interface to:

generate another fabric packet comprising the compressed data and an another compression mechanism indicator; and

send the fabric packet via an interconnect to a computer processing unit.

18. The apparatus of claim 13, wherein the second level memory comprising one or more volatil memory devices, and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.

19. The apparatus of claim 18, comprising:

the second level memory; and

the third level memory.

20. A computer-implemented method, comprising;

receiving a fabric packet comprising a compression mechanism indicator, compressed data, and an address to write data in at least one of a second level memory and a third level memory, the compression mechanism indicator to indicate a compression mechanism applied to data to generate the compressed data, and

decompressing the compressed data based on the compression mechansism applied to the compressed data and indicated in the compression mechanism indicator.

21. The computer-implemented method of claim 20, the compression mechanism indicator to indicate the compression mechanism is one of a byte pattern repeat, a word pattern repeat, a double word (Dword) pattern repeat, a quad word (Qword) pattern repeat, and compression alogrithm.

22. The computer-implemented method of claim 20, comprising receiving the compressed data via an interconnect comprising one of an optical interconnect and an electrical interconnect.

23. The computer-implemented method of claim 20, comprising:

receiving a read request;

retreiving data from at least one of the second level memory and the third level memory based on the read request; and

generating compressed data based using data received from the at least one of the second level memory and the third level memory.

24. The computer-implemented method of claim 23, comprising:

generating another fabric packet comprising the compressed data and an another compression mechanism indicator; and

sending the fabric packet via an interconnect to a computer processing unit.

25. The computer-implemented method of claim 20, wherein the second level memory comprising one or more volatil memory devices, and the third level memory comprising one or more byte addressable write-in-place non-volatile memory devices.