US20170194544A1 - Light emitting device and a method of making the same - Google Patents

Light emitting device and a method of making the same Download PDF

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Publication number
US20170194544A1
US20170194544A1 US15/392,860 US201615392860A US2017194544A1 US 20170194544 A1 US20170194544 A1 US 20170194544A1 US 201615392860 A US201615392860 A US 201615392860A US 2017194544 A1 US2017194544 A1 US 2017194544A1
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Prior art keywords
circuit pattern
layer
light emitting
emitting device
pattern layer
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Abandoned
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US15/392,860
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English (en)
Inventor
Pen-Yi Liao
Chia-Tai Chen
Wen-Chia TSAI
Jing-Yi YANG
Ai-Ling Lin
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Taiwan Green Point Enterprise Co Ltd
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Taiwan Green Point Enterprise Co Ltd
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Publication of US20170194544A1 publication Critical patent/US20170194544A1/en
Assigned to TAIWAN GREEN POINT ENTERPRISES CO., LTD reassignment TAIWAN GREEN POINT ENTERPRISES CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHIA-TAI, LIAO, PEN-YI, TSAI, WEN-CHIA, YANG, Jing-yi, LIN, AI-LING
Priority to US16/182,381 priority Critical patent/US10446731B2/en
Abandoned legal-status Critical Current

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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00—Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
    • F21K9/90—Methods of manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V23/00—Arrangement of electric circuit elements in or on lighting devices
    • F21V23/001—Arrangement of electric circuit elements in or on lighting devices the elements being electrical wires or cables
    • F21V23/002—Arrangements of cables or conductors inside a lighting device, e.g. means for guiding along parts of the housing or in a pivoting arm
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V29/00—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems
    • F21V29/50—Cooling arrangements
    • F21V29/70—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks
    • F21V29/71—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks using a combination of separate elements interconnected by heat-conducting means, e.g. with heat pipes or thermally conductive bars between separate heat-sink elements
    • F21V29/713—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks using a combination of separate elements interconnected by heat-conducting means, e.g. with heat pipes or thermally conductive bars between separate heat-sink elements in direct thermal and mechanical contact of each other to form a single system
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V29/00—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems
    • F21V29/50—Cooling arrangements
    • F21V29/70—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks
    • F21V29/74—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks with fins or blades
    • F21V29/76—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks with fins or blades with essentially identical parallel planar fins or blades, e.g. with comb-like cross-section
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V29/00—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems
    • F21V29/85—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems characterised by the material
    • F21V29/89—Metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements

Definitions

  • the disclosure relates to a light emitting device, and more particularly to a light emitting device with a heat sinking substrate, and a method of making the same.
  • U.S. Pat. No. 7,683,474 B2 discloses a conventional light emitting diode (LED) device 30 that includes a metal heat sinking base 64 , a walled container 32 disposed on the metal heat sinking base 64 and defining a surrounded volume, first and second conductors 40 , 42 formed on the metal heat sinking base 64 within the surrounded volume of the walled container 32 , a first pad 50 formed on the first conductor 40 , a second pad 52 formed on the second conductor 42 , at least one LED chip 44 disposed on the first pad 50 , a wire 48 interconnecting the LED chip 44 and the second. pad 52 , and an encapsulant 54 filling the surrounded volume of the walled container 32 .
  • LED light emitting diode
  • the first conductor 40 and the second conductor 42 formed on the metal heat sinking base 64 are respectively electrically connected to the LED chip 44 through the first pad 50 and the second pad 52 .
  • electric power is supplied to the LED chip 44 through the first and second conductors 40 , 42 , and heat generated by operation of the LED chip 44 is also dissipated by the metal heat sinking base 64 through the first and second conductors 40 , 42 .
  • an adhesive layer (not shown) required to be disposed between the first conductor 40 and the metal heat sinking base 64 so as to securely dispose the first conductor 40 , which exerts a dual function in electric power transmission and heat dissipation, on the metal heat sinking base 64 .
  • Inclusion of the adhesive layer tends to decrease heat dissipating efficiency of the first conductor 40 .
  • the first conductor 40 performs heat dissipation and electric power transmission at the same time, and heat dissipating efficiency of the first conductor 40 is unavoidably decreased and cannot he fully exploited. Therefore, there is plenty of room for improving the heat dissipating efficiency of the LED device.
  • an object of the disclosure is to provide a light emitting device that can alleviate at least one of the drawbacks of the prior art.
  • Another object of the disclosure is to provide a method of making a light emitting device.
  • a light emitting device includes a heat sinking substrate, an electrically insulating layer, a circuit pattern layer, and at least one light emitting diode (LED) chip.
  • LED light emitting diode
  • the electrically insulating layer is partially formed on the heat sinking substrate so as to expose a portion of the heat sinking substrate.
  • the circuit pattern layer is formed on the electrically insulating layer.
  • the LED chip is electrically connected to the circuit pattern layer, and is indirectly and non-electrically mounted to the portion of the heat sinking substrate exposed from the electrically insulating layer and the circuit pattern layer.
  • a method of making a light emitting device includes: partially forming an electrically insulating layer on a heat sinking substrate so as to expose a portion of the heat sinking substrate; forming a circuit pattern layer on the electrically insulating layer; and electrically connecting at least one LED chip to the circuit pattern layer, and indirectly and non-electrically mounting the LED chip to the portion of the heat sinking substrate exposed from the electrically insulating layer and the circuit pattern layer.
  • FIG. 1 is a schematic cross sectional view illustrating a conventional light emitting diode device of U.S. Pat. No. 7,683,474 B2;
  • FIG. 2 is a fragmentary schematic view illustrating an embodiment of a light emitting device according to the disclosure
  • FIG. 3 is a fragmentary schematic view illustrating another configuration of the embodiment
  • FIG. 4 is a fragmentary schematic view illustrating a modification of the embodiment.
  • FIG. 5 is a fragmentary schematic view illustrating another modification of the embodiment.
  • an embodiment of a light emitting device includes a heat sinking substrate 2 , an electrically insulating layer 3 , a circuit pattern layer 4 , and at least one light emitting diode (LED) chip 6 .
  • LED light emitting diode
  • the heat sinking substrate 2 has a top surface 22 and a bottom surface 23 opposite to the top surface 22 and is made from a metallic material, such as aluminum alloys and copper alloy, etc.
  • the heat sinking substrate 2 is formed with a plurality of heat sinking fins 21 , such as aluminum extruded fins, extending from the bottom surface 23 for being in contact with an atmosphere or an external fluid.
  • the heat sinking substrate 2 may be selected from, but not limited to, other conventional types of heat sinks or combinations thereof.
  • the top and bottom surfaces 22 , 23 of the heat sinking substrate 2 may be coated with a protecting paint layer, a weatherproof paint layer, an electrically insulating paint layer, etc.
  • the heat sinking fins 21 are not coated with the protecting paint layer.
  • the heat sinking substrate 2 may have, but not limited to, a curved configuration that is applicable to a curved. contour of a target object, such as a vehicle headlight.
  • the top surface 22 may have a curved surface in contact with an inner curved surface of a car headlight (not shown).
  • the top surface 22 of the heat sinking substrate 2 unlike the fins 21 , is a curved surface.
  • the configuration of the heat sinking substrate 22 of the disclosure may be modified based on actual applications.
  • the electrically insulating layer 3 is partially formed on the top surface 22 of the heat sinking substrate 2 so as to expose a portion of the top surface 22 of the heat sinking substrate 2 .
  • the electrically insulating layer 3 is made from an electrically insulating material that may be selected from epoxy resin, acrylic resin, and so on.
  • the electrically insulating layer 3 is desired to have a thickness as thin as possible to reduce the effect of heat conduction while maintaining electric insulativity. Preferably, the thickness ranges between 20 ⁇ m and 40 ⁇ m.
  • the circuit pattern layer 4 is formed on the electrically insulating layer 3 and has a predetermined pattern that is based on an equivalent circuit design of the light emitting device.
  • the circuit pattern layer 4 includes an active layer 41 which may include a polymer, a catalytic metal, or a combination thereof and which is formed on the electrically insulating layer 3 , and first electroless-plated metal layer 42 which is formed on the active layer 41 .
  • the circuit pattern layer 4 is exemplified to further include, but not limited to, a second electroless-plated metal layer 42 ′.
  • the circuit pattern layer 4 may include the first electroless-plated metal layer 42 interposed between the active layer 41 and the second electroless-plated metal layer 42 ′.
  • the catalytic metal of the active layer 41 may be selected from the group consisting of palladium (PD), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), silver (Aq), copper (Cu), nickel (Ni), iron (Fe) and alloys thereof.
  • the first electro less-plated metal layer 42 may be made from a metal material selected from the group consisting of copper (Cu), nickel (Ni) and alloys thereof.
  • the second electroless-plated metal layer 42 ′ may be made from a metal material selected from the group consisting of platinum (Pt), silver (Ag), tin (Sn), gold (Au), palladium (Pd) and alloys thereof, and is used for protecting the first electroless-plated metal layer 42 from oxidation.
  • the second electroless-plated metal layer 42 ′ can serve as an electrode for external electrical connection.
  • the LED chip 6 is electrically connected to the circuit pattern layer 4 and indirectly and non-electrically mounted to the portion of the heat sinking substrate 2 exposed from the electrically insulating layer 3 and the circuit pattern layer 4 .
  • the LED chip 6 is electrically connected to the circuit pattern layer 4 in a wire-bonding manner.
  • the light emitting device further includes an electrically insulating and thermally conductive interlayer 5 interposed between the LED chip 6 and the portion of the heat sinking substrate 2 exposed from the electrically insulating layer 3 and the circuit pattern layer 4 .
  • the interlayer 5 is made from a thermal interface material (TIM).
  • TIM thermal interface material
  • the interlayer 5 may be selected from one of thermal grease, a thermal pad, a thermal adhesive, and so on. Therefore, during the operation of the light emitting device, heat generated by the LED chip 6 can be dissipated to the heat sinking substrate 2 through the interlayer 5 .
  • a number of the LED chip is not limited to one.
  • the circuit pattern layer 4 is configured to have a plurality of spaced apart triple-stacked portions, i.e., each of the spaced apart triple-stacked portions has a structure of the first electroless-plated metal layer 42 interposed between the active layer 41 and the second electroless-plated metal layer 42 ′.
  • the LED chip 6 includes a bottom portion 61 , a top portion 62 opposite to the bottom portion 61 , and two wires 63 that respectively extend from the top portion 62 and are electrically connected to two corresponding ones of the spaced apart triple-stacked portions of the circuit pattern layer 4 through wire bonding.
  • the two corresponding triple-stacked portions of the circuit pattern layer 4 are adapted to respectively serve as a positive electrode and a negative electrode. Since the configuration and the material of the LED chip 6 are not the essential features of the disclosure and are known to those skilled in the art, further details thereof are not provided herein for the sake of brevity.
  • heat dissipation and electric power transmission. of the light emitting device are carried out through different paths.
  • the heat dissipation path of the light emitting device is from the LED chip 6 or the circuit pattern layer 4 to the heat sinking substrate 2 through the electrically insulating layer 3 , while the electric power transmission path is from the LED chip 6 to the circuit pattern layer 4 . Therefore, the resistivity of the circuit pattern layer 4 will not be undesirably increased due to heat accumulated therein.
  • the light emitting device further includes at least one solder pad 64 that is formed on the circuit pattern layer 4 .
  • the LED chip 6 is electrically connected to the circuit pattern layer 4 in a flip-chip manner. More specifically, the top portion 62 of the LED chip 6 is electrically connected to the circuit pattern layer 4 through two solder pads 64 .
  • the light emitting device further includes at least one solder pad 64 that is formed on the circuit pattern layer 4 .
  • the LED chip 6 is electrically connected to the circuit pattern layer 4 in a flip-chip manner.
  • the top portion 62 of the LED chip 6 includes a first electrode 621 , a second electrode 622 that is spaced apart from the first electrode 622 , and an insulator 623 that is disposed between the first electrode 621 and the second electrode 622 .
  • the first and second electrodes 621 , 622 are respectively connected to the circuit pattern layer 4 through a respective one of the solder pads 64 .
  • heat generated by the LED chip 6 can also be efficiently dissipated by the heat sinking substrate 2 through the electrically insulating layer 3 .
  • a method of making the embodiment of the light emitting device includes the following steps.
  • the electrically insulating layer 3 is partially formed on the heat sinking substrate 2 so as to expose a portion of the heat sinking substrate 2 .
  • the heat sinking substrate 2 is formed with a plurality of heat sink fins 21 .
  • the electrically insulating layer 3 is made of, but not limited to, epoxy, and its manufactured using electro-deposition (ED) coating techniques. It is noted that the portion of the heat sinking substrate 2 formed with the electrically insulating layer 3 is a position for the LED chip 6 to be formed on.
  • the circuit pattern layer 4 is formed on the electrically insulating layer 3 . More specifically, the circuit pattern layer 4 is formed by forming the active layer 41 , after which the first electroless-plated metal layer 42 is formed on the active layer 41 . In the method, the second electroless plating metal layer 42 ′ is further formed on the first. electroless-plated metal layer 42 .
  • the active layer 41 is first formed on the electrically insulating layer 3 using screen printing techniques.
  • the electrically insulating layer 3 and the active layer 41 may be also respectively formed using digitech printing techniques, spraying techniques, transfer printing techniques, dip plating techniques, or powder coating techniques.
  • the heat sinking substrate 2 cooperated with the electrically insulating layer 3 and the active layer 41 are dipped in a chemical plating bath containing metal ions, in which the metal ions are reduced so as to form a metal nucleus on the active layer 41 and in which the metal nucleus serves as a catalytic layer so as to conduct the reduction reaction thereon. Therefore, the first electroless-plated metal layer 42 is thus deposited on the active layer 41 for a predetermined time and includes a predetermined pattern corresponding in position to the active layer 41 .
  • the second electroless-plated metal layer 42 ′ may be deposited on the first electroless-plated metal layer 42 using the same chemical plating techniques that are used in the deposition of the first electroless-plated metal layer 42 .
  • the chemical plating bath used in the deposition of the first electroless-plated metal layer 42 is a chemical plating solution containing copper sulfate, such that the first electroless-plated metal layer 42 thus deposited is made of copper.
  • the chemical plating bath used in the deposition of the second electroless-plated metal layer 42 ′ is a chemical plating solution containing silver nitrate, such that the second electroless plated metal layer 42 ′ thus deposited is made of silver. Since the chemical plating techniques are well known to those skilled in the art, further details thereof are not provided herein for the sake of brevity.
  • the first and second electroless-plated metal layers 42 , 42 ′ may be deposited using sputtering techniques, another dip plating technique different from the electroless plating techniques, or evaporation techniques.
  • the formation of the circuit pattern layer 4 may be conducted. by one of two processes.
  • One of the processes includes: forming the active layer 4 with a predetermined pattern on the electrically insulating layer 3 ; and forming on the patterned active layer 41 the first electroless-plated metal layer 42 that has a pattern corresponding in position to the pattern of the active layer 41 so as to cooperate with the pattern of the active layer 41 to form the circuit. pattern layer 4 .
  • the other one of the processes includes: forming an active layer on the electrically insulating layer 3 ; forming the electroless-plated metal layer on a non-patterned active layer; and removing a portion of the electroless-plated metal layer and a portion of the active layer from a top surface of the electroless-plated metal layer to the active layer using laser techniques or other suitable techniques, so that the heat sinking substrate 2 corresponding in position to the etched portion of the electroless-plated metal layer and the active layer is exposed and the circuit pattern layer 4 is thus formed.
  • the electrically insulating and thermally conductive interlayer 5 is formed on the top surface 22 of the heat sinking substrate 2 that is exposed from the circuit pattern layer 4 .
  • the LED chip 6 is electrically connected to the circuit pattern layer 4 and is indirectly and non-electrically mounted to the portion of the heat sinking substrate 2 that is exposed from the electrically insulating layer 3 and the circuit pattern layer 4 . More specifically, the LED chip 6 is mounted to the heat sinking substrate 2 through the interlayer In other words, the interlayer 5 is interposed between the portion of the heat sinking substrate 2 and the LED chip 6 .
  • the LED chip 6 is connected to the circuit. pattern layer 4 by a wire bonding process. Since the wire bonding process is well known to those skilled in the art, further details thereof are not provided herein for the sake of brevity.
  • the formation of the interlayer 5 may be alternatively omitted in a method of making another configuration of the light emitting device, and the LED chip 6 is electrically connected to the circuit pattern layer 4 in the flip-chip manner.
  • solder pads 64 are formed on the circuit pattern layer 4 , and then the LED chip 6 is electrically connected to the circuit pattern layer 4 through the solder pads 64 by a flip-chip mounting process. Since the flip-chip mounting bonding process is well known to those skilled in the art, further details thereof are not provided herein for the sake of brevity.
  • the heat can be effectively conducted and dissipated away from the LED chip 6 .
  • the interlayer 5 cooperated with the heat sinking substrate 2 , a heat dissipation path different from the electric conduction path is provided.
  • stability, luminous efficiency and lifetime of the light emitting device can be improved.
  • the method of making the light emitting device is relatively uncomplicated.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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US15/392,860 2015-12-31 2016-12-28 Light emitting device and a method of making the same Abandoned US20170194544A1 (en)

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TW104144659A TWI580084B (zh) 2015-12-31 2015-12-31 發光組件及其製作方法
TW104144659 2015-12-31

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110133236A1 (en) * 2009-12-03 2011-06-09 Takahiko Nozaki Semiconductor light emitting device
US20120125577A1 (en) * 2010-11-24 2012-05-24 Industrial Technology Research Institute Heat sinking element and method of treating a heat sinking element
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