US20160372490A1 - Array substrate and manufacturing method thereof, and display panel - Google Patents

Array substrate and manufacturing method thereof, and display panel Download PDF

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US20160372490A1
US20160372490A1 US14/907,635 US201514907635A US2016372490A1 US 20160372490 A1 US20160372490 A1 US 20160372490A1 US 201514907635 A US201514907635 A US 201514907635A US 2016372490 A1 US2016372490 A1 US 2016372490A1
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layer
conducting
array substrate
conductive layer
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Jie Zhang
Fuqiang Li
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Ordos Yuansheng Optoelectronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a manufacturing method thereof, and a display panel.
  • a flat-panel display device has become a current mainstream display product due to factors such as light weight, thinness, low radiation and so on.
  • a narrow-frame display panel has a beautiful appearance and is conducive to obtain a large-sized spliced display product, and therefore a narrow-frame design of the display panel has become a major trend in development of the display field.
  • a narrow frame of the display panel is mainly implemented by manners of: firstly, reducing line width and line spacing of signal lines in a non-display region of the display panel; secondly, reducing a number of elements or sizes of the elements in a gate driving circuit, so as to compress a space occupied by the gate driving circuit.
  • the first manner since its implementation is limited by certain aspects such as alignment error, mura defect and process stability and so on, it is difficult to significantly save space occupied by the signal lines in the non-display region of the display panel; and in the second manner, in order to reduce the number of elements or the sizes of elements in the gate driving circuit, it is necessary to consider signal stability and antistatic capacity, so it is difficult to improve the gate driving circuit.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display panel, which can realize a narrow-frame display panel and be easily implemented, thereby reducing difficulty in fabricating the narrow-frame display panel.
  • an embodiment of the present disclosure provides an array substrate, comprising: a base substrate, including a display region and a non-display region; and a metal conductive layer, an insulating layer located above the metal conductive layer and an auxiliary conductive layer located above the insulating layer, formed on the base substrate, sequentially, wherein the metal conductive layer includes a plurality of first conducting lines, and the auxiliary conductive layer includes a plurality of second conducting lines, each of the plurality of first conducting lines corresponds to at least one of the plurality of second conducting lines, each of the plurality of second conducting lines is electrically connected with a corresponding first conducting line through a connecting structure in the insulating layer, and a vertical projection of the connecting structure is located in the non-display region.
  • an embodiment of the present disclosure provides a display panel, comprising: an array substrate provided as above; and an opposed substrate, cell-assembled with the array substrate.
  • an embodiment of the present disclosure provides a manufacturing method of an array substrate, comprising: preparing a base substrate, wherein the base substrate includes a display region and a non-display region; forming a metal conductive layer on the base substrate, the metal conductive layer including a plurality of first conducting lines; forming an insulating layer above the metal conductive layer, a plurality of connecting structures being formed in the insulating layer, and vertical projections of the connecting structures being located in the non-display region; and forming an auxiliary conductive layer above the insulating layer, the auxiliary conductive layer comprising a plurality of second conducting lines, and the second conducting line being electrically connected with the corresponding first conducting line through the connecting structure.
  • FIG. 1 is a structural schematic diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a structural schematic diagram of an insulating layer provided by an embodiment of the disclosure.
  • FIG. 3 is a structural schematic diagram of a first array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a structural schematic diagram of a second array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a structural schematic diagram of a third array substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides an array substrate, comprising: a base substrate 1 , including a display region and a non-display region; and a metal conductive layer, an insulating layer 3 located above the metal conductive layer and an auxiliary conductive layer located above the insulating layer 3 , which are formed on the base substrate 1 , sequentially;
  • the metal conductive layer includes a plurality of first conducting lines 2
  • the auxiliary conductive layer includes a plurality of second conducting lines 4 , each of the plurality of first conducting lines 2 corresponding to at least one of the plurality of second conducting lines 4 ;
  • the second conducting line 4 is electrically connected with the corresponding first conducting line 2 through a connecting structure 5 in the insulating layer 3 , and a vertical projection of the connecting structure 5 is located in the non-display region.
  • the vertical projection refers to a projection in a thickness direction of the array substrate.
  • each of the first conducting lines 2 may at least include a portion located in the non-display region, and further, the first conducting line 2 may further include a portion located in the display region, and the second conducting line 4 is electrically connected with the corresponding first conducting line 2 through the connecting structure 5 in the insulating layer 3 , which may be that the second conducting line 4 is electrically connected with the portion of the corresponding first conducting line 2 located in the non-display region.
  • the first conducting line 2 of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conducting line 4 electrically connected therewith, and thus, original wiring of the first conducting line 2 in the non-display region may be moved to the auxiliary conductive layer, so as to reduce an area or a width of the non-display region; when the array substrate is applied to a display panel, difficulty in realizing a narrow-frame display panel may be reduced.
  • the connecting structure 5 in FIG. 1 may be a via hole 51 , and the second conducting line 4 is electrically connected with a corresponding first conducting line 2 through the via hole 51 ; and/or, the connecting structure 5 may be a notch, and the second conducting line 4 covers a corresponding first conducting line 2 at the notch 52 .
  • FIG. 2 shows a structural schematic diagram of an insulating layer 3 , and the insulating layer 3 includes the via hole 51 and the notch 52 , and of course, may only include one of the via hole 51 and the notch 52 .
  • a Thin Film Transistor is usually formed on the array substrate, the thin film transistor includes a source-drain metal layer and a gate metal layer, and both the source-drain metal layer and the gate metal layer include a large number of signal lines or elements (e.g. a source electrode, a drain electrode and a gate electrode of the thin film transistor).
  • the source-drain metal layer may include a source electrode, a drain electrode, a data line and a power signal line and so on
  • the gate metal layer may include a gate electrode, a gate line and a common electrode line and so on.
  • the metal conductive layer is not limited to a single metal layer, and according to structure or design requirements of different array substrates, the metal conductive layer may be a single metal layer or a combination of a plurality of metal layers; when the metal conductive layer is a combination of a plurality of metal layers, the plurality of metal layers are insulated from each other; for example, the metal conductive layer may be the source-drain metal layer, and the first conducting line 2 may be at least one type of data lines, power signal lines and grounding lines; alternatively, the metal conductive layer may be the gate metal layer, and the first conducting line 2 may be at least one type of gate lines and common electrode lines; alternatively, the metal conductive layer may be a combination of the source-drain metal layer and the gate metal layer, and a gate insulating layer may be arranged between the source-drain metal layer and the gate metal layer for realizing insulation, the first conducting line 2 may be at least one type of a plurality types of lines included in the source-drain metal layer and/or the
  • a wiring space occupied by the first conducting line 2 in the non-display region of the source-drain metal layer and/or the gate metal layer may be reduced; and meanwhile, since the second conducting line 4 is used as an extending line of the first conducting line 2 , antistatic capacity of the first conducting line 2 can be enhanced.
  • the insulating layer 3 located above the metal conductive layer may be a passivation layer, a planarization layer or a combination of the passivation layer and the planarization layer;
  • the passivation layer may be any one of a silicon oxide film layer and a silicon nitride film layer or a composite film layer thereof, and the planarization layer may be a polymethyl methacrylate film layer.
  • a case in that the insulating layer 3 is located above the metal conductive layer refers to that the insulating layer 3 may be formed on the metal conductive layer and contact the metal conductive layer, or refers to that any other layer may be arranged between the insulating layer 3 and the metal conductive layer; a case in that the auxiliary conductive layer is located above the insulating layer 3 refers to that the auxiliary conductive layer may be formed on the insulating layer 3 and contact the insulating layer 3 , or refers to that any other layer may be arranged between the auxiliary conductive layer and the insulating layer 3 .
  • the TFT on the array substrate is of a bottom gate type, if the metal conductive layer only includes the gate metal layer, and the insulating layer 3 is a passivation layer, then a gate insulating layer, an active layer and a source-drain metal layer may be arranged between the gate metal layer and the passivation layer, sequentially; for example, the TFT on the array substrate is of a bottom gate type, if the metal conductive layer only includes the source-drain metal layer, the insulating layer 3 is a passivation layer, and the passivation layer is usually formed on the source-drain metal layer, then the insulating layer 3 is formed on the metal conductive layer and contacts it; for example, the TFT on the array substrate is of a top gate type, if the metal conductive layer only includes the gate metal layer, the insulating layer 3 is a passivation layer, and the passivation layer is usually formed on the gate metal layer, then the insulating layer 3 is formed on the metal conductive layer and contacts it; for example, the
  • FIG. 3 there is shown a structural schematic diagram of a first array substrate; the array substrate includes a TFT 6 , and the TFT 6 includes a gate electrode 61 , a source electrode 62 , a drain electrode 63 and an active layer 64 , wherein, a layer where the source electrode 62 and the drain electrode layer 63 are located is a source-drain metal layer, a layer where the gate electrode 61 is located is a gate metal layer, and a gate insulating layer 7 is arranged between the source-drain metal layer and the gate metal layer.
  • the first conducting line 2 is only arranged in the source-drain metal layer, i.e., the first conducting line 2 and the source electrode 62 as well as the drain electrode 63 are arranged in a same layer, and the first conducting line 2 may be at least one type of data lines, power signal lines, grounding lines, clock signal lines and common electrode lines.
  • Each of the plurality of the first conducting lines 2 is electrically connected with the corresponding second conducting line 4 through a via hole 51 or a notch 52 .
  • a case that the first conducting line 2 is only arranged in the gate metal layer has a structure similar to that of FIG. 3 , which will not be repeated here. It should be noted that, the structure of the TFT 6 is not limited to the bottom gate type shown in FIG.
  • the second conducting line 4 may be made of transparent conductive material, e.g., indium tin oxide (ITO), so as not to affect a pixel aperture ratio of the array substrate.
  • ITO indium tin oxide
  • the array substrate includes a TFT 6
  • the TFT 6 includes a gate electrode 61 , a source electrode 62 , a drain electrode 63 and an active layer 64 , wherein, a layer where the source electrode 62 and the drain electrode layer 63 are located is the source-drain metal layer, a layer where the gate electrode 61 is located is the gate metal layer, and a gate insulating layer 7 is arranged between the source-drain metal layer and the gate metal layer.
  • the first conducting lines 2 are arranged in the source-drain metal layer and the gate metal layer, i.e., a part of the first conducting lines 2 and the source electrode 62 as well as the drain electrode 63 are arranged in a same layer, a part of the first conducting lines 2 and the gate electrode 61 are arranged in a same layer, and the second conducting line 4 may be at least one type of a data line, a power signal line,a grounding line, a clock signal line and a common electrode line.
  • Each of the first conducting lines 2 is electrically connected with the corresponding second conducting line 4 through the via hole 51 or the notch 52 . It should be noted that, the structure of the TFT 6 is not limited to the bottom gate type shown in FIG.
  • the second conducting line 4 may further be a top gate type or any other structure, and a TFT of the top gate type or the other structure are also applicable to the embodiment.
  • the second conducting line 4 may be made of transparent conductive material, e.g., indium tin oxide (ITO), at a place where the second conducting line 4 is electrically connected with the first conducting line 2 , the second conducting line 4 covers and protects the first conducting line 2 , which can have waterproof protection and anti-oxidation protection for the first conducting line 2 located at the electrically connecting place.
  • ITO indium tin oxide
  • the insulating layer 3 in the array substrate shown in FIG. 3 and FIG. 4 may only be a passivation layer, or may only be a planarization layer, and of course, may also be a combination of a passivation layer and a planarization layer.
  • FIG. 5 there is shown a structural schematic diagram of a third array substrate, the array substrate shown in FIG. 5 and the array substrate shown in FIG. 4 have a similar structure, except that the insulating layer 3 of the array substrate shown in FIG. 5 includes a planarization layer 31 and a passivation layer 32 ; of course, a stacking sequence of the planarization layer 31 and the passivation layer 32 may be reversed.
  • the second conducting line 4 may be designed as a hollowed-out structure, and a pattern of the hollowed-out structure may be flexibly set, for example, the second conducting line 4 may be formed with square or circular holes or cut parts.
  • An embodiment of the present disclosure further provides a display panel, comprising the array substrate provided by the above embodiment.
  • the embodiment of the present disclosure has advantageous effects as follows: the first conducting line of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conducting line electrically connected therewith, and thus, original wiring of the first conducting line in the non-display region may be moved to the auxiliary conductive layer, so as to reduce wiring space occupied by the first conducting line in the non-display region of the metal conductive layer, further to reduce an area or a width of the non-display region, which is conducive to realizing a narrow-frame display panel; meanwhile, since it is not necessary to adjust a line width or a line spacing in the non-display region, and it is not necessary to modify the gate driving circuit, either, the narrow-frame display panel is easily realized and has low cost.
  • An embodiment of the present disclosure provides a display device, comprising the display panel provided by the above embodiment.
  • the embodiment of the present disclosure has advantageous effects as follows: the first conducting line of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conducting line electrically connected therewith, and thus, original wiring of the first conducting line in the non-display region may be moved to the auxiliary conductive layer, so as to reduce wiring space occupied by the first conducting line in the non-display region of the metal conductive layer, further to reduce an area or a width of the non-display region, which is conducive to realizing a narrow-frame display panel; meanwhile, since it is not necessary to adjust a line width or a line spacing in the non-display region, and it is not necessary to modify the gate driving circuit, either, the narrow-frame display panel is easily realized and has low cost.
  • an embodiment of the present disclosure further provides a manufacturing method of an array substrate, comprising steps of:
  • Step 601 preparing a base substrate, wherein the base substrate includes a display region and a non-display region;
  • Step 602 forming a metal conductive layer on the base substrate, the metal conductive layer including a plurality of first conducting lines.
  • the metal conductive layer may include any one of a gate metal layer and a source-drain metal layer or a combination of a gate metal layer and a source-drain metal layer.
  • the metal conductive layer includes a combination of a gate metal layer and a source-drain metal layer, an insulating layer should be arranged between the gate metal layer and the source-drain metal layer.
  • the first conducting lines may be formed only in the gate metal layer, or may be only formed in the source-drain metal layer, or may be formed in the gate metal layer and the source-drain metal layer.
  • Step 603 forming an insulating layer above the metal conductive layer, a plurality of connecting structures being formed in the insulating layer, and vertical projections of the connecting structures being located in the non-display region.
  • Step 604 forming an auxiliary conductive layer above the insulating layer, the auxiliary conductive layer including a plurality of second conducting lines, and the second conducting line being electrically connected with the corresponding first conducting line through the connecting structure.
  • a case in that the insulating layer 3 is located above the metal conductive layer refers to that the insulating layer 3 may be formed on the metal conductive layer and contact the metal conductive layer, or refers to that any other layer may be arranged between the insulating layer 3 and the metal conductive layer; a case in that the auxiliary conductive layer is located above the insulating layer 3 refers to that the auxiliary conductive layer may be formed on the insulating layer 3 and contact the insulating layer 3 , or refers to that any other layer may be arranged between the auxiliary conductive layer and the insulating layer 3 . Therefore, according to different structures or hierarchical structures of the TFT on the array substrate, based on the fabricating method provided by the embodiment, some modifications may be made, which are still within the scope of the embodiments of the present disclosure, and will not be repeated here.
  • the embodiment of the present disclosure has advantageous effects as follows: the first conducting line of the metal conductive layer of the array substrate extends to the auxiliary conductive layer through the second conducting line electrically connected therewith, and thus, original wiring of the first conducting line in the non-display region may be moved to the auxiliary conductive layer, so as to reduce wiring space occupied by the first conducting line in the non-display region of the metal conductive layer, further to reduce an area or a width of the non-display region, which is conducive to realizing a narrow-frame display panel; meanwhile, since it is not necessary to adjust a line width or a line spacing in the non-display region, and it is not necessary to modify the gate driving circuit, either, the narrow-frame display panel is easily realized and has low cost.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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CN109065549A (zh) * 2018-07-25 2018-12-21 深圳市华星光电技术有限公司 阵列基板及其制作方法、显示面板
US10177172B2 (en) * 2016-05-27 2019-01-08 Xiamen Tianma Micro-Electronics Co., Ltd. Array substrate, display panel and display device including the same
US20200341344A1 (en) * 2019-04-23 2020-10-29 E Ink Holdings Inc. Reflective active device array substrate and manufacturing method thereof and reflective display apparatus and manufacturing method thereof
US11301000B2 (en) 2018-12-04 2022-04-12 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Flexible display panel

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CN104795043B (zh) * 2015-05-11 2018-01-16 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及显示装置
CN108630144A (zh) * 2018-06-19 2018-10-09 武汉天马微电子有限公司 显示面板和显示装置
CN109448555B (zh) * 2018-12-04 2020-11-06 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及其制备方法
CN111856832B (zh) * 2019-04-23 2024-09-10 元太科技工业股份有限公司 反射式主动元件阵列基板及其制作方法与反射式显示设备
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CN111308813B (zh) * 2020-03-03 2022-04-26 Tcl华星光电技术有限公司 一种显示面板
CN116246547A (zh) * 2020-12-02 2023-06-09 湖北长江新型显示产业创新中心有限公司 显示面板和显示装置
CN114063835B (zh) * 2021-11-24 2023-10-03 昆山国显光电有限公司 触控显示面板
CN115394212B (zh) * 2022-08-29 2023-07-25 武汉华星光电半导体显示技术有限公司 显示面板及拼接显示屏

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US10593706B2 (en) * 2016-09-30 2020-03-17 Boe Technology Group Co., Ltd. Array substrate assembly, method of manufacturing array substrate assembly, display panel and display apparatus
CN109065549A (zh) * 2018-07-25 2018-12-21 深圳市华星光电技术有限公司 阵列基板及其制作方法、显示面板
US11301000B2 (en) 2018-12-04 2022-04-12 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Flexible display panel
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