US20150318868A1 - Data processing apparatus and data processing method - Google Patents

Data processing apparatus and data processing method Download PDF

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US20150318868A1
US20150318868A1 US14/412,718 US201414412718A US2015318868A1 US 20150318868 A1 US20150318868 A1 US 20150318868A1 US 201414412718 A US201414412718 A US 201414412718A US 2015318868 A1 US2015318868 A1 US 2015318868A1
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column
parity check
code
check matrix
bit
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Yuji Shinohara
Makiko YAMAMOTO
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Saturn Licensing LLC
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present technology relates to a data processing apparatus and a data processing method, and in particular, relates to a data processing apparatus and a data processing method which are able to secure good communication quality in data transmission using, for example, an LDPC code.
  • a low density parity check (LDPC) code has a high error correction ability, and has been widely adopted in a transmission scheme including digital broadcasting such as, for example, European digital video broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 in recent years (for example, see NPL 1).
  • digital broadcasting such as, for example, European digital video broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 in recent years (for example, see NPL 1).
  • the LDPC code has a performance close to the Shannon limit, similar to turbo codes or the like, with an increase in a code length.
  • the LDPC code since the LDPC code has properties of a minimum distance being proportional to the code length, the LDPC code has an advantage in which a block error probability characteristic is good and a so-called error floor phenomenon observed as a decoding property of the turbo code or the like hardly occurs, as properties.
  • the LDPC code is formed into a symbol of quadrature modulation (digital modulation) such as quadrature phase shift keying (QPSK) (is symbolized), and the symbol is transmitted by being mapped to the signal point of quadrature modulation.
  • quadrature modulation digital modulation
  • QPSK quadrature phase shift keying
  • the present technology has been made in view of such circumstances, and an object is to secure good communication quality in data transmission using an LDPC code.
  • a first data processing apparatus/a data processing method of the present technology includes a coding unit/step that encodes an information bit into an LDPC code having a code length of 16200 bits and a code rate of 12/15, based on a parity check matrix of a low density parity check (LDPC) code, in which the LDPC code includes an information bit and a parity bit, the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit, the information matrix portion is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • LDPC low density parity check
  • an information bit is encoded into an LDPC code having a code length of 16200 bits and a code rate of 12/15, based on a parity check matrix of a low density parity check (LDPC) code.
  • the LDPC code includes an information bit and a parity bit
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • a second data processing apparatus/data processing method of the present technology includes a decoding unit/step that decodes an LDPC code which is obtained from data transmitted from a transmission apparatus including a coding unit that encodes an information bit into an LDPC code having a code length of 16200 bits and a code rate of 12/15, based on a parity check matrix of a low density parity check (LDPC) code, in which the LDPC code includes an information bit and a parity bit, the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit, the information matrix portion is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • LDPC low density parity check
  • an LDPC code which is obtained from data transmitted from a transmission apparatus is decoded, in which the transmission apparatus includes a coding unit/step that encodes an information bit into an LDPC code having a code length of 16200 bits and a code rate of 12/15, based on a parity check matrix of a low density parity check (LDPC) code, in which the LDPC code includes an information bit and a parity bit, the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit, the information matrix portion is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • a third data processing apparatus of the present technology includes a decoding unit that decodes an LDPC code having a code length of 16200 bits and a code rate of 12/15, based on a parity check matrix of a low density parity check (LDPC) code, in which the LDPC code includes an information bit and a parity bit, the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit, the information matrix portion is represented by a parity check matrix initial value table, the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • LDPC low density parity check
  • an LDPC code having a code length of 16200 bits and a code rate of 12/15 is decoded, based on a parity check matrix of a low density parity check (LDPC) code.
  • the LDPC code includes an information bit and a parity bit
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit
  • the information matrix portion is represented by a parity check matrix initial value table
  • the parity check matrix initial value table is a table representing positions of elements of 1 in the information matrix portion at an interval of 360 columns, and is
  • the data processing apparatus may be an independent apparatus or may be an internal block configuring one apparatus.
  • FIG. 1 is a diagram describing a parity check matrix H of an LDPC code.
  • FIG. 2 is a flowchart illustrating a decoding procedure of the LDPC code.
  • FIG. 3 is a diagram illustrating an example of a parity check matrix of the LDPC code.
  • FIG. 4 is a diagram illustrating a Tanner graph of the parity check matrix.
  • FIG. 5 is a diagram illustrating a variable node.
  • FIG. 6 is a diagram illustrating a check node.
  • FIG. 7 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied.
  • FIG. 8 is a diagram illustrating a configuration example of a transmission apparatus 11 .
  • FIG. 9 is a block diagram illustrating a configuration example of a bit interleaver 116 .
  • FIG. 10 is a diagram illustrating a parity check matrix.
  • FIG. 11 is a diagram illustrating a parity matrix.
  • FIG. 12 is a diagram illustrating a parity check matrix of the LDPC code which is defined in the DVB-S.2 standard.
  • FIG. 13 is a diagram describing the parity check matrix of the LDPC code which is defined in the DVB-S.2 standard.
  • FIG. 14 is a diagram illustrating a signal point arrangement of 16QAM.
  • FIG. 15 is a diagram illustrating a signal point arrangement of 64QAM.
  • FIG. 16 is a diagram illustrating a signal point arrangement of 64QAM.
  • FIG. 17 is a diagram illustrating a signal point arrangement of 64QAM.
  • FIG. 18 is a diagram illustrating a signal point arrangement which is defined in the DVB-S.2 standard.
  • FIG. 19 is a diagram illustrating a signal point arrangement which is defined in the DVB-S.2 standard.
  • FIG. 20 is a diagram illustrating a signal point arrangement which is defined in the DVB-S.2 standard.
  • FIG. 21 is a diagram illustrating a signal point arrangement which is defined in the DVB-S.2 standard.
  • FIG. 22 is a diagram describing a process of a demultiplexer 25 .
  • FIG. 23 is a diagram describing a process of the demultiplexer 25 .
  • FIG. 24 is a diagram illustrating a Tanner graph for decoding of the LDPC code.
  • FIG. 25 is a diagram illustrating a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T .
  • FIG. 26 is a diagram illustrating a parity matrix H T of a parity check matrix H corresponding to an LDPC code after parity interleave.
  • FIG. 27 is a diagram illustrating a conversion parity check matrix.
  • FIG. 28 is a diagram describing a process of a column twist interleaver 24 .
  • FIG. 29 is a diagram illustrating the number of columns and an address of a write start position of a memory 31 required for column twist interleave.
  • FIG. 30 is a diagram illustrating the number of columns and an address of a write start position of the memory 31 required for column twist interleave.
  • FIG. 31 is a flowchart illustrating a process performed in a bit interleaver 116 and a mapper 117 .
  • FIG. 32 is a diagram illustrating a communication path model employed in a simulation.
  • FIG. 33 is a diagram illustrating a relationship between an error rate obtained by the simulation and a Doppler frequency f d of a flutter.
  • FIG. 34 is a diagram illustrating a relationship between an error rate obtained by the simulation and a Doppler frequency f d of a flutter.
  • FIG. 35 is a block diagram illustrating a configuration example of an LDPC encoder 115 .
  • FIG. 36 is a flowchart illustrating a process of the LDPC encoder 115 .
  • FIG. 37 is a diagram illustrating an example of a parity check matrix initial value table in which a code rate is 1/4 and a code length is 16200.
  • FIG. 38 is a diagram describing a method of obtaining a parity check matrix H from the parity check matrix initial value table.
  • FIG. 40 is a diagram illustrating an example of a Tanner graph of ensemble of a degree sequence in which a column weight is 3 and a row weight is 6.
  • FIG. 41 is a diagram illustrating an example of a Tanner graph of a multi-edge type ensemble.
  • FIG. 45 is a diagram illustrating a simulation result of simulation of measuring BER/FER.
  • FIG. 46 is a block diagram illustrating a configuration example of a reception apparatus 12 .
  • FIG. 47 is a block diagram illustrating a configuration example of a bit deinterleaver 165 .
  • FIG. 48 is a flowchart illustrating a process performed by a demapper 164 , the bit deinterleaver 165 , and an LDPC decoder 166 .
  • FIG. 49 is a diagram illustrating an example of a parity check matrix of an LDPC code.
  • FIG. 50 is a diagram illustrating a matrix (conversion parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix.
  • FIG. 51 is a diagram illustrating a conversion parity check matrix which is divided into 5 ⁇ 5 units.
  • FIG. 52 is a block diagram illustrating a configuration example of a decoding device that performs node calculation in groups of P.
  • FIG. 53 is a block diagram illustrating a configuration example of the LDPC decoder 166 .
  • FIG. 54 is a diagram describing a process of a multiplexer 54 configuring the bit deinterleaver 165 .
  • FIG. 55 is a diagram describing a process of a column twist deinterleaver 55 .
  • FIG. 56 is a block diagram illustrating another configuration example of the bit deinterleaver 165 .
  • FIG. 57 is a block diagram illustrating a first configuration example of a reception system to which the reception apparatus 12 is applicable.
  • FIG. 58 is a block diagram illustrating a second configuration example of a reception system to which the reception apparatus 12 is applicable.
  • FIG. 59 is a block diagram illustrating a third configuration example of a reception system to which the reception apparatus 12 is applicable.
  • FIG. 60 is a block diagram illustrating a configuration example of an embodiment of a computer to which the present technology is applied.
  • the LDPC code is a linear code, and does not need to be binary, but here, a description will be given assuming that the LDPC code is binary.
  • a parity check matrix defining the LDPC code is a sparse matrix.
  • the sparse matrix is a matrix in which the number of “1” elements of the matrix is very small (most elements in the matrix are 0).
  • FIG. 1 is a diagram illustrating a parity check matrix H of the LDPC code.
  • a weight of each column (a column weight) (the number of “1”) (a weight) is set to “3”, and a weight of each row (a row weight) is set to “6”.
  • a generation matrix G is generated based on the parity check matrix H, and a codeword (LDPC code) is generated by multiplying the generation matrix G with a binary information bit.
  • the generation matrix G is a K ⁇ N matrix
  • the codeword (LDPC code) generated by the coding device is received on the receiving side through a predetermined communication path.
  • the decoding of the LDPC code is an algorithm that is proposed and referred to as probabilistic decoding by Gallager, and the algorithm may be performed by a message passing algorithm by belief propagation on a so-called Tanner graph which is configured with a variable node (also referred to as a message node) and a check node.
  • a variable node also referred to as a message node
  • a check node a check node
  • FIG. 2 is a flowchart illustrating a decoding procedure of the LDPC code.
  • a real number which is obtained by representing the “0” likelihood of a value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio, is referred to as a received value u 0i .
  • the message output from the check node is assumed to be u j
  • the message output from the variable node is assumed to be v i .
  • step S 11 the LDPC code is received, the message (check node message) u j is initialized to “0”, a variable k which is an integer as a counter of an iterative process is initialized to “0”, and the process proceeds to step S 12 .
  • step S 12 the message (variable node message) v i is obtained by performing the calculation (variable node calculation) shown in Equation (1) based on the received value u 0i obtained by receiving the LDPC code, and the message u j is obtained by performing the calculation (check node calculation) shown in Equation (2), based on the message v i .
  • d v and d c in the equation (1) and the equation (2) are respectively parameters indicating the number of “1” in the vertical direction (column) and the horizontal direction (row) of the parity check matrix H, which can be arbitrarily selected.
  • variable node calculation of the equation (1) and the check node calculation of the equation (2) a message which is input from an edge (a line connecting the variable node and the check node) from which a message is to be output is not used as a target of calculation, and thus a calculation range is 1 to d v ⁇ 1 or 1 to d c ⁇ 1.
  • the check node calculation of the equation (2) is performed actually by previously creating a table of a function R(v 1 , v 2 ) shown in equation (3) which is defined as one output for two inputs v 1 and v 2 and continuously (recursively) using the table as shown in equation (4).
  • step S 12 the variable k is incremented by “1”, and the process proceeds to step S 13 .
  • step S 13 it is determined whether or not the variable k is greater than a predetermined iterative decoding number C. In step S 13 , if the variable k is determined not to be greater than C, the process returns to step S 12 , and the same process is repeated.
  • step S 13 if the variable k is determined to be greater than C, the process proceeds to step S 14 , a message v i as a decoding result to be finally output is obtained and output by performing the calculation shown in the equation (5), and the decoding process of the LDPC code is ended.
  • the calculation of the equation (5) is different from the variable node calculation of the equation (1), and is performed by using the message u j from all edges coupled to the variable node.
  • FIG. 3 is a diagram illustrating an example of a parity check matrix H of (3, 6) LDPC code (code rate of 1/2, code length of 12).
  • a column weight is set to 3 and a row weight is set to 6, similarly to FIG. 1 .
  • FIG. 4 is a diagram illustrating a Tanner graph of the parity check matrix H in FIG. 3 .
  • the check nodes and the variable nodes respectively correspond to the rows and the columns of the parity check matrix H.
  • the connection lines between the check nodes and the variable nodes are edges, and the edges corresponds to “1” elements in the parity check matrix.
  • the edge represents that the code bit corresponding to the variable node has constraints corresponding to the check node.
  • variable node calculation and the check node calculation are repeatedly performed.
  • FIG. 5 is a diagram illustrating a variable node calculation performed at a variable node.
  • a message v i corresponding to an edge to be calculated is obtained by the variable node calculation of equation (1) using messages u 1 and u 2 from the remaining edges which are connected to the variable node and a received value u 0i .
  • the messages corresponding to other edges are obtained in the same manner.
  • FIG. 6 is a diagram illustrating a check node calculation performed at the check node.
  • a ⁇ b exp ⁇ ln(
  • sign(x) is 1 when x ⁇ 0
  • sign(x) is ⁇ 1 when x ⁇ 0.
  • the check node calculation of the equation (2) is performed according to the equation (7).
  • a message U j corresponding to an edge to be calculated is obtained by the check node calculation of the equation (7) using messages v 1 , v 2 , v 3 , v 4 , and v 5 from the remaining edges which are connected to the check node.
  • the messages corresponding to other edges are obtained in the same manner.
  • the functions ⁇ (x) and ⁇ ⁇ 1 (x) are implemented in hardware, the functions may be implemented by using look up tables (LUTs) in some cases, but the LUTs are the same.
  • FIG. 7 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied (the system refers to those in which a plurality of devices are assembled logically, and it does not matter whether the constituent devices are in the same housing).
  • the transmission system includes a transmission apparatus 11 and a reception apparatus 12 .
  • the transmission apparatus 11 performs transmission (broadcasting) (sending) of, for example, programs and the like of television broadcasting.
  • the transmission apparatus 11 encodes, for example, target data which is a target of transmission such as image data and audio data as a program into an LDPC code, and transmits the encoded target data through a communication path 13 such as, for example, satellite lines, terrestrial waves, cables (wired lines).
  • the reception apparatus 12 receives the LDPC code which is transmitted from the transmission apparatus 11 through the communication path 13 , decodes the LDPC code into target data, and outputs the data.
  • LDPC code used in the transmission system of FIG. 7 exerts a significantly high capacity in an Additive White Gaussian Noise (AWGN) communication path.
  • AWGN Additive White Gaussian Noise
  • the communication path 13 may generate a burst error or erasure.
  • OFDM Orthogonal Frequency Division Multiplexing
  • a burst error may occur due to the status of the wiring from a reception unit (not shown) such as an antenna which receives signals from the transmission apparatus 11 on the reception apparatus 12 to the reception apparatus 12 , and the instability of power of the reception apparatus 12 .
  • the check node if two or more of variable nodes connected to the check node are simultaneously erased, the check node returns a message in which a probability of having a value 0 and a probability of having a value 1 are the same in all variable nodes.
  • the check node that returns the message of the equal probability does not contribute to one decoding process (one set of variable node calculation and check node calculation), as a result, a lot number of iterations of the decoding process is required, the decoding performance is deteriorated, and the power consumption of the reception apparatus 12 that decodes the LDPC code increases.
  • the transmission system of FIG. 7 enables improvement in resistance to the burst error and erasure while maintaining the performance at the AWGN communication path (AWGN channel).
  • FIG. 8 is a block diagram illustrating a configuration example of the transmission apparatus 11 in FIG. 7 .
  • input streams of one or more as target data are supplied to a mode adaptation/multiplexer 111 .
  • the mode adaptation/multiplexer 111 performs a process such as mode selection and multiplexing of one or more input streams supplied thereto, as necessary, and supplies the resulting data to a padder 112 .
  • the padder 112 performs necessary zero padding (null insertion) on the data from the mode adaptation/multiplexer 111 , and supplies the resulting data to a BB scrambler 113 .
  • the BB scrambler 113 performs Base-Band Scrambling (BB scrambling) on the data from the padder 112 , and supplies the resulting data to a BCH encoder 114 .
  • the BCH encoder 114 performs BCH coding on the data from the BB scrambler 113 , and supplies the resulting data as the LDPC target data which is the target of LDPC coding, to an LDPC encoder 115 .
  • the LDPC encoder 115 performs LDPC coding according to the parity check matrix in which the parity matrix which is a portion corresponding to parity bits of the LDPC code has a staircase structure, on the LDPC target data from the BCH encoder 114 , and outputs the LDPC code with the LDPC target data as an information bit.
  • the LDPC encoder 115 performs LDPC coding which encodes the LDPC target data into an LDPC code (corresponding to the parity check matrix) which is defined in predetermined standards such as, for example, DVB-S.2, DVB-T.2, and DVB-C.2, or an LDPC code (corresponding to the parity check matrix) which is determined in advance, and outputs the resulting LDPC code.
  • LDPC code corresponding to the parity check matrix
  • the LDPC code which is defined in standards such as DVB-S.2, DVB-T.2, and DVB-C.2 is an Irregular Repeat accumulate (IRA) code
  • the parity matrix in the parity check matrix of the LDPC code has a staircase structure. The parity matrix and the stair structure will be described later.
  • the IRA code is described in, for example, “Irregular Repeat-accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, September 2000.
  • the LDPC code output from the LDPC encoder 115 is supplied to a bit interleaver 116 .
  • the bit interleaver 116 performs a bit interleave which will be described later, on the LDPC code from the LDPC encoder 115 , and supplies the LDPC code after the bit interleave to a mapper 117 .
  • the mapper 117 performs a quadrature modulation (multilevel modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of the quadrature modulation, in a unit of code bit of one bit or more of the LDPC code (symbol unit).
  • the mapper 117 performs quadrature modulation by mapping the LDPC code from the bit interleaver 116 to the signal points which are determined in a modulation scheme which performs the quadrature modulation of the LDPC code, on an IQ plane (IQ constellation) which is defined as an I axis representing an I component which is in-phase with a carrier wave and a Q axis representing a Q component which is orthogonal to the carrier wave.
  • IQ plane IQ constellation
  • an example of a modulation scheme of the quadrature modulation performed in the mapper 117 includes for example, a modulation scheme which is defined in standards such as DVB-S.2, DVB-T.2, and DVB-C.2, the other modulation schemes, in other words, for example, binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 8 phase shift keying (PSK), 16 amplitude phase-shift keying (APSK), 32 APSK, 16 quadrature amplitude modulation (QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and 4 pulse amplitude modulation (PAM).
  • BPSK binary phase shift keying
  • QPSK quadrature phase shift keying
  • PSK 8 phase shift keying
  • APSK 16 amplitude phase-shift keying
  • QAM 16 quadrature amplitude modulation
  • QAM quadrature amplitude modulation
  • 64QAM 64QAM
  • 256QAM 256QAM
  • the data which is obtained by a process in the mapper 117 (a mapping result obtained by mapping a symbol into a signal point) is supplied to a time interleaver 118 .
  • the time interleaver 118 performs time interleave (interleave in a time direction) in a unit of symbol, on the data from the mapper 117 , and supplies the resulting data to a Single Input Single Output/Multiple Input Single Output (SISO/MISO) encoder 119 .
  • SISO/MISO Single Input Single Output/Multiple Input Single Output
  • the SISO/MISO encoder 119 performs space-time coding on the data from the time interleaver 118 , and supplies the resulting data to a frequency interleaver 120 .
  • the frequency interleaver 120 performs frequency interleave (interleave in a frequency direction) in a unit of symbol, on the data from the SISO/MISO encoder 119 , and supplies the resulting data to a frame builder/resource allocation unit 131 .
  • control data for transmission control such as Base Band Signaling (BB signaling) (BB Header) is supplied to a BCH encoder 121 .
  • BB signaling Base Band Signaling
  • BB Header Base Band Signaling
  • the BCH encoder 121 similarly to the BCH encoder 114 , performs BCH coding on the control data supplied thereto, and supplies the resulting data to an LDPC encoder 122 .
  • the LDPC encoder 122 similarly to the LDPC encoder 115 , performs LDPC coding on the data from the BCH encoder 121 as the LDPC target data, and supplies the resulting LDPC code to a mapper 123 .
  • the mapper 123 similarly to the mapper 117 , performs a quadrature modulation by mapping the LDPC code from the LDPC encoder 122 to a signal point representing one symbol of the quadrature modulation, in a unit of code bit of one bit or more of the LDPC code (symbol unit), and supplies the resulting data to a frequency interleaver 124 .
  • the frequency interleaver 124 similarly to the frequency interleaver 120 , performs a frequency interleave in a symbol unit on the data from the mapper 123 , and supplies the resulting data to the frame builder/resource allocation unit 131 .
  • the frame builder/resource allocation unit 131 inserts a pilot symbol in a necessary position of data (symbol) from the frequency interleavers 120 and 124 , makes a frame formed of symbols of a predetermined number (for example, a Physical Layer (PL) frame, a T2 frame, a C2 frame, and the like) from the resulting data (symbol), and supplies the frame to an OFDM generation unit 132 .
  • a predetermined number for example, a Physical Layer (PL) frame, a T2 frame, a C2 frame, and the like
  • the OFDM generation unit 132 generates an OFDM signal corresponding to the frame, from the frame from the frame builder/resource allocation unit 131 , and transmits the OFDM signal through the communication path 13 ( FIG. 7 ).
  • the transmission apparatus 11 may be configured without providing some of the blocks shown in FIG. 8 such as, for example, the time interleaver 118 , the SISO/MISO encoder 119 , the frequency interleaver 120 , and the frequency interleaver 124 .
  • FIG. 9 illustrates a configuration example of a bit interleaver 116 in FIG. 8 .
  • the bit interleaver 116 has a function of interleaving data, and is configured with a parity interleaver 23 , a column twist interleaver 24 , and a demultiplexer (DEMUX) 25 .
  • the bit interleaver 116 may be configured without providing one or both of the parity interleaver 23 and the column twist interleaver 24 .
  • the parity interleaver 23 performs parity interleave which interleaves the parity bit of the LDPC code from the LDPC encoder 115 in the position of another parity bit, and supplies the LDPC code after the parity interleave to the column twist interleaver 24 .
  • the column twist interleaver 24 performs the column twist interleave on the LDPC code from the parity interleaver 23 , and supplies the LDPC code after the column twist interleave to the demultiplexer 25 .
  • the LDPC code is transmitted while the code bits of one bit or more of the LDPC code are mapped to a signal point representing one symbol of the quadrature modulation by the mapper 117 in FIG. 8 .
  • a column twist interleave which will be described later, is performed as a rearrangement process of rearranging the code bits of the LDPC code from the parity interleaver 23 such that a plurality of code bits of an LDPC code corresponding to any 1 in any one row of the parity check matrix used in the LDPC encoder 115 are not included in one symbol.
  • the demultiplexer 25 obtains an LDPC code having enhanced resistance to AWGN and the like by performing a replacing process of replacing the position of two or more code bits of the LDPC code which is a symbol, on the LDPC code from the column twist interleaver 24 . Then, the demultiplexer 25 supplies the two or more code bits of the LDPC code which is obtained by the replacing process, as a symbol, to the mapper 117 ( FIG. 8 ).
  • FIG. 10 is a diagram illustrating the parity check matrix H used in LDPC coding in the LDPC encoder 115 in FIG. 8 .
  • H Low-Density Generation Matrix
  • the information length K and the parity length M for the LDPC code of a certain code length N are determined by a code rate. Further, the parity check matrix H is a matrix of row ⁇ column M ⁇ N. Then, the information matrix H A is a matrix of M ⁇ K, and the parity matrix H T is a matrix of M ⁇ M.
  • FIG. 11 shows the parity matrix H T of the parity check matrix H of the LDPC code which is defined in the standard of DVB-S.2, DVB-T.2, and DVB-C.2.
  • the parity matrix H T of the parity check matrix H of the LDPC code which is defined in the standard such as DVB-T.2 is a matrix of a staircase structure in which elements of 1 are arranged in a staircase shape (lower bidiagonal matrix).
  • the row weight of the parity matrix H T is 1 in a first row, and is 2 in all remaining rows. Further, the column weight is 1 in a last column, and is 2 in all remaining columns.
  • the LDPC code (one codeword) is represented by a row vector c, and a column vector obtained by transporting the row vector is represented by c T . Further, the information bit part is represented by a row vector c, and the parity bit part is represented by a row vector T, in the row vector c which is the LDPC code.
  • the parity check matrix H and the row vector c [A
  • H T ] has the staircase structure shown in FIG. 11 , the row vector T as the parity bits configuring the row vector c [A
  • FIG. 12 is a diagram describing the parity check matrix H of the LDPC code which is defined in the standard of DVB-T.2.
  • the column weight X is given to the first column to a KX-th column, and the column weight 3 is given to the subsequent K 3 columns, the column weight 2 is given to the subsequent M ⁇ 1 columns, and the column weight 1 is given to the last column.
  • KX+K 3 +M ⁇ 1+1 is equal to the code length N.
  • FIG. 13 is a diagram illustrating the number of columns KX, K 3 , and M, and a column weight X for each code rate of the LDPC code which is defined in the standards of DVB-T.2 and the like.
  • the LDPC codes of the code length N of 64800 bits and 16200 bits are defined.
  • the code length N of 64800 bits is referred to as 64 kbits and the code length N of 16200 bits is referred to as 16 kbits.
  • the code bit corresponding to the column having a large column weight of the parity check matrix H is likely to have a low error rate.
  • the parity check matrix H which is defined in the standard of DVB-T.2 and the like shown in FIG. 12 and FIG. 13 , the closer to the first side (left side) the column is, the larger the column weight is likely to be, therefore, for the LDPC code corresponding to the parity check matrix H, the code bit on the start side is likely to be strong in error (having a resistance to error), and the code bit on the end side is likely to be weak in error.
  • FIG. 14 illustrates an arrangement example of 16 symbols (signal points corresponding thereto) on the IQ plane when 16QAM is performed by the mapper 117 in FIG. 8 .
  • a of FIG. 14 shows symbols (signal points corresponding thereto) of 16QAM of DVB-T.2.
  • 16QAM 16QAM
  • the four bits that represents one bit of 16QAM can be represented as bits y 0 , y 1 , y 2 , and y 3 from the most significant bit in order. If a modulation scheme is 16QAM, four bits of the code bits of the LDPC code become (symbolized into) a symbol (symbol values) of four bits y 0 to y 3 .
  • FIG. 14 shows bit boundaries for the symbol bit y i four bits (hereinafter, referred to as a symbol bit) y 0 to y 3 represented by symbols of 16QAM.
  • the bit boundaries are located between the first column and the second column and between the third column and the fourth column from the left, out of 4 ⁇ 4 symbols.
  • bit boundaries are located between the first row and the second row and between the third row and the fourth row from the top, out of 4 ⁇ 4 symbols.
  • strong bit a bit in which error hardly occurs (strong in error)
  • weak bit a bit in which error easily occurs (weak in error)
  • the top symbol bit y 0 and the second symbol bit y 1 are strong bits
  • the third symbol bit y 2 and the fourth symbol bit y 3 are weak bits.
  • FIG. 15 to FIG. 17 illustrate an arrangement example of 64 symbols (signal points corresponding thereto), in other words, symbols of 16QAM of DVB-T.2 on the IQ plane when 64QAM is performed by the mapper 117 in FIG. 8 .
  • the symbol bits of one symbol of 64QAM can be represented as bits y 0 , y 1 , y 2 , y 3 , y 4 , and y 5 from the most significant bit in order. If a modulation scheme is 64QAM, six bits of the code bits of the LDPC code are a symbol of symbol bits y 0 to y 5 of six bits.
  • FIG. 15 illustrates the bit boundary for each of the top symbol bit y 0 and the second symbol bit y 1
  • FIG. 16 illustrates the bit boundary for each of the third symbol bit y 2 and the fourth symbol bit y 3
  • FIG. 17 illustrates the bit boundary for each of the fifth symbol bit y 4 and the sixth symbol bit y 5 , among the symbol bits y 0 to y 5 of the symbol of 64QAM.
  • the number of bit boundaries for each of the top symbol bit y 0 and the second symbol bit y 1 is one. Further, as shown in FIG. 16 , the number of bit boundaries for each of the third symbol bit y 2 and the fourth symbol bit y 3 is two, and as shown in FIG. 17 , the number of bit boundaries for each of the fifth symbol bit y 4 and the sixth symbol bit y 5 is four.
  • the top symbol bit y 0 and second symbol bit y 1 are the strongest bits
  • the third symbol bit y 2 and the fourth symbol bit y 3 are the second strongest bits.
  • the fifth symbol bit y 4 and the sixth symbol bit y 5 are weak bits.
  • an upper bit is likely to be a strong bit and a lower bit is likely to be a weak bit, for the symbol bits of the symbol of the quadrature modulation.
  • FIG. 18 illustrates an arrangement example of four symbols (signal points corresponding thereto) on an IQ plane, in other words, for example, signal point arrangement of QPSK of DVB-S.2, when a satellite line is employed as the communication path 13 ( FIG. 7 ) and QPSK is performed by the mapper 117 in FIG. 8 .
  • the symbol is mapped to one of four signal points on the circumference of a circle having a radius p of 1 with an origin of the IQ plane as a center.
  • FIG. 19 illustrates an arrangement example of eight symbols on an IQ plane, in other words, for example, signal point arrangement of 8PSK of DVB-S.2, when a satellite line is employed as the communication path 13 ( FIG. 7 ) and 8PSK is performed by the mapper 117 in FIG. 8 .
  • the symbol is mapped to one of eight signal points on the circumference of a circle having a radius ⁇ of 1 with an origin of the IQ plane as a center.
  • FIG. 20 illustrates an arrangement example of 16 symbols on an IQ plane, in other words, for example, signal point arrangement of 16APSK of DVB-S.2, when a satellite line is employed as the communication path 13 ( FIG. 7 ) and 16APSK is performed by the mapper 117 in FIG. 8 .
  • a in FIG. 20 shows constellation of 16APSK of DVB-S.2.
  • the symbol is mapped to one of a total of 16 signal points including four signal points on the circumference of a circle having a radius R 1 and 12 signal points on the circumference of a circle having a radius R 2 (>R 1 ), with an origin of the IQ plane as a center.
  • the ratio ⁇ of the radius R 2 to the radius R 1 changes depending on the code rate, in the constellation of 16APSK of DVB-S.2.
  • FIG. 21 illustrates an arrangement example of 32 symbols on an IQ plane, in other words, for example, signal point arrangement of 32APSK of DVB-S.2, when a satellite line is employed as the communication path 13 ( FIG. 7 ) and 32APSK is performed by the mapper 117 in FIG. 8 .
  • FIG. 21 shows constellation of 32APSK of DVB-S.2.
  • the symbol is mapped to one of a total of 32 signal points including four signal points on the circumference of a circle having a radius R 1 , 12 signal points on the circumference of a circle having a radius R 2 (>R 1 ), and 16 signal points on the circumference of a circle having a radius R 3 (>R 2 ), with an origin of the IQ plane as a center.
  • the ratio ⁇ 1 of the radius R 2 to the radius R 1 and the ratio ⁇ 2 of the radius R 3 to the radius R 1 change depending on code rate, in the constellation of 32APSK of DVB-S.2.
  • the demultiplexer 25 in FIG. 9 can perform the process of the interleaver.
  • FIG. 22 is a diagram describing the process of the demultiplexer 25 in FIG. 9 .
  • a of FIG. 22 shows a functional configuration example of the demultiplexer 25 .
  • the demultiplexer 25 is configured with a memory 31 and a replacement unit 32 .
  • the LDPC code from the LDPC encoder 115 is supplied to the memory 31 .
  • the memory 31 has a storage capacity for storing mb bits in a row (horizontal) direction and N/(mb) bits in a column (vertical) direction, and supplies the replacement unit 32 with the code bit of the LDPC code supplied thereto, by writing the code bit in the column direction and reading the code bit in the row direction.
  • m represents the number of bits of code bit of the LDPC code as one symbol
  • b represents a predetermined positive integer
  • m is a multiple used for integer multiplying.
  • the demultiplexer 25 forms (symbolizes) the code bit of the LDPC code into a symbol, in a unit of the predetermined number of bits m
  • the multiple b represents the number of symbols obtained by one time of symbolizing by the demultiplexer 25 .
  • a of FIG. 22 illustrates a configuration example of the demultiplexer 25 in which a modulation scheme is 64QAM which maps a symbol to any of 64 signal points, and therefore, the number m of bits of code bit of the LDPC code which is one symbol is six bits.
  • the memory 31 has a storage capacity of N/(6 ⁇ 1) ⁇ (6 ⁇ 1) bits in the column direction x row direction.
  • a storage area of the memory 31 which has one bit in the row direction and extends in the column direction, hereinafter, as appropriate, is referred to as a column.
  • the writing of the code bit of the LDPC code in a direction from the top to the bottom of the columns (in the column direction) configuring the memory 31 is performed toward the column in the left-to-right direction.
  • the code bits are read, from the first column of all columns configuring the memory 31 , in the row direction, in a unit of six bits (mb bits) and supplied to the replacement unit 32 .
  • the replacement unit 32 performs a replacement process of replacing the positions of the code bits of six bits from the memory 31 , and outputs six resulting bits as six symbol bits y 0 , y 1 , Y 2 , y 3 , y 4 , and y 5 that represent one symbol of 64QAM.
  • the code bit located in the direction of a bit b 0 is a code bit which is strong in error
  • the code bit located in the direction of a bit b 5 is a code bit which is weak in error.
  • the replacement unit 32 can perform a replacement process of replacing the positions of the code bits b 0 to b 5 of six bits from the memory 31 such that the code bit which is weak in error among the code bits b 0 to b 5 of six bits from the memory 31 is allocated to the strong bits among the symbol bits y 0 to y 5 of one symbol of 64QAM.
  • B of FIG. 22 , C of FIG. 22 , and D of FIG. 22 respectively show a first replacement method, a second replacement method, and a third replacement method.
  • a line connecting the bit b i and y i means allocating the code bit b i to the symbol bit y i of the symbol (replacing it in the position of the symbol bit y i ).
  • FIG. 23 illustrates a configuration example of the demultiplexer 25 in which a modulation scheme is 64QAM which maps a symbol to any of 64 signal points, (therefore, the number m of bits of code bit of the LDPC code which is mapped to one symbol is six bits, similarly to FIG. 22 ), and the multiple b is 2, and the fourth replacement method.
  • a modulation scheme is 64QAM which maps a symbol to any of 64 signal points, (therefore, the number m of bits of code bit of the LDPC code which is mapped to one symbol is six bits, similarly to FIG. 22 ), and the multiple b is 2, and the fourth replacement method.
  • a of FIG. 23 illustrates a write order of the LDPC code to the memory 31 .
  • the writing of the code bit of the LDPC code in a direction from the top to the bottom of the columns (in the column direction) configuring the memory 31 is performed toward the column in the left-to-right direction.
  • the code bits are read, from the first column of all columns configuring the memory 31 , in the row direction, in a unit of 12 bits (mb bits) and supplied to the replacement unit 32 .
  • the replacement unit 32 performs a replacement process of replacing the positions of the code bits of 12 bits from the memory 31 by using the fourth replacement method, and outputs 12 resulting bits as 12 bits representing two symbols (b symbols) of 64QAM, in other words, six symbol bits y 0 , y 1 , y 2 , y 3 , y 4 , and y 5 that represent one symbol of 64QAM, and six symbol bits y 0 , y 1 , y 2 , y 3 , y 4 , and y 5 that represent one next symbol.
  • B of FIG. 23 illustrates the fourth replacement method of the replacement process by the replacement unit 32 of A of FIG. 23 .
  • the code bits of mb bits are allocated to the symbol bits of mb bits of b successive symbols.
  • the (i+1)-th bit from the most significant bit of the symbol bit of mb bits of b successive symbols is represented as bit (symbol bit) y 1 .
  • What code bit replacement method is appropriate, in other words, further improves the error rate in the AWGN communication path, and the like varies depending on the code rate and code length of the LDPC code, the modulation scheme and the like.
  • parity interleave by the parity interleaver 23 in FIG. 9 will be described with reference to FIG. 24 to FIG. 26 .
  • FIG. 24 illustrates a Tanner graph (a part thereof) of the parity check matrix of the LDPC code.
  • variable nodes code bits corresponding thereto
  • the check node returns a message in which a probability of having a value 0 and a probability of having a value 1 are equal, to all variable nodes connected to the check node. Therefore, if a plurality of variable nodes connected to the same check node simultaneously become erasures, the decoding performance is degraded.
  • the LDPC code which is defined in the standard of DVB-S.2 and output by the LDPC encoder 115 in FIG. 8 is an IRA code
  • the parity matrix H T of the parity check matrix H has a staircase structure, as illustrated in FIG. 11 .
  • FIG. 25 is a diagram illustrating a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T .
  • a of FIG. 25 shows a parity matrix H T having a staircase structure
  • B of FIG. 25 shows a Tanner graph corresponding to the parity matrix H T of A of FIG. 25 .
  • the check node connected to the two variable nodes (variable nodes for obtaining a message by using the parity bit) corresponding to the two parity bits which become error bits returns a message in which a probability of having a value 0 and a probability of having a value 1 are equal, to the variable node connected to the check node, such that decoding performance is degraded.
  • the burst length (the number of bits of the parity bits which become error bits in series) is increased, the number of check nodes returning the message indicating the equal probabilities is increased and the decoding performance is further degraded.
  • the parity interleaver 23 ( FIG. 9 ) performs interleave of interleaving the parity bit of the LDPC code from the LDPC encoder 115 to the position of another parity bit.
  • FIG. 26 is a diagram illustrating a parity matrix H T of a parity check matrix H corresponding to an LDPC code after parity interleave is performed by the parity interleaver 23 in FIG. 9 .
  • the information matrix H A of the parity check matrix H corresponding to the LDPC code which is output by the LDPC encoder 115 has a cyclic structure.
  • the cyclic structure refers to a structure in which a certain column is obtained by cyclically shifting another column, and includes for example, a structure in which for every P columns, the position of 1 in each row of the P column is the position resulting from cyclically shifting the first column of the P column, by a value proportional to a value q obtained by dividing the parity length M, in the column direction.
  • the P column in the cyclic structure is referred to as the number of columns of a unit of a cyclic structure.
  • An example of the LDPC code which is defined in the standard of DVB-S.2 includes two types of LDPC codes in which the code length N is 64800 bits and 16200 bits, as described in FIG. 12 and FIG. 13 , for both the two types of LDPC codes, the number P of columns of a unit of a cyclic structure is defined as 360 which is one of divisors excluding 1 and M among divisors having the parity length M.
  • the parity interleaver 23 interleaves the (K+qx+y+1)-th code bit among code bits of the LDPC code of N bits in the position of the (K+Py+x+1)-th code bit, as parity interleave.
  • both the (K+qx+y+1)-th code bit and the (K+Py+x+1)-th code bit are the (K+1)-th and subsequent code bits, according to the parity interleave, the position of the parity bit of the LDPC code is moved.
  • variable nodes (parity bit corresponding thereto) connected to the same check node are separated by the number P of columns of a unit of a cyclic structure, in other words, here, 360 bits, such that when the burst length is less than 360 bits, it is possible to avoid a state in which a plurality of variable nodes connected to the same check node simultaneously become error nodes, and thus to improve a resistance to the burst error.
  • the LDPC code after the parity interleave of interleaving the (K+qx+y+1)-th code bit to the position of the (K+Py+x+1)-th code bit coincides with the LDPC code of the parity check matrix (hereinafter, referred to as a conversion parity check matrix) obtained by the column permutation of replacing the (K+qx+y+1)-th column of the original parity check matrix H with the (K+Py+x+1)-th column.
  • a conversion parity check matrix obtained by the column permutation of replacing the (K+qx+y+1)-th column of the original parity check matrix H with the (K+Py+x+1)-th column.
  • the quasi-cyclic structure means a structure in which some parts, except for other parts, have the cyclic structure.
  • the conversion parity check matrix obtained by performing column permutation corresponding to the parity interleave on the parity check matrix of the LDPC code which is defined in the standard of DVB-S.2, there is no element of 1 (becomes a 0 element) in a portion of 360 rows ⁇ 360 columns in the right corner portion (a shift matrix which will be described later), and from this point, the parity check matrix does not have a (complete) cyclic structure, but a so-called quasi-cyclic structure.
  • the conversion parity check matrix in FIG. 26 is a matrix obtained by performing permutation of rows (a row permutation) so as to configure a configuration matrix which will be described later, as well as the column permutation corresponding to the parity interleave, on the original parity check matrix H.
  • the transmission apparatus 11 of FIG. 8 transmits one bit or more code bits of the LDPC code as one symbol.
  • QPSK is used as a modulation scheme
  • 16APSK or 16QAM is used as a modulation scheme
  • variable node corresponding to the code bits of one symbol being connected to the same check node to lower the probability that a plurality of variable nodes connected to the same check node (code bit corresponding thereto) become erasures at the same time, in order to improve decoding performance.
  • the information matrix H A has a cyclic structure
  • the parity matrix H T has a staircase structure.
  • FIG. 27 illustrates a conversion parity check matrix
  • a of FIG. 27 illustrates a conversion parity check matrix of the parity check matrix H of the LDPC code in which the code length N is 64800 bits and the code rate (r) is 3/4.
  • FIG. 27 illustrates a process performed by the demultiplexer 25 ( FIG. 9 ), with an LDPC code of the conversion parity check matrix of A of FIG. 27 , in other words, the LDPC code after the parity interleave as a target.
  • the code bits which are written in the four columns configuring the memory 31 , in the column direction, are read in a four bit unit, in the row direction, so as to be one symbol.
  • the code bits B 0 , B 1 , B 2 , and B 3 of four bits as one symbol may be code bits corresponding to 1 in any one row of the conversion parity check matrix of A in FIG. 27 , and in this case, the variable nodes respectively corresponding to the code bits B 0 , B 1 , B 2 , and B 3 are connected to the same check node.
  • the code bits B 0 , B 1 , B 2 , and B 3 of four bits of one symbol are code bits corresponding to 1 in any one row of the conversion parity check matrix, if an erasure occurs in the symbol, it is not possible to obtain an appropriate message from the same check node connected to the variable nodes respectively corresponding to the code bits B 0 , B 1 , B 2 , and B 3 , and thus the decoding performance is degraded.
  • a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node may be one symbol of 16APSK or 16QAM.
  • the column twist interleaver 24 performs column twist interleave of interleaving the code bit of the LDPC code after the parity interleave from the parity interleaver 23 such that a plurality of code bits corresponding to 1 in any one row of the conversion parity check matrix are not included in one symbol.
  • FIG. 28 is a diagram describing column twist interleave.
  • FIG. 28 illustrates the memory 31 (FIG. 22 and FIG. 23 ) of the demultiplexer 25 .
  • the memory 31 has a storage capacity for storing mb bits in the column (vertical) direction and N/(mb) bits in the row (horizontal) direction and is configured with mb columns. Then, the column twist interleaver 24 performs column twist interleave by controlling the write start position for the memory 31 , when writing the code bit of the LDPC code in the column direction and reading the code bit in the row direction.
  • the column twist interleaver 24 appropriately changes a write start position at which the writing of the code bit is started, for each of a plurality of columns, such that a plurality of code bits configuring one symbol which are read in the row direction do not become code bits corresponding to 1 located in a certain one row of the conversion parity check matrix (the code bits of the LDPC code are rearranged such that a plurality of code bits corresponding to 1 located in a certain one row of the parity check matrix are not included in the same symbol).
  • the column twist interleaver 24 (on behalf of the demultiplexer 25 in FIG. 22 ) performs the writing of the code bit of the LDPC code in a direction from the top to the bottom of four columns (in the column direction) configuring the memory 31 , toward the column in the left-to-right direction.
  • the column twist interleaver 24 reads the code bit from the first row of all columns configuring the memory 31 , in the row direction, in a unit of four bits (mb bit), and outputs the code bit as the LDPC code after the column twist interleave, to the replacement unit 32 ( FIG. 22 and FIG. 23 ) of the demultiplexer 25 .
  • the write start position of the leftmost column is the position of an address 0
  • the write start position of the second (from the left) column is the position of an address 2
  • the write start position of the third column is the position of an address 4
  • the write start position of the fourth column is the position of an address 7 .
  • FIG. 29 illustrates the required number of columns of the memory 31 for column twist interleave and the address of a write start position, for each modulation scheme, for respective LDPC codes of the code length N of 64800 and 11 code rates which are defined in the standard of DVB-T.2.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2 .
  • the multiple b is 1.
  • the memory 31 has four columns storing 2 ⁇ 2 bits in the row direction, and stores 64800/(2 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 4
  • the write start position of the fourth column is the position of an address 7 .
  • the multiple b is 2.
  • the memory 31 has four columns storing 4 ⁇ 1 bits in the row direction, and stores 64800/(4 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 4
  • the write start position of the fourth column is the position of an address 7 .
  • the memory 31 has eight columns storing 4 ⁇ 2 bits in the row direction, and stores 64800/(4 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 4
  • the write start position of the fifth column is the position of an address 4
  • the write start position of the sixth column is the position of an address 5
  • the write start position of the seventh column is the position of an address 7
  • the write start position of the eighth column is the position of an address 7 .
  • the memory 31 has six columns storing 6 ⁇ 1 bits in the row direction, and stores 64800/(6 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 5
  • the write start position of the fourth column is the position of an address 9
  • the write start position of the fifth column is the position of an address 10
  • the write start position of the sixth column is the position of an address 13 .
  • the memory 31 has 12 columns storing 6 ⁇ 2 bits in the row direction, and stores 64800/(6 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 3
  • the write start position of the sixth column is the position of an address 4
  • the write start position of the seventh column is the position of an address 4
  • the write start position of the eighth column is the position of an address 5
  • the write start position of the ninth column is the position of an address 5
  • the write start position of the tenth column is the position of an address 7
  • the write start position of the 11th column is the position of an address 8
  • the write start position of the 12th column is the position of an address 9 .
  • the memory 31 has 8 columns storing 8 ⁇ 1 bits in the row direction, and stores 64800/(8 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 4
  • the write start position of the fifth column is the position of an address 4
  • the write start position of the sixth column is the position of an address 5
  • the write start position of the seventh column is the position of an address 7
  • the write start position of the eighth column is the position of an address 7 .
  • the memory 31 has 16 columns storing 8 ⁇ 2 bits in the row direction, and stores 64800/(8 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 2
  • the write start position of the sixth column is the position of an address 3
  • the write start position of the seventh column is the position of an address 7
  • the write start position of the eighth column is the position of an address 15
  • the write start position of the ninth column is the position of an address 16
  • the write start position of the tenth column is the position of an address 20
  • the write start position of the 11th column is the position of an address 22
  • the write start position of the 12th column is the position of an address 22
  • the write start position of the 13th column is the position of an address 27
  • the write start position of the 14th column is the position
  • the memory 31 has 10 columns storing 10 ⁇ 1 bits in the row direction, and stores 64800/(10 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 3
  • the write start position of the third column is the position of an address 6
  • the write start position of the fourth column is the position of an address 8
  • the write start position of the fifth column is the position of an address 11
  • the write start position of the sixth column is the position of an address 13
  • the write start position of the seventh column is the position of an address 15
  • the write start position of the eighth column is the position of an address 17
  • the write start position of the ninth column is the position of an address 18
  • the write start position of the tenth column is the position of an address 20 .
  • the memory 31 has 20 columns storing 10 ⁇ 2 bits in the row direction, and stores 64800/(10 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 1
  • the write start position of the third column is the position of an address 3
  • the write start position of the fourth column is the position of an address 4
  • the write start position of the fifth column is the position of an address 5
  • the write start position of the sixth column is the position of an address 6
  • the write start position of the seventh column is the position of an address 6
  • the write start position of the eighth column is the position of an address 9
  • the write start position of the ninth column is the position of an address 13
  • the write start position of the tenth column is the position of an address 14
  • the write start position of the 11th column is the position of an address 14
  • the write start position of the 12th column is the position of an address 16
  • the write start position of the 13th column is the position of an address 21
  • the write start position of the 14th column is the position of
  • the memory 31 has 12 columns storing 12 ⁇ 1 bits in the row direction, and stores 64800/(12 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 3
  • the write start position of the sixth column is the position of an address 4
  • the write start position of the seventh column is the position of an address 4
  • the write start position of the eighth column is the position of an address 5
  • the write start position of the ninth column is the position of an address 5
  • the write start position of the tenth column is the position of an address 7
  • the write start position of the 11th column is the position of an address 8
  • the write start position of the 12th column is the position of an address 9 .
  • the memory 31 has 24 columns storing 12 ⁇ 2 bits in the row direction, and stores 64800/(12 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 5
  • the write start position of the third column is the position of an address 8
  • the write start position of the fourth column is the position of an address 8
  • the write start position of the fifth column is the position of an address 8
  • the write start position of the sixth column is the position of an address 8
  • the write start position of the seventh column is the position of an address 10
  • the write start position of the eighth column is the position of an address 10
  • the write start position of the ninth column is the position of an address 10
  • the write start position of the tenth column is the position of an address 12
  • the write start position of the 11th column is the position of an address 13
  • the write start position of the 12th column is the position of an address 16
  • the write start position of the 13th column is the position of an address 17
  • the write start position of the 14th column is the position
  • FIG. 30 illustrates the required number of columns of the memory 31 for column twist interleave and the address of a write start position, for each modulation scheme, for respective LDPC codes of the code length N of 16200 and 10 code rates which are defined in the standard of DVB-T.2.
  • the memory 31 has two columns storing 2 ⁇ 1 bits in the row direction, and stores 16200/(2 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0 .
  • the memory 31 has 4 columns storing 2 ⁇ 2 bits in the row direction, and stores 16200/(2 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 3
  • the write start position of the fourth column is the position of an address 3 .
  • the memory 31 has 4 columns storing 4 ⁇ 1 bits in the row direction, and stores 16200/(4 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 2
  • the write start position of the third column is the position of an address 3
  • the write start position of the fourth column is the position of an address 3 .
  • the memory 31 has 8 columns storing 4 ⁇ 2 bits in the row direction, and stores 16200/(4 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 1
  • the write start position of the fifth column is the position of an address 7
  • the write start position of the sixth column is the position of an address 20
  • the write start position of the seventh column is the position of an address 20
  • the write start position of the eighth column is the position of an address 21 .
  • the memory 31 has 6 columns storing 6 ⁇ 1 bits in the row direction, and stores 16200/(6 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 3
  • the write start position of the fifth column is the position of an address 7
  • the write start position of the sixth column is the position of an address 7 .
  • the memory 31 has 12 columns storing 6 ⁇ 2 bits in the row direction, and stores 16200/(6 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 2
  • the write start position of the sixth column is the position of an address 2
  • the write start position of the seventh column is the position of an address 3
  • the write start position of the eighth column is the position of an address 3
  • the write start position of the ninth column is the position of an address 3
  • the write start position of the tenth column is the position of an address 6
  • the write start position of the 11th column is the position of an address 7
  • the write start position of the 12th column is the position of an address 7 .
  • the memory 31 has 8 columns storing 8 ⁇ 1 bits in the row direction, and stores 16200/(8 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 1
  • the write start position of the fifth column is the position of an address 7
  • the write start position of the sixth column is the position of an address 20
  • the write start position of the seventh column is the position of an address 20
  • the write start position of the eighth column is the position of an address 21 .
  • the memory 31 has 10 columns storing 10 ⁇ 1 bits in the row direction, and stores 16200/(10 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 1
  • the write start position of the third column is the position of an address 2
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 3
  • the write start position of the sixth column is the position of an address 3
  • the write start position of the seventh column is the position of an address 4
  • the write start position of the eighth column is the position of an address 4
  • the write start position of the ninth column is the position of an address 5
  • the write start position of the tenth column is the position of an address 7 .
  • the memory 31 has 20 columns storing 10 ⁇ 2 bits in the row direction, and stores 16200/(10 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 2
  • the write start position of the sixth column is the position of an address 2
  • the write start position of the seventh column is the position of an address 2
  • the write start position of the eighth column is the position of an address 2
  • the write start position of the ninth column is the position of an address 5
  • the write start position of the tenth column is the position of an address 5
  • the write start position of the 11th column is the position of an address 5
  • the write start position of the 12th column is the position of an address 5
  • the write start position of the 13th column is the position of an address 5
  • the memory 31 has 12 columns storing 12 ⁇ 1 bits in the row direction, and stores 16200/(12 ⁇ 1) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 2
  • the write start position of the fifth column is the position of an address 2
  • the write start position of the sixth column is the position of an address 2
  • the write start position of the seventh column is the position of an address 3
  • the write start position of the eighth column is the position of an address 3
  • the write start position of the ninth column is the position of an address 3
  • the write start position of the tenth column is the position of an address 6
  • the write start position of the 11th column is the position of an address 7
  • the write start position of the 12th column is the position of an address 7 .
  • the memory 31 has 24 columns storing 12 ⁇ 2 bits in the row direction, and stores 16200/(12 ⁇ 2) bits in the column direction.
  • the write start position of the first column is the position of an address 0
  • the write start position of the second column is the position of an address 0
  • the write start position of the third column is the position of an address 0
  • the write start position of the fourth column is the position of an address 0
  • the write start position of the fifth column is the position of an address 0
  • the write start position of the sixth column is the position of an address 0
  • the write start position of the seventh column is the position of an address 0
  • the write start position of the eighth column is the position of an address 1
  • the write start position of the ninth column is the position of an address 1
  • the write start position of the tenth column is the position of an address 1
  • the write start position of the 11th column is the position of an address 2
  • the write start position of the 12th column is the position of an address 2
  • the write start position of the 13th column is the position of an address 2
  • FIG. 31 is a flowchart illustrating a process performed by the LDPC encoder 115 , the bit interleaver 116 , and the mapper 117 of FIG. 8 .
  • the LDPC encoder 115 receives the LDPC target data supplied from the BCH encoder 114 , LDPC-encodes the LDPC target data to the LDPC code in step S 101 , supplies the LDPC code to the bit interleaver 116 , and the process proceeds to step S 102 .
  • the bit interleaver 116 in step S 102 , performs bit interleave on the LDPC code from the LDPC encoder 115 , supplies a symbol obtained by symbolizing the LDPC code after the bit interleave to the mapper 117 , and the process proceeds to step S 103 .
  • step S 102 in the bit interleaver 116 ( FIG. 9 ), the parity interleaver 23 performs a parity interleave on the LDPC code from the LDPC encoder 115 , and supplies the LDPC code after the parity interleave to the column twist interleaver 24 .
  • the column twist interleaver 24 performs the column twist interleave on the LDPC code from the parity interleaver 23 , and supplies it to the demultiplexer 25 .
  • the demultiplexer 25 performs a replacement process of replacing the code bit of the LDPC code after the column twist interleave by the column twist interleaver 24 , and setting the code bit after the replacement as the symbol bit of the symbol (bit that represents the symbol).
  • the replacement process by the demultiplexer 25 may be performed according to the first to fourth replacement methods illustrated in FIG. 22 and FIG. 23 , and may be performed according to another replacement method.
  • the symbol obtained by the replacement process by the demultiplexer 25 is supplied to the mapper 117 from the demultiplexer 25 .
  • step S 103 the mapper 117 maps the symbol from the demultiplexer 25 to the signal point which is determined by the modulation scheme of quadrature modulation performed by the mapper 117 so as to perform quadrature modulation, and supplies the resulting data to the time interleaver 118 .
  • the parity interleaver 23 which is a block performing parity interleave and the column twist interleaver 24 which is a block performing column twist interleave are configured separately, but the parity interleaver 23 and the column twist interleaver 24 can be configured integrally.
  • both the parity interleave and the column twist interleave may be performed by reading and writing code bits to the memory, and may be represented by a matrix that converts the address for writing the code bits (write address) into the address for reading the code bits (read address).
  • the matrix representing parity interleave and the matrix representing column twist interleave are multiplied so as to obtain a matrix and a code bit is converted by using the matrix, it is possible to achieve a resulting LDPC code by performing the parity interleave on the LDPC code and performing the column twist interleave on the LDPC code which has been subjected to the parity interleave.
  • demultiplexer 25 in addition to the parity interleaver 23 and the column twist interleaver 24 .
  • the parity interleave and the column twist interleave are not to be performed.
  • the communication path 13 is a satellite line or the like in which the burst error and flutter do not need to be considered, and the like, other than AWGN, as DVB-S.2, the parity interleave and the column twist interleave are not to be performed.
  • the simulation is performed by employing a communication path having a flutter of D/U of 0 dB.
  • FIG. 32 is a diagram illustrating a communication path model employed in a simulation.
  • a of FIG. 32 illustrates a model of a flutter employed in the simulation.
  • B of FIG. 32 illustrates a model of a communication path having the flutter represented by the model of A of FIG. 32 .
  • H represents a model of the flutter in FIG. 32 .
  • N represents Inter Carrier Interference (ICI), and in the simulation, an expected value E[N 2 ] of the power is approximated to AWGN.
  • ICI Inter Carrier Interference
  • FIG. 33 and FIG. 34 show a relationship between the error rate obtained by the simulation and the Doppler frequency f d of the flutter.
  • FIG. 33 shows a relationship between the error rate and the Doppler frequency f d , when the modulation scheme is 16QAM and the code rate (r) is (3/4), and the replacement method is the first replacement method.
  • FIG. 34 shows a relationship between the error rate and the Doppler frequency f d , when the modulation scheme is 64QAM and the code rate (r) is (5/6), and the replacement method is the first replacement method.
  • a thick line shows the relationship between the error rate and the Doppler frequency f d in the case of performing all of the parity interleave, the column twist interleave, and the replacement process
  • a thin line shows the relationship between the error rate and the Doppler frequency f d in the case of performing only the replacement process among the parity interleave, the column twist interleave, and the replacement process.
  • FIG. 35 is a block diagram illustrating a configuration example of the LDPC encoder 115 of FIG. 8 .
  • the LDPC encoder 122 of FIG. 8 is configured similarly.
  • the LDPC codes of two types of code lengths N of 64800 bits and 16200 bits are defined.
  • the LDPC encoder 115 may perform coding (error correction coding) by the LDPC code of each code rate of code lengths N of 64800 bits and 16200 bits, for each code length N, according to the parity check matrix H prepared for each code rate.
  • the LDPC encoder 115 is configured with a coding processing unit 601 and a storage unit 602 .
  • the coding processing unit 601 is configured with a code rate setting unit 611 , an initial value table reading unit 612 , a parity check matrix generation unit 613 , an information bit reading unit 614 , a coding parity calculation unit 615 , and a control unit 616 , performs LDPC coding on the LDPC target data supplied to the LDPC encoder 115 , and supplies the resulting LDPC code to the bit interleaver 116 ( FIG. 8 ).
  • the code rate setting unit 611 sets the code length N and the code rate of the LDPC code in response to, for example, an operator's operations, or the like.
  • the initial value table reading unit 612 reads a parity check matrix initial value table, which will be described later, corresponding to the code length N and the code rate which are set by the code rate setting unit 611 , from the storage unit 602 .
  • the information bit reading unit 614 reads (extracts) the information bit of the information length K, from the LDPC target data supplied to the LDPC encoder 115 .
  • the coding parity calculation unit 615 generates a codeword (LDPC code) by reading the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602 , and calculating the parity bit for the information bit which is read by the information bit reading unit 614 based on a predetermined equation, by using the parity check matrix H.
  • LDPC code codeword
  • the control unit 616 controls respective blocks configuring the coding processing unit 601 .
  • the storage unit 602 stores, for example, a plurality of parity check matrix initial value tables corresponding to each of a plurality of code rates shown in FIG. 12 and FIG. 13 , for each of the code lengths N of 64800 bits and 16200 bits. Further, the storage unit 602 temporarily stores data required for the process by the coding processing unit 601 .
  • FIG. 36 is a flowchart illustrating a process of the LDPC encoder 115 in FIG. 35 .
  • step S 201 the code rate setting unit 611 determines (sets) the code length N and the code rate r for performing LDPC coding.
  • step S 202 the initial value table reading unit 612 reads a parity check matrix initial value table which is set in advance, corresponding to the code length N and the code rate r which are determined by the code rate setting unit 611 , from the storage unit 602 .
  • step S 203 the parity check matrix generation unit 613 obtains (generates) the parity check matrix H of the LDPC code of the code length N and the code rate r which are determined by the code rate setting unit 611 , by using the parity check matrix initial value table which is read from the storage unit 602 by the initial value table reading unit 612 , and supplies and stores the parity check matrix H in the storage unit 602 .
  • step S 205 the coding parity calculation unit 615 sequentially calculates the parity bit of the codeword c satisfying the equation (8), by using the information bit and the parity check matrix H from the information bit reading unit 614 .
  • c represents a row vector as a codeword (LDPC code)
  • c T represents a vector obtained by transporting the row vector c.
  • the row vector c which is the LDPC code (1 codeword)
  • the parity check matrix H and the row vector c [A
  • H T ] has the staircase structure shown in FIG. 11 , the row vector T as a parity bit configuring the row vector c [A
  • step S 206 the control unit 616 determines whether or not the LDPC coding is ended.
  • step S 206 when it is determined that the LDPC coding is not completed, in other words, for example, when there is still an LDPC target data to be subjected to the LDPC coding, the process returns to step S 201 (or step S 204 ), and thereafter, the process from the step S 201 (or step S 204 ) to S 206 is repeated.
  • step S 206 when it is determined that the LDPC coding is ended, in other words, for example, when there is no LDPC target data to be subjected to the LDPC coding, the LDPC encoder 115 ends the process.
  • a parity check matrix initial value table corresponding to each code length N and each code rate r is prepared, the LDPC encoder 115 performs the LDPC coding of a predetermined code rate r of a predetermined code length N, by using the parity check matrix H generated from the parity check matrix initial value table corresponding to the predetermined code length N and the predetermined code rate r.
  • the parity check matrix initial value table is a table that represents the positions of elements of 1 of an information matrix H A ( FIG. 10 ) corresponding to the information length K corresponding to the code length N and code rate r of the LDPC code of the parity check matrix H (LDPC code defined by the parity check matrix H) at an interval of 360 columns (column number P in units of cyclic structure), and is created in advance for each parity check matrix H of each code length N and each code rate r.
  • FIG. 37 is a diagram illustrating an example of the parity check matrix initial value table.
  • FIG. 37 shows a parity check matrix initial value table for the parity check matrix H which is defined in DVB-T.2 standard and of which the code length N is 16200 bits and the code rate r (code rate on the representation of DVB-T.2) is 1/4.
  • the parity check matrix generation unit 613 ( FIG. 35 ) obtains the parity check matrix H by using the parity check matrix initial value table in the following manner.
  • FIG. 38 is a diagram describing a method of obtaining the parity check matrix H from the parity check matrix initial value table.
  • FIG. 38 shows a parity check matrix initial value table for the parity check matrix H which is defined in DVB-T.2 standard and of which the code length N is 16200 bits and the code rate r 2/3.
  • the parity check matrix initial value table is a table representing the positions of elements of 1 in an information matrix H A ( FIG. 10 ) corresponding to the information length K according to the code length N and code rate r of the LDPC code at an interval of 360 columns (the number P of columns in a unit of a cyclic structure), and row numbers (row numbers assuming that the row number of the first row of the parity check matrix H is 0) of elements of 1 in the (1+360 ⁇ (i ⁇ 1))-th column of the parity check matrix H are arranged by the number of the column weight of the (1+360 ⁇ (i ⁇ 1))-th column, in the i-the row.
  • the parity matrix H T ( FIG. 10 ) corresponding to the parity length M, of the parity check matrix H is determined as illustrated in FIG. 25 , according to the parity check matrix initial value table, the information matrix H A ( FIG. 10 ) corresponding to the information length K, of the parity check matrix H is obtained.
  • the number k+1 of rows of the parity check matrix initial value table changes depending on the information length K.
  • 360 in the equation (9) is number P of columns of a unit of the cyclic structure described in FIG. 26 .
  • the column weight of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 38 is 13 from the first row to the ⁇ 1+360 ⁇ (3-1)-1 ⁇ -th row, and is 3 from the (1+360 ⁇ (3-1))-th row to the K-th row.
  • 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are in the first row of the parity check matrix initial value table of FIG. 38 , which shows that the elements of the rows of the row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 in the first column of the parity check matrix H are 1 (other elements are 0).
  • the parity check matrix initial value table represents the positions of elements of 1 in the information matrix H A of the parity check matrix H at an interval of 360 columns.
  • the columns other than the (1+360 ⁇ (i ⁇ 1))-th columns in the parity check matrix H are arranged by periodically cyclically shifting the elements of 1 in the (1+360 ⁇ (i ⁇ 1))-th column determined by the parity check matrix initial value table, according to the parity length M, in the down direction (the down direction of a column).
  • the row number H w-j of the element of 1 in the w-th column which is a column other than the (1+360 ⁇ (i ⁇ 1))-th column of the parity check matrix H may be obtained by the equation (10).
  • H w-j mod ⁇ h i,j +mod(( w ⁇ 1), P ) ⁇ q,M ) (10)
  • mod(x, y) means the remainder when dividing x by y.
  • P is the number P of columns of a unit of the cyclic structure described above, and is 360, for example, in the standards of DVB-S.2, DVB-T.2, and DVB-C.2, as described above.
  • the parity check matrix generation unit 613 ( FIG. 35 ) specifies the row number of the element of 1 in the (1+360 ⁇ (i ⁇ 1))-th column of the parity check matrix H by the parity check matrix initial value table.
  • the parity check matrix generation unit 613 obtains the row number H w-j of the element of 1 in the w-th column which is a column other than the (1+360 ⁇ (i ⁇ 1))-th column of the parity check matrix H by the equation (10), and generates the parity check matrix H in which the element of the row number obtained as described above is 1.
  • the demand of transmitting data of a large capacity such as an image of a high resolution will be increased in the future.
  • the LDPC code of a high code rate (low redundancy) is required, but even when using the LDPC code with high code rate, it is desired to secure good communication quality.
  • the LDPC code with high code rate in which good communication quality may be secured for example, the LDPC code (hereinafter, referred to as new LDPC code) in which the code rate r is 12/15, and the code length N is 16 k bits will be described.
  • the parity matrix H T of the parity check matrix H has a staircase structure ( FIG. 11 ) similarly to the LDPC code which is defined in the DVB-S.2, and the like, from the viewpoint of maintaining affinity (compatibility) with the LDPC code of the existing standards such as the DVB-S.2 as much as possible.
  • the information matrix H A of the parity check matrix H has a cyclic structure, and the number P of columns of a unit of the cyclic structure is 360 similarly to the LDPC code which is defined in the DVB-S.2, and the like.
  • FIG. 39 is a diagram illustrating an example of the parity check matrix initial value table of a new LDPC code.
  • the LDPC encoder 115 ( FIG. 8 , FIG. 35 ) performs LDPC coding to the new LDPC code, by using the parity check matrix H obtained from the parity check matrix initial value table shown in FIG. 39 .
  • the parity check matrix initial value table shown in FIG. 39 is stored in the storage unit 602 of the LDPC encoder 115 ( FIG. 8 ).
  • the new LDPC code obtained by using the parity check matrix H obtained from the parity check matrix initial value table shown in FIG. 39 is a high performance-LDPC code.
  • the high performance-LDPC code is the LDPC code obtained from an appropriate parity check matrix H.
  • the appropriate parity check matrix H is a parity check matrix H satisfying a predetermined condition in which when the LDPC code obtained from the parity check matrix H is transmitted at a low E s /N o , or E b /N o (signal power to noise power ratio per one bit), BER (and FER) is reduced).
  • the appropriate parity check matrix H may be obtained by performing a simulation of measuring the BER when for example, the LDPC code obtained from various check matrices satisfying the predetermined condition is transmitted at a low E s /N o .
  • a predetermined condition to be satisfied by an appropriate parity check matrix H is that an analysis result obtained by a method of analyzing a code performance called Density Evolution is good and there is no a loop of the elements of 1, which is called a cycle 4.
  • the information matrix H A if elements of 1 are dense as a cycle 4, it is known that the decoding performance of the LDPC code is deteriorated, therefore, it is required that there is no cycle 4 as a predetermined condition to be satisfied by an appropriate parity check matrix H.
  • FIG. 40 and FIG. 41 are diagrams describing density evolution by which an analysis result is obtained as a predetermined condition to be satisfied by the appropriate parity check matrix H.
  • the density evolution is a code analysis method of calculating an expected value of an error probability for an entire LDPC code (ensemble) in which the code length N characterized by a degree sequence to be described later is ⁇ .
  • the expected value of error probability of a certain ensemble is 0 at first on the AWGN channel, but if the variance of noise is gradually increasing from 0 and the variance of noise goes to a certain threshold or more, the expected value is not 0.
  • the quality of the performance of the ensemble (adequacy of a parity check matrix) by comparing the threshold of the variance of the noise in which the expected value of error probability is not 0 (hereinafter, also referred to as a performance threshold).
  • the high performance-LDPC code may be found among the LDPC codes belonging to the ensemble.
  • the above described degree sequence represents a percentage of which the variable node and the check node with each weight are present, for the code length N of the LDPC code.
  • the regular (3, 6) LDPC code of which a code rate is 1/2 belongs to an ensemble characterized by a degree sequence in which the weight (column weight) of all variable nodes is 3 and the weight (row weight) of all check nodes is 6.
  • FIG. 40 illustrates a Tanner graph of such an ensemble.
  • the number of variable nodes denoted by circle marks ( ⁇ mark) is N which is equal to the code length N
  • the number of check nodes denoted by square marks ( ⁇ mark) is N/2 which is obtained by multiplying the code length N by a code rate 1/2.
  • the interleaver randomly rearranges the 3N edges coupled to the N variable nodes, and connects each rearranged edge to any of the 3N edges coupled to the N/2 check nodes.
  • the interleaver through which the edge coupled to the variable node and the edge coupled to the check node pass, is divided into multi edges, such that characterizing the ensemble is more strictly performed.
  • FIG. 41 illustrates an example of a Tanner graph of an ensemble of a multi-edge type.
  • a performance threshold is a predetermined value or less by using a density evolution of multi-edge type, and the LDPC code of which BER is reduced in the case of using one or more quadrature modulations such as QPSK among the LDPC codes belonging to the ensemble is selected as a high performance-LDPC code, here, the performance threshold is E b /N 0 (signal power to noise power ratio per one bit) at which BER begins to fall (becomes smaller).
  • the parity check matrix initial value table of the new LDPC code described above is the parity check matrix initial value table of the LDPC code in which the code length N is 16 kbits and the code rate r is 12/15.
  • FIG. 42 is a diagram illustrating a minimum cycle length and a performance threshold of the parity check matrix H which are obtained from the parity check matrix initial value table of the new LDPC code of FIG. 39 .
  • the minimum cycle length (girth) means a minimum value of the length (loop length) of a loop configured with elements of 1.
  • the minimum cycle length is 6, and the cycle 4 (a loop configured with elements of 1, having a loop length of 4) does not exist.
  • the performance threshold of the new LDPC code is 4.269922.
  • FIG. 43 is a diagram describing a parity check matrix H (parity check matrix H of the new LDPC code) (which is obtained from the parity check matrix initial value table) of FIG. 39 .
  • the column weight X is given to the first column to a KX column, and the column weight Y 1 is given to the subsequent KY 1 columns, the column weight Y 2 is given to the subsequent KY 2 columns, the column weight 2 is given to the subsequent M ⁇ 1 columns, and the column weight 1 is given to the last one column.
  • FIG. 44 is a diagram illustrating the numbers of columns KX, KY 1 , KY 2 , and M in FIG. 43 , and column weights X, Y 1 , and Y 2 , for the parity check matrix H of the new LDPC code.
  • the parity check matrix H of the new LDPC code similar to the parity check matrix described in FIG. 12 and FIG. 13 , the closer to the first side (left side) the column is, the larger the column weight is likely to be, therefore, the code bit on the start side of the new LDPC code is likely to be strong in error (having a resistance to error).
  • FIG. 45 is a diagram illustrating a simulation result of BER/FER of the new LDPC code of FIG. 39 .
  • the communication path (channel) is assumed as AWGN, QPSK is adopted as a modulation scheme, and 50 is adopted as the iterative decoding number of times.
  • the horizontal axis represents E s /N 0
  • the vertical axis represents BER/FER.
  • the solid line represents BER
  • the dotted line represents FER.
  • FIG. 46 is a block diagram illustrating a configuration example of the reception apparatus 12 of FIG. 7 .
  • the OFDM processing unit (OFDM operation) 151 receives an OFDM signal from the transmission apparatus 11 ( FIG. 7 ), and performs a signal process on the OFDM signal.
  • the data by the OFDM processing unit 151 performing the signal process is supplied to the frame management unit 152 .
  • the frame management unit 152 performs a process (frame analysis) on a frame configured with data supplied from the OFDM processing unit 151 , and supplies the a resulting target data signal and a control data signal to the frequency deinterleavers 161 and 153 , respectively.
  • the frequency deinterleaver 153 performs frequency deinterleave in symbol units on the data from the frame management unit 152 , and supplies the resulting data to the demapper 154 .
  • the demapper 154 performs demapping (signal point arrangement decoding) and quadrature demodulation of the data (data on the constellation) from the frequency deinterleaver 153 , based on the arrangement (constellation) of a signal point as defined by quadrature modulation to be performed on the transmission apparatus 11 side, and supplies the resulting data (LDPC code (likelihood)) to the LDPC decoder 155 .
  • demapping signal point arrangement decoding
  • quadrature demodulation of the data (data on the constellation) from the frequency deinterleaver 153 , based on the arrangement (constellation) of a signal point as defined by quadrature modulation to be performed on the transmission apparatus 11 side, and supplies the resulting data (LDPC code (likelihood)) to the LDPC decoder 155 .
  • the LDPC decoder 155 performs the LDPC decoding on the LDPC code from the demapper 154 , and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder (BCH decoder) 156 .
  • the BCH decoder 156 performs the BCH decoding of the LDPC target data from the LDPC decoder 155 , and outputs the resulting control data (signaling).
  • the frequency deinterleaver 161 performs frequency deinterleave in symbol units on the data from the frame management unit 152 , and supplies the resulting data to the SISO/MISO decoder 162 .
  • the SISO/MISO decoder 162 performs space-time decoding of the data from the frequency deinterleaver 161 , and supplies the resulting data to the time deinterleaver 163 .
  • the time deinterleaver 163 performs time deinterleave in symbol units on the data from the SISO/MISO decoder 162 , and supplies the resulting data to the demapper 164 .
  • the demapper 164 performs demapping (signal point arrangement decoding) and quadrature demodulation of the data (data on the constellation) from the time deinterleaver 163 , based on the arrangement (constellation) of the signal point as defined by quadrature modulation to be performed on the transmission apparatus 11 side, and supplies the resulting data to the bit deinterleaver 165 .
  • the bit deinterleaver 165 performs the bit deinterleave of the data from the demapper 164 , and supplies the LDPC code (likelihood) which is data subjected to the bit deinterleave, and supplies the resulting data to the LDPC decoder 166 .
  • LDPC code likelihood
  • the LDPC decoder 166 performs the LDPC decoding on the LDPC code from the bit deinterleaver 165 , and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder 167 .
  • the BCH decoder 167 performs the BCH decoding of the LDPC target data from the LDPC decoder 155 , and outputs the resulting data to the BB descrambler 168 .
  • the BB descrambler 168 performs the BB descrambling on the data from the BCH decoder 167 , and supplies the resulting data to a null deletion unit (Null Deletion) 169 .
  • the null deletion unit 169 deletes Null inserted by the padder 112 of FIG. 8 , from data from the BB descrambler 168 , and supplies the result to the demultiplexer 170 .
  • the demultiplexer 170 separates one or more streams (object data) obtained by multiplexing the data from the null deletion unit 169 into each stream, performs necessary processes thereon, and outputs the result as an output stream.
  • the reception apparatus 12 can be configured without providing some blocks shown in FIG. 46 being provided.
  • the transmission apparatus 11 FIG. 8
  • the reception apparatus 12 can be configured without providing the time deinterleaver 163 , the SISO/MISO decoder 162 , the frequency deinterleaver 161 , and the frequency deinterleaver 153 respectively corresponding to the time interleaver 118 , the SISO/MISO encoder 119 , the frequency interleaver 120 , and the frequency interleaver 124 of the transmission apparatus 11 .
  • FIG. 47 is a block diagram illustrating a configuration example of a bit deinterleaver 165 in FIG. 46 .
  • the bit deinterleaver 165 is configured with a multiplexer (MUX) 54 and a column twist deinterleaver 55 , and performs (bit) deinterleave on the symbol bit of a symbol that is data from the demapper 164 ( FIG. 46 ).
  • MUX multiplexer
  • bit deinterleave on the symbol bit of a symbol that is data from the demapper 164 ( FIG. 46 ).
  • the multiplexer 54 performs a reverse replacement process (a process opposite to the replacement process) corresponding to the replacement process performed by the demultiplexer 25 in FIG. 9 on the symbol bit of the symbol from the demapper 164 , in other words, the reverse replacement process of returning the position of the code bit (likelihood) of the LDPC code which is replaced by the replacement process to its original position, and supplies the resulting LDPC code to the column twist deinterleaver 55 .
  • a reverse replacement process a process opposite to the replacement process
  • the column twist deinterleaver 55 performs a column twist deinterleave (a process opposite to the column twist interleave) corresponding to the column twist interleave as the rearrangement process performed by the column twist interleaver 24 in FIG. 9 on the LDPC code from the multiplexer 54 , in other words, for example, a column twist deinterleave as the reverse replacement process of returning the code bit of the LDPC code of which the sequence is changed by the column twist interleave as the replacement process to its original sequence.
  • the column twist deinterleaver 55 performs column twist deinterleave by writing and reading the code bit of the LDPC code to the deinterleave memory configured similarly to the memory 31 shown in FIG. 28 .
  • the writing of the code bit is performed in the row direction of the deinterleave memory by using the read address during the reading of the code bit from the memory 31 as the write address. Further, the reading of the code bit is performed by using the write address during the writing of the code bit to the memory 31 as the read address.
  • the LDPC code obtained from the column twist deinterleave is supplied from the column twist deinterleaver 55 to the LDPC decoder 166 .
  • the parity interleave, the column twist interleave, and the replacement process are performed on the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 , in the bit deinterleaver 165 , it is possible to perform a parity deinterleave corresponding to the parity interleave (a process opposite to the parity interleave, in other words, the parity deinterleave of returning the code bit of the LDPC code of which the sequence is changed by the parity interleave to its original sequence), the reverse replacement process corresponding to the replacement process, and the column twist deinterleave corresponding to the column twist interleave.
  • the multiplexer 54 of performing the reverse replacement process corresponding to the replacement process, and the column twist deinterleaver 55 of performing the column twist deinterleave corresponding to the column twist interleave are provided, but a block of performing the parity deinterleave corresponding to the parity interleave is not provided and the parity deinterleave is not performed.
  • the bit deinterleaver 165 (the column twist deinterleaver 55 thereof) performs the reverse replacement process and the column twist deinterleave on the LDPC decoder 166 , and supplies the LDPC code which is not subjected to the parity deinterleave, to the LDPC decoder 166 .
  • the LDPC decoder 166 performs the LDPC decoding on the LDPC code from the bit deinterleaver 165 by using a conversion parity check matrix obtained by performing at least column replacement corresponding to the parity interleave on the parity check matrix H used for the LDPC coding by the LDPC encoder 115 in FIG. 8 , and outputs the resulting data as a decoding result of the LDPC target data.
  • FIG. 48 is a flowchart illustrating a process performed by the demapper 164 , the bit deinterleaver 165 , and the LDPC decoder 166 in FIG. 47 .
  • step S 111 the demapper 164 performs demapping and quadrature demodulation on the data (data on the constellation mapped to a signal point) from the time deinterleaver 163 , and supplies the result to the bit deinterleaver 165 , and the process proceeds to step S 112 .
  • the bit deinterleaver 165 performs deinterleave (bit deinterleave) on the data from the demapper 164 in step S 112 , and the process proceeds to step S 113 .
  • step S 112 the multiplexer 54 in the bit deinterleaver 165 performs the reverse replacement process on the data (corresponding to the symbol bit of the symbol) from the demapper 164 , and supplies the code bit of the resulting LDPC code to the column twist deinterleaver 55 .
  • the column twist deinterleaver 55 performs column twist deinterleave on the LDPC code from the multiplexer 54 , and supplies the resulting LDPC code (likelihood) to the LDPC decoder 166 .
  • step S 113 the LDPC decoder 166 performs the LDPC decoding on the LDPC code from the column twist deinterleaver 55 by using the parity check matrix H used for the LDPC coding by the LDPC encoder 115 in FIG. 8 , in other words, by using the conversion parity check matrix H obtained by performing at least column replacement corresponding to the parity interleave on the parity check matrix H, and outputs the resulting data as a decoding result of the LDPC target data to the BCH decoder 167 .
  • the multiplexer 54 which performs the reverse replacement process and the column twist deinterleaver 55 which performs column twist deinterleave are configured separately, but the multiplexer 54 and the column twist deinterleaver 55 can be configured integrally.
  • the column twist deinterleaver 55 does not need to be provided in the bit deinterleaver 165 in FIG. 47 .
  • the LDPC decoder 166 in FIG. 46 performs the LDPC decoding on the LDPC code from the column twist deinterleaver 55 in which the reverse replacement process and the column twist deinterleave are performed and the parity deinterleave is not performed, as described above, on the parity check matrix H used for the LDPC coding by the LDPC encoder 115 in FIG. 8 by using the conversion parity check matrix obtained by performing at least column replacement corresponding to the parity interleave.
  • an LDPC decoding has been proposed previously which is able to suppress an operating frequency to a sufficiently feasible range while suppressing the circuit scale by performing the LDPC decoding by using the conversion parity check matrix (for example, see Japanese Patent No. 4224777).
  • FIG. 49 illustrates an example of the parity check matrix H of an LDPC code of which the code length N is 90 and the code rate is 2/3.
  • 0 is expressed as period (.).
  • the parity matrix has a staircase structure.
  • FIG. 50 illustrates a parity check matrix H′ obtained by performing the row permutation of equation (11) and the column permutation of equation (12) on the parity check matrix H in FIG. 49 .
  • s, t, x, and y are integers in respective ranges 0 ⁇ s ⁇ 5, 0 ⁇ x ⁇ 6, 0x ⁇ 5, and 0 ⁇ t ⁇ 6.
  • permutation is performed such that the first, seventh, 13th, 19th, and 25th rows which have remainders of 1 when dividing these by 6 are replaced with the first, second, third, fourth, and fifth rows, and the second, eighth, 14th, 20th, and 26th rows which have remainders of 2 when dividing these by 6 are replaced with the sixth, seventh, eighth, ninth, and tenth rows.
  • permutation is performed such that the 61th, 67th, 73th, 79th, and 85th columns after the 61th column (parity matrix) which have remainders of 1 when dividing these by 6 are replaced with the 61th, 62th, 63th, 64th, and 65th columns, and the 62th, 68th, 74th, 80th, and 86th columns which have remainders of 2 when dividing these by 6 are replaced with the 66th, 67th, 68th, 69th, and 70th columns.
  • the matrix obtained by performing the row and column permutation on the parity check matrix H in FIG. 49 is the parity check matrix H′ in FIG. 50 .
  • the parity check matrix H′ of FIG. 50 is a conversion parity check matrix obtained by at least performing a column permutation of replacing the (K+qx+y+1)-th column of the parity check matrix of FIG. 49 (hereinafter, as appropriate, referred to as an original parity check matrix) H with the (K+qx+x+1)-th column.
  • the conversion parity check matrix H′ in FIG. 50 is the parity check matrix of the LDPC code c′ obtained by performing column permutation of the equation (12) on the LDPC code c of the original parity check matrix H.
  • FIG. 51 illustrates a conversion parity check matrix H′ of FIG. 50 by being spaced in a unit of a 5 ⁇ 5 matrix.
  • the conversion parity check matrix H′ of FIG. 51 may be configured with the 5 ⁇ 5 unit matrix, the quasi-unit matrix, the shift matrix, the sum matrix, and the zero matrix.
  • the 5 ⁇ 5 matrices (the unit matrix, the quasi-unit matrix, the shift matrix, the sum matrix, and the zero matrix) configuring the conversion parity check matrix H′ are referred to as, hereinafter, as appropriate, configuration matrices.
  • FIG. 52 is a block diagram illustrating a configuration example of a decoding device that performs such decoding.
  • FIG. 52 illustrates a configuration example of a decoding device that performs decoding of the LDPC code by using the conversion parity check matrix H′ in FIG. 51 which is obtained by performing at least the column permutation of the equation (12) on the original parity check matrix H in FIG. 49 .
  • the decoding device in FIG. 52 is configured with an edge data storage memory 300 configured with six FIFOs 300 1 to 300 6 , a selector 301 that selects the FIFOs 300 1 to 300 6 , a check node calculation unit 302 , two cyclic shift circuits 303 and 308 , an edge data storage memory 304 configured with 18 FIFOs 304 1 to 304 18 , a selector 305 that selects the FIFOs 304 1 to 304 18 , a reception data memory 306 that stores reception data, a variable node calculation unit 307 , a decoding word calculation unit 309 , a reception data rearrangement unit 310 , and a decoding data rearrangement unit 311 .
  • the edge data storage memory 300 is configured with six FIFOs 300 1 to 300 6 , here, six is the number obtained by dividing the number 30 of rows of the conversion parity check matrix H′ in FIG. 51 by the number 5 of rows of the configuration matrix (the number P of columns of a unit of a cyclic structure).
  • Pieces of data (a message v i from the variable node) corresponding to the positions of 1 in the first row to the fifth row of the conversion parity check matrix H′ of FIG. 51 are stored in the FIFO 300 1 in the form of padding each row in the horizontal direction (in the form of ignoring 0).
  • the j-th row and the i-th column are expressed as (j, i)
  • pieces of data corresponding to the positions of 1 in a 5 ⁇ 5 unit matrix of (1, 1) to (5, 5) of the conversion parity check matrix H′ are stored in the storage area of the first stage of the FIFO 300 1 .
  • Pieces of data corresponding to the positions of 1 in a shift matrix (a shift matrix obtained by cyclically shifting the 5 ⁇ 5 unit matrix by three in the right direction) of (1, 21) to (5, 25) of the conversion parity check matrix H′ are stored in the storage area of the second stage.
  • data is stored in the storage areas of the third to eighth stages in association with the conversion parity check matrix H′.
  • pieces of data corresponding to the positions of 1 in a shift matrix (a shift matrix obtained by 1 in the first row of the 5 ⁇ 5 unit matrix being replaced with 0 and cyclic-shifted by one in the left direction) of (1, 86) to (5, 90) of the conversion parity check matrix H′ are stored in the storage area of the ninth stage.
  • Pieces of data corresponding to the positions of 1 in the sixth row to the tenth row of the conversion parity check matrix H′ of FIG. 51 are stored in the FIFO 300 2 .
  • pieces of data corresponding to the positions of 1 in a first shift matrix configuring the sum matrix (a sum matrix as a sum of a first shift matrix and a second shift matrix which are obtained by respectively cyclic-shifting the 5 ⁇ 5 unit matrix by one and two in the right direction) of (6, 1) to (10, 5) of the conversion parity check matrix H′ are stored in the storage area of the first stage of the FIFO 300 2 .
  • Pieces of data corresponding to the positions of 1 in a second shift matrix configuring the sum matrix of (6, 1) to (10, 5) of the conversion parity check matrix H′ are stored in the storage area of the second stage of the FIFO 300 2 .
  • the configuration matrix having a weight of 2 or greater when the configuration matrix is represented in the form of a sum of a plurality of matrices out of a P ⁇ P unit matrix having a weight of 1, a quasi-unit matrix having 0 for one or more elements of 1 in the unit matrix, or a shift matrix obtained by cyclically shifting the unit matrix or the quasi-unit matrix, pieces of data corresponding to the positions of 1 in the unit matrix having the weight of 1, the quasi-unit matrix, or the shift matrix (messages corresponding to the edges belonging to the unit matrix, the quasi-unit matrix, or the shift matrix) are stored in the same address (the same FIFO among the FIFOs 300 1 to 300 6 ).
  • the edge data storage memory 304 is configured with 18 FIFO 304 1 to 304 18 , here, 18 is obtained by dividing the number 90 of columns of the conversion parity check matrix H′ by the number 5 of columns of the configuration matrix (the number P of columns in a unit of the cyclic structure).
  • Pieces of data (a message u j from the check node) corresponding to the positions of 1 in the first column to the fifth column of the conversion parity check matrix H′ of FIG. 51 are stored in the FIFO 304 1 in the form of padding each column in the vertical direction (in the form of ignoring 0).
  • pieces of data corresponding to the positions of 1 in a 5 ⁇ 5 unit matrix of (1, 1) to (5, 5) of the conversion parity check matrix H′ are stored in the storage area of the first stage of the FIFO 304 1 .
  • Pieces of data corresponding to the positions of 1 in a first shift matrix configuring a sum matrix (a sum matrix as a sum of a first shift matrix and a second shift matrix which are obtained by respectively cyclic-shifting the 5 ⁇ 5 unit matrix by one and two in the right direction) of (6, 1) to (10, 5) of the conversion parity check matrix H′ are stored in the storage area of the second stage.
  • Pieces of data corresponding to the positions of 1 in a second shift matrix configuring the sum matrix of (6, 1) to (10, 5) of the conversion parity check matrix H′ are stored in the storage area of the third stage.
  • the configuration matrix having a weight of 2 or greater when the configuration matrix is represented in the form of a sum of a plurality of matrices out of a P ⁇ P unit matrix having a weight of 1, a quasi-unit matrix having 0 for one or more elements of 1 in the unit matrix, or a shift matrix obtained by cyclically shifting the unit matrix or the quasi-unit matrix, pieces of data corresponding to the positions of 1 in the unit matrix having the weight of 1, the quasi-unit matrix, or the shift matrix (messages corresponding to the edges belonging to the unit matrix, the quasi-unit matrix, or the shift matrix) are stored in the same address (the same FIFO among the FIFOs 304 1 to 304 18 ).
  • the number of stages of the storage area of the FIFO 304 1 is 5 which is the maximum number of 1 (Hamming weight) in the row direction in the first column to the fifth column of the conversion parity check matrix H′.
  • Data is stored in association with the conversion parity check matrix H′ even in the FIFOs 304 2 and 304 3 , each length (number of stages) is 5. Similarly, data is stored in association with the conversion parity check matrix H′ even in the FIFOs 304 4 to 304 12 , each length is 3. Similarly, data is stored in association with the conversion parity check matrix H′ even in the FIFOs 304 13 to 304 18 , each length is 2.
  • the edge data storage memory 300 is configured with six FIFOs 300 1 to 300 6 , and selects a FIFO which stores data from the FIFOs 300 1 to 300 6 , according to information (Matrix data) D 312 regarding which row of the conversion parity check matrix H′ of FIG. 51 five messages D 311 supplied from the cyclic shift circuit 308 in the preceding stage belong to, and stores messages D 311 in groups of five messages in the selected FIFO in order. Further, during data reading, the edge data storage memory 300 reads five messages D 300 1 in order from the FIFO 300 1 , and supplies them to the selector 301 in the next stage. After the reading of messages from the FIFO 300 1 is ended, the edge data storage memory 300 reads messages in order from the FIFOs 300 2 to 300 6 , and supplies the messages to the selector 301 .
  • information (Matrix data) D 312 regarding which row of the conversion parity check matrix H′ of FIG. 51 five messages D 311 supplied from the cyclic shift circuit
  • the selector 301 selects five messages from the FIFO from which data is read at present, among the FIFO 300 1 to 300 6 , in response to the select signal D 301 , and supplies the messages as a message D 302 to the check node calculation unit 302 .
  • the check node calculation unit 302 is configured with five check node calculators 302 1 to 302 5 , performs check node calculation according to the equation (7), by using the message D 302 supplied from the selector 301 (D 302 1 to D 302 5 ) (message v i in the equation (7)), and supplies five messages D 303 (D 303 1 to D 303 5 ) (message U j in the equation (7)) obtained from the check node calculation to the cyclic shift circuit 303 .
  • the cyclic shift circuit 303 cyclically shifts the five messages D 303 1 to D 303 5 obtained by the check node calculation unit 302 , based on information (Matrix data) D 305 regarding the number of times of cyclic shifting of the unit matrix (or quasi-unit matrix) which is a base in the conversion parity check matrix H′ which is performed on the corresponding edge, and supplies the result as a message D 304 , to the edge data storage memory 304 .
  • the edge data storage memory 304 is configured with 18 FIFOs 304 1 to 304 18 , and selects a FIFO which stores data from the FIFOs 304 1 to 304 18 , according to information D 305 regarding which row of the conversion parity check matrix H′ five messages D 304 supplied from the cyclic shift circuit 303 in the preceding stage belong to, and arranges and stores messages D 304 in groups of five messages in the selected FIFO in order. Further, during data reading, the edge data storage memory 304 reads five messages D 306 1 in order from the FIFO 304 1 , and supplies it to the selector 305 in the next stage. After the reading of data from the FIFO 304 1 is ended, the edge data storage memory 304 reads messages in order from the FIFO 304 2 to 304 18 , and supplies the messages to the selector 305 .
  • the selector 305 selects five messages from the FIFO from which data is read at present, among the FIFOs 304 1 to 304 18 , in response to the select signal D 307 , and supplies the messages as a message D 308 to the variable node calculation unit 307 and the decoding word calculation unit 309 .
  • the reception data rearrangement unit 310 rearranges the LDPC code D 313 corresponding to the parity check matrix H of FIG. 49 , received through the communication path 13 by performing column permutation of the equation (12), and supplies the rearranged LDPC code as the reception data D 314 , to the reception data memory 306 .
  • the reception data memory 306 calculates and stores the reception log likelihood ratio (LLR) from the reception data D 314 supplied from the reception data rearrangement unit 310 , and supplies the reception LLR in groups of five, as the received value D 309 , to the variable node calculation unit 307 and the decoding word calculation unit 309 .
  • LLR reception log likelihood ratio
  • the variable node calculation unit 307 is configured with five variable node calculators 307 1 to 307 5 , performs variable node calculation according to the equation (1), by using the message D 308 (D 308 1 to D 308 5 ) (message u j of the equation (1)) supplied through the selector 305 and the five received values D 309 (received value u 0i of the equation (1)) supplied from the reception data memory 306 , and supplies the message D 310 (D 310 1 to D 310 5 ) (message v i of the equation (1)) obtained by the calculation to the cyclic shift circuit 308 .
  • the cyclic shift circuit 308 cyclically shifts the five messages D 310 1 to D 310 5 obtained by the variable node calculation unit 307 , based on information regarding the number of times of cyclic shifting of the unit matrix (or quasi-unit matrix) which is a base in the conversion parity check matrix H′ which is performed on the corresponding edge, and supplies the result as a message D 311 , to the edge data storage memory 300 .
  • the decoding device of FIG. 52 decodes the LDPC code a predetermined number of times, and supplies a finally obtained decoding result to the decoding word calculation unit 309 and the decoding data rearrangement unit 311 .
  • the decoding word calculation unit 309 is configured with five decoding word calculators 309 1 to 309 5 , calculates a decoding result (decoding word) based on the equation (5) by using the five messages D 308 (D 308 1 to D 308 5 ) (message u j of the equation (5)) output by the selector 305 and the five received values D 309 (received value u 0i of the equation (5)) supplied from the reception data memory 306 , as the final stage of the multiple times of decoding, and supplies the resulting decoding data D 315 to the decoding data rearrangement unit 311 .
  • the decoding data rearrangement unit 311 rearranges and outputs the order as the final decoding result D 316 , by performing the inverse permutation to the column permutation of the equation (12) on the decoding data D 315 supplied from the decoding word calculation unit 309 .
  • the parity check matrix is converted to a parity check matrix (conversion parity check matrix) which can be expressed by a combination of a P ⁇ P unit matrix, a quasi-unit matrix having 0 for one or more elements of 1, or a shift matrix obtained by cyclically shifting the unit matrix or the quasi-unit matrix, a sum matrix which is a sum of a plurality of matrices of the unit matrix, the quasi-unit matrix, or the shift matrix, a P ⁇ P zero matrix, in other words, a combination of configuration matrices by performing one or both of the row permutation and the column permutation on the parity check matrix (original parity check matrix) as described above, such that it is possible to adopt an architecture of simultaneously performing the check node calculations and the variable node calculations P number of times, here, P is a smaller number than the number of rows and the number of columns of the parity check matrix, for the decoding of the LDPC code.
  • conversion parity check matrix conversion parity check matrix
  • the LDPC decoder 166 configuring the reception apparatus 12 of FIG. 46 performs LDPC decoding by simultaneously performing the check node calculations and the variable node calculations P number of times, similarly to, for example, the decoding device of FIG. 52 .
  • the parity check matrix of the LDPC code which is output by the LDPC encoder 115 configuring the transmission apparatus 11 of FIG. 8 is, for example, the parity check matrix H in which the parity matrix has the staircase structure, illustrated in FIG. 49
  • the LDPC code which is not subjected to the parity deinterleave in other words, the LDPC code in the state of the column permutation of the equation (12) being performed is supplied to the LDPC decoder 166 from the column twist deinterleaver 55 , and the LDPC decoder 166 performs the same process as the decoding device of FIG. 52 except for not performing the column permutation of the equation (12).
  • FIG. 53 illustrates a configuration example of the LDPC decoder 166 of FIG. 46 .
  • the LDPC decoder 166 is configured similarly to the decoding device of FIG. 52 except that the reception data rearrangement unit 310 of FIG. 52 is not provided, and performs the same process as that of decoding device of FIG. 52 except that the column permutation in equation (12) is not performed, the description thereof will be omitted.
  • the LDPC decoder 166 can be configured without providing the reception data rearrangement unit 310 , such that it is possible to reduce the size further than the size of decoding device of FIG. 52 .
  • the code length N of the LDPC code is 90
  • the information length K is 60
  • the number p of columns of a unit of a cyclic structure (the number of rows and the number of columns of the configuration matrix) is 5
  • FIG. 54 is a diagram describing a process of the multiplexer 54 of the bit deinterleaver 165 of FIG. 47 .
  • a of FIG. 54 illustrates a functional configuration example of the multiplexer 54 .
  • the multiplexer 54 is configured with a reverse replacement unit 1001 and a memory 1002 .
  • the multiplexer 54 performs a reverse replacement process (a process opposite to the replacement process) corresponding to the replacement process performed by the demultiplexer 25 of the transmission apparatus 11 on the symbol bit of the symbol from the demapper 164 in the preceding stage, in other words, the reverse replacement process of returning the position of the code bit (symbol bit) of the LDPC code which is replaced by the replacement process to its original position, and supplies the resulting LDPC code to the column twist deinterleaver 55 in the subsequent stage.
  • a reverse replacement process a process opposite to the replacement process
  • the symbol bits y 0 , y 1 , . . . , y mb-1 of mb bits of the b symbols, in a unit of (successive) b symbols are supplied to the reverse replacement unit 1001 , in the multiplexer 54 .
  • the reverse replacement unit 1001 performs a reverse replacement of returning the sequence of the symbol bits y 0 , to y mb-1 of mb bits to the arrangement of the original code bits b 0 , b 1 , b mb-1 of m bits (the sequence of the code bits b 0 to b mb-1 before the replacement is performed by the replacement unit 32 configuring the demultiplexer 25 of the transmission apparatus 11 ), and outputs the resulting code bits b 0 to b mb-1 of mb bits.
  • the memory 1002 has a storage capacity for storing mb bits in the row (horizontal) direction and N/(mb) bits in the column (vertical) direction, similarly to the memory 31 configuring the demultiplexer 25 on the transmission apparatus 11 side.
  • the memory 1002 is configured with mb columns for storing N/(mb) bits.
  • the writing of the code bit of the LDPC code which is output by the reverse replacement unit 1001 to the memory 1002 is performed in the direction of the reading of the code bit from the memory 31 of the demultiplexer 25 of the transmission apparatus 11 , and the reading of the code bit which is written to the memory 1002 is performed in the direction of the writing of the code bit to the memory 31 .
  • the multiplexer 54 of the reception apparatus 12 sequentially performs the writing of the code bit of the LDPC code which is output by the reverse replacement unit 1001 toward the bottom row from the first row of the memory 1002 .
  • the multiplexer 54 reads the code bit in the column direction from the memory 1002 and supplies it to the column twist deinterleaver 55 in the subsequent stage.
  • B of FIG. 54 is a diagram illustrating reading of a code bit from the memory 1002 .
  • the reading of the code bit of the LDPC code in a direction from the top to the bottom of the columns (in the column direction) configuring the memory 1002 is performed toward the column in the left-to-right direction.
  • FIG. 55 is a diagram describing a process of the column twist deinterleaver 55 configuring the bit deinterleaver 165 in FIG. 47 .
  • FIG. 55 illustrates a configuration example of a memory 1002 of the multiplexer 54 .
  • the memory 1002 has a storage capacity for storing mb bits in the column (vertical) direction and N/(mb) bits in the row (horizontal) direction, and is configured with mb columns.
  • the column twist deinterleaver 55 performs column twist deinterleave by controlling the read start position when writing the code bit of the LDPC code in the row direction to the memory 1002 and reading the code bit in the column direction from the memory 1002 .
  • the column twist deinterleaver 55 performs a reverse rearrangement process of returning the sequence of the code bit which is rearranged by the column twist interleave to an original sequence, by appropriately changing the read start position in which the reading of the code bit is started, for each of the plurality of columns.
  • FIG. 55 illustrates a configuration example of the memory 1002 when the modulation scheme described in FIG. 28 is 16APSK, 16QAM, or the like, and the multiple b is 1.
  • the column twist deinterleaver 55 sequentially performs the writing of the code bit of the LDPC code which is output by the replacement unit 1001 , instead of the multiplexer 54 , toward the bottom row from the first row of the memory 1002 .
  • the column twist deinterleaver 55 performs the reading of the code bit in the top to bottom direction (in the column direction) of the memory 1002 toward the column in the left-to-right direction.
  • the column twist deinterleaver 55 performs reading of the code bit from the memory 1002 , by using the write start position in which the column twist interleaver 24 of the transmission apparatus 11 writes a code bit as the read start position of the code bit.
  • the read start position for the leftmost column is the position of an address 0
  • the read start position for the second column is the position of an address 2
  • the read start position for the third column is the position of an address 4
  • the read start position for the fourth column is the position of an address 7 .
  • the sequence of the code bit that is rearranged by the column twist interleave is returned to the original sequence.
  • FIG. 56 is a block diagram illustrating another configuration example of the bit deinterleaver 165 in FIG. 46 .
  • bit deinterleaver 165 in FIG. 56 is configured similarly to the case of FIG. 47 except for that a parity deinterleaver 1011 is newly provided.
  • the bit deinterleaver 165 is configured with a multiplexer (MUX) 54 , a column twist deinterleaver 55 , and a parity deinterleaver 1011 , and performs bit deinterleave on the code bit of the LDPC code from the demapper 164 .
  • MUX multiplexer
  • the multiplexer 54 performs a reverse replacement process (a process opposite to the replacement process) corresponding to the replacement process performed by the demultiplexer 25 of the transmission apparatus 11 , in other words, the reverse replacement process of returning the position of the code bit which is replaced by the replacement process to its original position, on the LDPC code from the demapper 164 , and supplies the resulting LDPC code to the column twist deinterleaver 55 .
  • the column twist deinterleaver 55 performs a column twist deinterleave corresponding to the column twist interleave as the rearrangement process performed by the column twist interleaver 24 of the transmission apparatus 11 on the LDPC code from the multiplexer 54 .
  • the LDPC code obtained by the column twist deinterleave is supplied from the column twist deinterleaver 55 to the parity deinterleaver 1011 .
  • the parity deinterleaver 1011 performs a parity deinterleave (a process opposite to the parity interleave) corresponding to the parity interleave performed by the parity interleaver 23 of the transmission apparatus 11 , in other words, a parity deinterleave of returning the code bit of the LDPC code of which the sequence is changed by the parity interleave to its original sequence, on the code bit subjected to the column twist deinterleave by the column twist deinterleaver 55 .
  • the LDPC code obtained by the parity deinterleave is supplied from the parity deinterleaver 1011 to the LDPC decoder 166 .
  • the bit deinterleaver 165 in FIG. 56 the LDPC code subjected to the reverse replacement process, the column twist deinterleave, and the parity deinterleave, in other words, the LDPC code obtained by the LDPC coding according to the parity check matrix H is supplied to the LDPC decoder 166 .
  • the LDPC decoder 166 performs the LDPC decoding of the LDPC code from the bit deinterleaver 165 by using the parity check matrix H used in the LDPC coding by the LDPC encoder 115 of the transmission apparatus 11 .
  • the LDPC decoder 166 performs the LDPC decoding of the LDPC code from the bit deinterleaver 165 by using the parity check matrix H used in the LDPC coding by the LDPC encoder 115 of the transmission apparatus 11 , or by using a conversion parity check matrix obtained by performing at least column permutation corresponding to the parity interleave on the parity check matrix H.
  • the LDPC decoder 166 may be, for example, a decoding device that performs LDPC decoding according to a full serial decoding scheme of sequentially performing the calculation of a message (a check node message, a variable node message) one node by one node or a decoding device that performs LDPC decoding according to a full parallel decoding scheme of simultaneously (in parallel) performing the calculation of a message for all nodes.
  • the LDPC decoder 166 when the LDPC decoder 166 performs the LDPC decoding of the LDPC code on the parity check matrix H used in the LDPC coding by the LDPC encoder 115 of the transmission apparatus 11 , by using the conversion parity check matrix obtained by at least performing the column permutation corresponding to the parity interleave, the LDPC decoder 166 is a decoding device of an architecture of simultaneously performing the check node calculations and the variable node calculations P (or a divisor of P, the divisor is other than 1) number of times, and is configured by the decoding device ( FIG. 52 ) including the reception data rearrangement unit 310 that rearranges the code bit of the LDPC code, by performing the same column permutation as the column permutation for obtaining the conversion parity check matrix on the LDPC code.
  • the multiplexer 54 that performs the reverse replacement process, the column twist deinterleaver 55 that performs the column twist deinterleave, and the parity deinterleaver 1011 that performs the parity deinterleave are respectively and separately configured, but two or more of the multiplexer 54 , the column twist deinterleaver 55 , and the parity deinterleaver 1011 may be integrally configured, similarly to the parity interleaver 23 , the column twist interleaver 24 , and the demultiplexer 25 of the transmission apparatus 11 .
  • bit interleaver 116 ( FIG. 8 ) of the transmission apparatus 11 is configured without providing the parity interleaver 23 and the column twist interleaver 24
  • bit deinterleaver 165 may be configured without providing the column twist deinterleaver 55 and the parity deinterleaver 1011 .
  • the LDPC decoder 166 can be configured with the decoding device of a full serial decoding scheme that performs LDPC decoding by using the parity check matrix H, the decoding device of a full parallel decoding scheme that performs LDPC decoding by using the parity check matrix H, or the decoding device ( FIG. 52 ) including the reception data rearrangement unit 310 that performs the LDPC decoding by P simultaneous check node calculations and variable node calculations by using the conversion parity check matrix H′.
  • FIG. 57 is a block diagram illustrating a first configuration example of a reception system to which a reception apparatus 12 is applicable.
  • the reception system is configured with an acquisition unit 1101 , a channel decoding processing unit 1102 , and an information source decoding processing unit 1103 .
  • the acquisition unit 1101 acquires signals including the LDPC code obtained by at least LDPC-coding LDPC target data such as image data and sound data of a program, through for example, a channel (communication path), not shown, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, and other networks, and supplies the signals to the channel decoding processing unit 1102 .
  • a channel communication path
  • the acquisition unit 1101 acquires signals including the LDPC code obtained by at least LDPC-coding LDPC target data such as image data and sound data of a program, through for example, a channel (communication path), not shown, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, and other networks, and supplies the signals to the channel decoding processing unit 1102 .
  • the acquisition unit 1101 when signals acquired by the acquisition unit 1101 are broadcast, for example, from a broadcast station through terrestrial waves, satellite waves, cable television (CATV) networks, and the like, the acquisition unit 1101 is configured with a tuner, a Set Top Box (STB), or the like. Further, when signals acquired by the acquisition unit 1101 are multicast, for example, from a web server, as an Internet Protocol Television (IPTV), the acquisition unit 1101 is configured with, for example, a network interface (IF) such as a Network Interface Card (NIC).
  • IF network interface
  • NIC Network Interface Card
  • the channel decoding processing unit 1102 corresponds to the reception apparatus 12 .
  • the channel decoding processing unit 1102 performs a channel decoding process including at least a process of correcting an error occurring in a channel, on the signals acquired by the acquisition unit 1101 through the channel, and supplies the resulting signal to the information source decoding processing unit 1103 .
  • the signals acquired by the acquisition unit 1101 through the channel are signals obtained by performing at least the error correction coding for correcting the errors occurring in the channel, and the channel decoding processing unit 1102 performs for example, the channel decoding process such as an error correction process on such signals.
  • examples of the error correction coding include LDPC coding and BCH coding.
  • the LDPC coding is performed as the error correction coding.
  • the channel decoding process may include demodulation of a modulation signal, and the like.
  • the information source decoding processing unit 1103 performs the information source decoding process including at least a process of decompressing the compressed information to the original information on the signal subjected to the channel decoding process.
  • the signals acquired by the acquisition unit 1101 through the channel may be subjected to a compression coding for compressing information, in order to reduce the amount of data such as an image and sound as the information, in this case, the information source decoding processing unit 1103 performs the information source decoding process such as a process of decompressing (decompression process) the compressed information to the original information on the signal subjected to the channel decoding process.
  • the information source decoding processing unit 1103 performs the information source decoding process such as a process of decompressing (decompression process) the compressed information to the original information on the signal subjected to the channel decoding process.
  • the information source decoding processing unit 1103 does not perform the process of decompressing the compressed information to the original information.
  • the example of the decompression process includes MPEG decoding.
  • the channel decoding process may include descrambling and the like, in addition to the decompression process.
  • the acquisition unit 1101 acquires, for example, signals obtained by performing compression coding such as MPEG coding and error correction coding such as LDPC coding on data such as an image and sound, through the channel, and supplies it to the channel decoding processing unit 1102 .
  • the same process as that performed by the reception apparatus 12 is performed as a channel decoding process on the signal from the acquisition unit 1101 , and the resulting signal is supplied to the information source decoding processing unit 1103 .
  • the information source decoding processing unit 1103 the information source decoding process such as MPEG decoding is performed on the signal from the channel decoding processing unit 1102 , and the resulting image or sound is output.
  • the reception system of FIG. 57 described above may be applied to, for example, a television tuner that receives television broadcasting as digital broadcasting.
  • the acquisition unit 1101 , the channel decoding processing unit 1102 , and the information source decoding processing unit 1103 may be respectively configured as one independent apparatus (hardware (Integrated Circuit (IC), or the like), or a software module).
  • IC Integrated Circuit
  • a set of the acquisition unit 1101 and the channel decoding processing unit 1102 , a set of the channel decoding processing unit 1102 and the information source decoding processing unit 1103 , and a set of the acquisition unit 1101 , the channel decoding processing unit 1102 , and the information source decoding processing unit 1103 are respectively configured as one independent apparatus.
  • FIG. 58 is a block diagram illustrating a second configuration example of a reception system to which the reception apparatus 12 is applicable.
  • the reception system of FIG. 58 is in common with the case in FIG. 57 in having the acquisition unit 1101 , the channel decoding processing unit 1102 , and the information source decoding processing unit 1103 , and is different from the case in FIG. 57 in that an output unit 1111 is newly provided.
  • the output unit 1111 is a display device that displays an image or a speaker that outputs sound, and outputs the image and sound or the like as a signal output from the information source decoding processing unit 1103 .
  • the output unit 1111 displays the image or outputs sound.
  • the reception system of FIG. 58 described above may be applied to for example, a television receiver (TV) receiving television broadcasting as digital broadcasting, a radio receiver receiving radio broadcasting, or the like.
  • TV television receiver
  • radio receiver receiving radio broadcasting
  • the signal output by the channel decoding processing unit 1102 is supplied to the output unit 1111 .
  • FIG. 59 is a block diagram illustrating a third configuration example of a reception system to which the reception apparatus 12 is applicable.
  • the reception system of FIG. 59 is in common with the case in FIG. 57 in having the acquisition unit 1101 and the channel decoding processing unit 1102 .
  • the reception system in FIG. 59 is different from the case in FIG. 57 in that the information source decoding processing unit 1103 is not provided and a recording unit 1121 is newly provided.
  • the recording unit 1121 records (stores) signals (for example, TS packets of TS of MPEG) which are output by the channel decoding processing unit 1102 on a recording (storage) medium such as an optical disc, a hard disk (magnetic disk), and a flash memory.
  • a recording (storage) medium such as an optical disc, a hard disk (magnetic disk), and a flash memory.
  • the reception system of FIG. 59 as described above may be applied to a recorder recording television broadcasting.
  • the reception system is configured by providing an information source decoding processing unit 1103 , and may record a signal subjected to an information source decoding process by the information source decoding processing unit 1103 , in other words, an image and sound resulting from the decoding in the recording unit 1121 .
  • a series of processes described above may be performed by either hardware or software.
  • a program constituting the software is installed in a general-purpose computer or the like.
  • FIG. 60 illustrates a configuration example of an embodiment of a computer in which a program executing the series of processes described above is installed.
  • the program may be recorded in advance on a hard disk 705 or a ROM 703 as a recording medium built in the computer.
  • a removable recording medium 711 such as a flexible disk, a Compact Disc Read Only Memory (CD-ROM), a Magneto Optical (MO) disc, a Digital Versatile Disc (DVD), a magnetic disk, and a semiconductor memory.
  • a removable recording medium 711 may be provided as so-called package software.
  • the program may be wirelessly transferred to the computer from the download site through an artificial satellite for digital satellite broadcasting or transferred to the computer in a wired manner through a network such as a Local Area Network (LAN) or the Internet, and the computer may receive the program transferred as described above by the communication unit 708 , and install the program on a built-in hard disk 705 .
  • LAN Local Area Network
  • the computer has a built-in Central Processing Unit (CPU) 702 .
  • An input and output interface 710 is connected to the CPU 702 through a bus 701 , and when an instruction is input by an input unit 707 such as a keyboard, a mouse, a microphone or the like being operated by a user, through the input and output interface 710 , the CPU 702 executes the program stored in the Read Only Memory (ROM) 703 in response to the instruction.
  • ROM Read Only Memory
  • the CPU 702 loads a program stored in the hard disk 705 , a program that is transferred from a satellite or network, received by the communication unit 708 , and installed in the hard disk 705 , or a program that is read from the removable recording medium 711 mounted on the drive 709 and is installed on the hard disk 705 , in the Random Access Memory (RAM) 704 , and executes the programs.
  • the CPU 702 executes the process according to the flowchart described above or the process performed by the configuration of the block diagram described above.
  • the CPU 702 causes the process result, as required, for example, through the input and output interface 710 , to be output from an output unit 706 configured with a Liquid Crystal Display (LCD), a speaker and the like, or be transmitted from the communication unit 708 , or to be recorded in the hard disk 705 .
  • LCD Liquid Crystal Display
  • processing steps of describing a program causing a computer to execute various processes need not necessarily be processed in time series according to the order described in the flowchart, and the processing steps include processes to be processed in parallel or individually (for example, a parallel process or a process using objects).
  • a program may be processed by a single computer, or may be distributed and processed by a plurality of computers.
  • a program may be transferred to a remote computer and executed.
  • a system means a set of a plurality of components (devices, modules (products), and the like), and it does not matter whether all the components are in the same housing. Therefore, both a plurality of devices which are housed in separate housings and connected through a network, and, a single device in which a plurality of modules are housed in a single housing are systems.
  • the present technology can take a cloud computing configuration in which one function is shared and processed jointly by a plurality of devices through the network.
  • each step described in the flowchart described above is performed by a single apparatus, and may be performed by being shared by a plurality of devices.
  • the plurality of processes included in the one step are performed by a single apparatus, and may be performed by being shared by a plurality of devices.
  • the new LDPC code described above (the parity check matrix initial value table thereof), it is possible to use satellite lines, terrestrial waves, cables (wired lines), and others as the communication path 13 ( FIG. 7 ). Further, it is possible to use the new LDPC code for data transmission other than digital broadcasting.

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