US20150296618A1 - Substrate structure and manufacturing method thereof - Google Patents

Substrate structure and manufacturing method thereof Download PDF

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Publication number
US20150296618A1
US20150296618A1 US14/287,071 US201414287071A US2015296618A1 US 20150296618 A1 US20150296618 A1 US 20150296618A1 US 201414287071 A US201414287071 A US 201414287071A US 2015296618 A1 US2015296618 A1 US 2015296618A1
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Prior art keywords
substrate
layer
carrier
release layer
pads
Prior art date
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Abandoned
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US14/287,071
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English (en)
Inventor
Yu-Chi Huang
Kuo-Tung Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Subtron Technology Co Ltd
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Subtron Technology Co Ltd
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Filing date
Publication date
Application filed by Subtron Technology Co Ltd filed Critical Subtron Technology Co Ltd
Assigned to SUBTRON TECHNOLOGY CO., LTD. reassignment SUBTRON TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, YU-CHI, LIN, KUO-TUNG
Publication of US20150296618A1 publication Critical patent/US20150296618A1/en
Priority to US15/648,465 priority Critical patent/US9883594B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/24—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer not being coherent before laminating, e.g. made up from granular material sprinkled onto a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/26—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/04—Punching, slitting or perforating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/26—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the lamination process, e.g. release layers or pressure equalising layers
    • B32B2037/268—Release layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/04—Punching, slitting or perforating
    • B32B2038/047—Perforating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/202—Conductive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/204—Di-electric
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/08—PCBs, i.e. printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0221—Perforating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Definitions

  • the invention relates to a substrate structure, and particularly relates to a substrate structure having a preferable bonding strength or capable of providing a sensing space required by a sensing element of a package structure and meeting the need for filling paste or liquid and the need for ventilation of a package element.
  • Circuit substrates are used in a variety of electronic products for electrical signal transmission, power supply, and ground connection. Through miniaturization of electronic products, circuit substrates are also developed in the tendency of being more compact and having a more intensive circuitry. However, in the chip packaging process, the miniaturized substrates may be broken easily or have defects in wiring.
  • the conventional way is to attach a plurality of non-defective substrates to a carrier through a release layer to improve the rigidity of the overall structure of the substrates, and the attached substrates and carrier are then sent for the subsequent chip packaging process. Then, the substrates packaged with chips are removed from the carrier.
  • the adhesive characteristic of the release layer influences the bonding strength between the substrates and the carrier.
  • a release layer having a greater adhesive force is usually used to ensure the substrates and the carrier are closely bonded.
  • some adhesive material may remain on the back surface of the substrate due to the overly strong adhesive force of the release layer. If a release layer having a weaker adhesive force is used to avoid leaving the adhesive material on the substrate or to separate the substrate from the carrier easily, the issue that the substrate may be separated from the carrier during the process arises.
  • the industry certainly needs a method that closely bonds the substrates and the carrier during the chip packaging process, while allows the substrates to be easily separated from the carrier.
  • the invention provides a substrate structure capable of improving a bonding strength between a substrate and a carrier while making the substrate and the carrier easy to separate.
  • the invention provides a manufacturing method of a substrate structure.
  • the substrate structure manufactured according to the method has a higher bonding strength between a substrate and a carrier thereof and allows the substrate to be easily separated from the carrier.
  • the invention provides a substrate structure capable of providing a sensing space for a sensing element of a package structure and meeting the need for filling paste or liquid and the need for ventilation of a package element.
  • the invention provides a manufacturing method of a substrate structure.
  • the substrate structure manufactured according to the method is capable of providing a sensing space for a sensing element of a package structure and meeting the need for filling paste or liquid and the need for ventilation of a package element.
  • the substrate structure of the invention includes a carrier and a substrate.
  • the carrier includes a release layer, a dielectric layer, and a metal layer.
  • the dielectric layer is disposed between the release layer and the metal layer.
  • the substrate includes a packaging region and a peripheral region.
  • the peripheral region is connected to the packaging region and surrounds the packaging region.
  • the peripheral region has the plurality of through holes.
  • the substrate is disposed on the carrier.
  • the release layer is located between the substrate and the dielectric layer, and the release layer and the dielectric layer are filled into the through holes, such that the substrate is separably attached to the carrier.
  • the manufacturing method of the substrate structure of the invention provides steps as follows. First of all, a substrate is provided.
  • the substrate includes a packaging region and a peripheral region.
  • the peripheral region is connected to the packaging region and surrounds the packaging region. Pluralities of through holes are formed in the peripheral region.
  • a carrier is provided.
  • the carrier includes a release layer, a dielectric layer, and a metal layer.
  • the dielectric layer is disposed between the release layer and the metal layer.
  • the substrate is laminated to the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier.
  • the substrate structure of the invention includes a carrier and a substrate.
  • the carrier includes a release layer, a dielectric layer, and a metal layer.
  • the dielectric layer is disposed between the release layer and the metal layer.
  • the substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region.
  • the packaging region has the plurality of through holes.
  • the substrate is disposed on the carrier.
  • the release layer is located between the substrate and the dielectric layer, and the release layer and the dielectric layer are filled into the through holes, such that the substrate is separably attached to the carrier.
  • the manufacturing method of the substrate structure of the invention provides steps as follows. First of all, a substrate is provided.
  • the substrate includes a packaging region and a peripheral region.
  • the peripheral region is connected to the packaging region and surrounds the packaging region. Pluralities of through holes are formed in the packaging region.
  • a carrier is provided.
  • the carrier includes a release layer, a dielectric layer, and a metal layer.
  • the dielectric layer is disposed between the release layer and the metal layer.
  • the substrate is laminated to the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier.
  • a material of the release layer includes an aluminum foil or a polyimide (PI) film.
  • the substrate is a single-layer circuit board.
  • the substrate is a multi-layer circuit board.
  • the substrate further includes a plurality of pads and a patterned solder mask.
  • the pads are disposed on an upper surface of the substrate and located within the packaging region.
  • the patterned solder mask covers the upper surface of the substrate and exposes the pads.
  • the substrate further includes a surface finishing layer covering the pads.
  • the step of providing the substrate further includes forming a plurality of pads on an upper surface of the substrate.
  • the pads are located within the packaging region.
  • a patterned solder mask is formed on the upper surface. The patterned solder mask exposes the pads.
  • the step of forming the substrate further includes forming a surface finishing layer covering the pads.
  • the substrate structure further includes a chip disposed on the packaging region and covering one of the through holes to contact the release layer.
  • the chip is electrically connected to the pads through a plurality of wires.
  • the manufacturing method of the substrate structure further includes disposing a chip in the packaging region of the substrate.
  • the chip covers one of the through holes and contacts the release layer.
  • the chip is electrically connected to the pads by a plurality of wires.
  • the substrate is laminated to the carrier to squeeze the release layer and the dielectric layer of the carrier into the through holes of the substrate, so as to enhance the bonding strength between the substrate and the carrier.
  • the substrate may be easily separated from the carrier without being damaged after the subsequent packaging process is completed.
  • the invention not only enhances the bonding strength between the substrate and the carrier in the substrate structure, but also reduces the manufacturing difficulty and increases the yield rate of the manufacturing process.
  • FIGS. 1A to 1D are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.
  • FIG. 2 is a top schematic view illustrating a substrate according to an embodiment of the invention.
  • FIG. 3 is a top schematic view illustrating a substrate according to an embodiment of the invention.
  • FIGS. 4A to 4E are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.
  • FIGS. 1A to 1D are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.
  • FIG. 2 is a top schematic view illustrating a substrate according to an embodiment of the invention.
  • the manufacturing method of the substrate structure of this embodiment includes steps as follows. First of all, as shown in FIG. 1A , a substrate 110 is provided.
  • the substrate may be a single-layer circuit board or a multi-layer circuit board.
  • the substrate 110 may include a packaging region A 1 and a peripheral region A 2 , as shown in FIG. 1A .
  • the peripheral region A 2 may be connected to the packaging region A 1 and surround the packaging region A 1 , as shown in FIG. 2 .
  • the peripheral region A 2 in FIG. 2 is only shown for an illustrative purpose, and the invention is not limited thereto. In other embodiments of the invention, the peripheral region A 2 may be merely located at one side of the packaging region A 1 without surrounding the whole packaging region A 1 .
  • a manufacturing process of the substrate 110 may include forming a plurality of pads 130 on an upper surface 114 of the substrate 110 .
  • the pads 130 are located within the packaging region A 1 , and may be connected to corresponding vias 132 on the substrate 110 , for example, so as to be electrically connected to a circuit layer 134 on the other side of the substrate 110 through the vias 132 .
  • a patterned solder mask 140 may be further formed on the upper surface 114 .
  • the patterned solder mask 140 may have a plurality of openings 142 and each of the openings 142 exposes at least a portion of the corresponding pad 130 .
  • a surface finishing layer 150 is formed on the pads 130 exposed by the patterned solder mask 140 to form the substrate 110 shown in FIG. 1A .
  • a material of the surface finishing layer is gold, nickel, silver, or other suitable materials.
  • a plurality of through holes 112 are formed in the peripheral region A 2 , so as to form the substrate 110 shown in FIG. 2 .
  • the substrate 110 includes the upper surface 114 and a lower surface 116 opposite to each other, and the through holes 112 connect the upper surface 114 and the lower surface 116 , as shown in FIG. 1B .
  • the carrier 120 includes a release layer 122 , a dielectric layer 124 , and a metal layer 126 .
  • the dielectric layer 124 is disposed between the release layer 122 and the metal layer 126 .
  • a material of the release layer may include an aluminum foil or a polyimide film (PI film)
  • a material of the dielectric layer 124 may include prepreg (PP)
  • a material of the metal layer 126 may be copper foil, for example.
  • the embodiment only serves for an illustrative purpose, and the invention is not limited thereto.
  • the substrate 110 is laminated onto the release layer 122 of the carrier 120 , such that the release layer 122 and the dielectric layer 124 are filled into the through holes 112 , as shown in FIG. 1D .
  • the release layer 122 is located between the substrate 110 and the dielectric layer 124 and contacts an inner wall of each of the through holes 112 , such that the substrate 110 may be separably attached to the carrier 120 .
  • the substrate structure 100 formed by the manufacturing method includes the substrate 110 and the carrier 120 .
  • the substrate 110 includes the packaging region A 1 and the peripheral region A 2 .
  • the peripheral region A 2 has the plurality of through holes 112 and is connected to the packaging region A 1
  • the peripheral region A 2 surrounds the packaging region A 1 .
  • the substrate 110 may further include the plurality of pads 130 , the patterned solder mask 140 , and the surface finishing layer 150 .
  • the pads 130 are located within the packaging region A 1 of the substrate 110 and connected to the corresponding vias 132 , so as to be electrically connected to the circuit layer 134 on the other side of the substrate 110 through the vias 132 .
  • the patterned solder mask 140 covers the upper surface 114 of the substrate and exposes the pads 130 .
  • the surface finishing layer 150 covers the pads 130 exposed by the patterned solder mask 140 .
  • a material of the surface finishing layer 150 is gold, nickel, silver, or other suitable materials.
  • the carrier 110 includes the release layer 122 , the dielectric layer 124 , and the metal layer 126 .
  • the dielectric layer 124 is disposed between the release layer 122 and the metal layer 126 .
  • the substrate 110 is disposed on the release layer 122 of the carrier 120 , and the release layer 122 and the dielectric layer 124 are filled in the through holes 112 , such that the release layer 122 is located between the substrate 110 and the dielectric layer 124 and contacts an inner wall of each through hole 112 , so as to separably attach the substrate 110 to the carrier 120 .
  • the release layer 122 and the dielectric layer 124 of the carrier 120 are pressed and filled into the through holes 112 of the substrate 110 by laminating the substrate 110 to the carrier 120 , thereby enhancing a bonding strength between the substrate 110 and the carrier 120 .
  • the substrate 110 may be easily separated from the carrier 120 without being damaged after a subsequent packaging process is completed.
  • the embodiment not only enhances the bonding strength between the substrate 110 and the carrier 120 in the substrate structure 100 , but reduces a manufacturing difficulty and increases a yield rate of the manufacturing process.
  • FIG. 3 is a top schematic view illustrating a substrate according to an embodiment of the invention.
  • FIGS. 4A to 4E are cross-sectional schematic views illustrating the processes of a manufacturing method of a substrate structure according to an embodiment of the invention.
  • a substrate structure 100 a of this embodiment is similar to the substrate structure 100 . Therefore, the reference numerals and a part of the contents in the previous embodiment are used in the this embodiment, in which identical reference numerals indicate identical or similar components, and repeated description of the same technical contents is omitted. For a detailed description of the omitted parts, reference can be found in the previous embodiment, and no repeated description is contained in this embodiment. Detailed description regarding the difference between the substrate structure 100 a of this embodiment and the substrate structure 100 in the previous embodiment is provided below.
  • the manufacturing method of the substrate structure of this embodiment includes steps as follows. First of all, as shown in FIG. 1A , a substrate 110 a is provided.
  • the substrate 110 a may be a single-layer circuit board or a multi-layer circuit board.
  • the substrate 110 a may include the packaging region A 1 and the peripheral region A 2 .
  • the peripheral region A 2 is connected to the packaging region A 1 and surrounds the packaging region A 1 .
  • FIGS. 4A to 4E only illustrate partial cross-sections of the packaging region A 1 without illustrating partial cross-sections of the peripheral region A 2 .
  • a manufacturing process of the substrate 110 a of this embodiment is similar to the manufacturing process of the substrate 110 .
  • the plurality of pads 130 may also be formed on the packaging region A 1 of the substrate 110 a , and then the patterned solder mask 140 is formed on the substrate 110 a .
  • the patterned solder mask 140 covers the upper surface 114 of the substrate 110 a and exposes the pads 130 .
  • the surface finishing layer 150 is formed on the pads 130 exposed by the patterned solder mask 140 .
  • through holes 112 a of this embodiment are formed in the packaging region A 1 of the substrate 110 a , and the pads 130 may be disposed around the through holes 112 a , for example.
  • the carrier 120 shown in FIG. 4B is provided. Like the carrier 120 of the previous embodiment, the carrier 120 of this embodiment also includes the release layer 122 , the dielectric layer 124 , and the metal layer 126 . Relevant technical contents may be referred to the previous embodiment, and no further details in this respect will be reiterated below. Then, as shown in FIG. 4C , the substrate 110 a is laminated to the release layer 122 of the carrier 120 , such that the release layer 122 and the dielectric layer 124 are pressed and filled into the through holes 112 a located within the packaging region A 1 , as shown in FIG. 4C .
  • the release layer 122 is located between the substrate 110 a and the dielectric layer 124 and contacts an inner wall of each through hole 112 a , as shown in FIG. 4C , so as to separably attach the substrate 110 a to the carrier 120 .
  • preliminary manufacture of the substrate structure 100 a is completed.
  • the substrate structure 100 a formed by the manufacturing method is similar to the substrate structure 100 of the previous embodiment, except that the through holes 112 a are disposed in the packaging region A 1 of the substrate 110 a . Therefore, in this embodiment, the release layer 122 and the dielectric layer 124 of the carrier 120 are pressed and filled into the through holes 112 a of the packaging region A 1 of the substrate 110 a , so as to preserve a space for filling a heat dissipation paste or liquid, preserve a space to be conductive for ventilation, or preserve a sensing space for a sensing element of a chip on the substrate structure 100 a , for example.
  • a chip 160 may be further disposed in the packaging region A 1 of the substrate 110 a in this embodiment.
  • the chip 160 covers one of the through holes 112 a and contacts the release layer 122 in the through holes 112 a .
  • the chip 160 is electrically connected to the pads 130 by a plurality of wires 170 , so as to fix the chip 160 to the substrate 110 a and be electrically connected to the substrate 110 a .
  • the chip 160 includes an active surface 162 and a back surface 164 opposite to the active surface 162 .
  • the wires 170 are connected to the active surface 162 of the chip 160 .
  • the carrier 120 is removed to expose the back surface 164 of the chip 160 by utilizing the characteristic that the release layer 122 is easily separated from the substrate 110 a .
  • a chip package formed by the aforementioned manufacturing process is able to provide a sensing space for a sensing element of the chip 160 .
  • the chip 160 may include a light-sensing element, a sound-sensing element, or a touch-sensing element.
  • a light-sensing region of the light-sensing element, a resonant region i.e.
  • the chip 160 may also utilize the back surface 164 exposed by the through holes 112 a for heat dissipation or ventilation.
  • a heat dissipation paste or liquid maybe filled in the through holes 112 a to facilitate heat dissipation efficiency. Therefore, this embodiment is capable of increasing a functionality of the chip 160 .
  • the substrate is laminated to the carrier so the release layer and the dielectric layer of the carrier are pressed and filled into the through holes of the substrate, so as to enhance the bonding strength between the substrate and the carrier.
  • the substrate may be easily separated from the carrier without being damaged after the subsequent packaging process is completed.
  • the invention not only enhances the bonding strength between the substrate and the carrier in the substrate structure, but reduces the manufacturing difficulty and increases the yield rate of the manufacturing process.
  • the through holes of the substrate are located within the packaging region of the substrate and the chip is disposed on the packaging region to cover the through holes, the through holes of the substrate then exposes the surface of the chip after the carrier is separated from the substrate by utilizing the release layer.
  • the sensing space of the sensing element of the chip which may serve as the light-sensing region of the light-sensing element, the resonant region (vibrating region) of the sound-sensing element, and the touch region of the touch-sensing element, may be provided.
  • the chip may utilize the surface exposed by the through holes for heat dissipation or ventilation.
  • the heat dissipation paste may be filled in the through holes, so as to facilitate the heat dissipation efficiency of the chip. Therefore, the invention also increases the functionality of the chip.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US14/287,071 2014-04-15 2014-05-26 Substrate structure and manufacturing method thereof Abandoned US20150296618A1 (en)

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JP2015204454A (ja) 2015-11-16
CN105023873A (zh) 2015-11-04
TW201539682A (zh) 2015-10-16
US9883594B2 (en) 2018-01-30
TWI512924B (zh) 2015-12-11
US20170311450A1 (en) 2017-10-26
JP5810206B1 (ja) 2015-11-11

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