US20150255402A1 - Packaged radio-frequency module having wirebond shielding - Google Patents

Packaged radio-frequency module having wirebond shielding Download PDF

Info

Publication number
US20150255402A1
US20150255402A1 US14/720,872 US201514720872A US2015255402A1 US 20150255402 A1 US20150255402 A1 US 20150255402A1 US 201514720872 A US201514720872 A US 201514720872A US 2015255402 A1 US2015255402 A1 US 2015255402A1
Authority
US
United States
Prior art keywords
wirebonds
packaged
component
wirebond
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/720,872
Inventor
Dinhphuoc V. Hoang
Thomas E. Noll
Anil K. Agarwal
Robert W. Warren
Matthew S. Read
Anthony LoBianco
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Skyworks Solutions Inc
Original Assignee
Skyworks Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/793,618 external-priority patent/US7198987B1/en
Application filed by Skyworks Solutions Inc filed Critical Skyworks Solutions Inc
Priority to US14/720,872 priority Critical patent/US20150255402A1/en
Publication of US20150255402A1 publication Critical patent/US20150255402A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Definitions

  • the present invention is generally in the field of semiconductor devices. More particularly, the invention is in the field of semiconductor device packaging.
  • Portable electronic devices such as cell phones, typically utilize multi-component semiconductor modules to provide a high level of circuit integration in a single molded package.
  • the multi-component semiconductor module can include, for example, a semiconductor die and a number of electronic components, which are mounted on a circuit board.
  • the circuit board including the semiconductor die and electronic components can be encapsulated in a molding process to form an overmolded semiconductor package.
  • the overmolded semiconductor package must be shielded from Electro-Magnetic Interference (EMI), which includes Radio Frequency Interference (RFI).
  • EMI Electro-Magnetic Interference
  • RFID Radio Frequency Interference
  • semiconductor device manufacturers are challenged to provide effective EMI shielding for an overmolded semiconductor package without increasing the size of the package and without substantially increasing packaging cost.
  • EMI shielding is provided a prefabricated metal shield, which is formed over the overmolded semiconductor package.
  • the prefabricated metal shield typically includes a wall, which is formed around the overmolded semiconductor package, and a cover, which is attached to the wall and situated a sufficient distance above the overmolded package to avoid interfering with the package.
  • the prefabricated metal shield undesirably increases the thickness of the final overmolded package.
  • the formation of the prefabricated metal shield requires an extra process step and additional materials, which significantly increases packaging cost.
  • conductive foam or rubber is applied over the overmolded semiconductor package to absorb and trap EMI.
  • the conductive foam or rubber must be applied manually and requires special materials and an extra process, which significantly increases packaging cost. Additionally, the conductive foam or rubber undesirably increases the thickness of the final overmolded package.
  • the present invention is directed to an overmolded semiconductor package with a wirebond cage for EMI shielding.
  • the present invention addresses and resolves the need in the art for a cost-effective EMI shield for an overmolded semiconductor package that does not substantially increase package thickness.
  • an overmolded package includes a component situated on a substrate.
  • the component can be an active device or a passive device.
  • the overmolded package further includes an overmold situated over the component and the substrate.
  • the overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds.
  • the wirebond cage forms an EMI shield around the component.
  • the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.
  • the conductive layer may be conductive ink.
  • each of the wirebonds can have a first and second ends and a middle portion, where the first and second ends are connected to respective bond pads on the substrate and the middle portion is connected to the conductive layer.
  • each of the wirebonds can have first and second ends, where the first end is connected to a bond pad on the substrate and the second end is connected to the conductive layer.
  • the invention is a method for achieving the above-described structure.
  • Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
  • FIG. 1A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 1B illustrates a cross sectional view of the exemplary structure of FIG. 1A .
  • FIG. 2A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 2B illustrates a cross sectional view of the exemplary structure of FIG. 2A .
  • FIG. 3A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 3B illustrates a cross sectional view of the exemplary structure of FIG. 3A .
  • FIG. 4A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 4B illustrates a cross sectional view of the exemplary structure of FIG. 4A .
  • FIG. 5 is a flowchart corresponding to exemplary method steps according to one embodiment of the present invention.
  • the present invention is directed to an overmolded semiconductor package with a wirebond cage for EMI shielding.
  • the following description contains specific information pertaining to the implementation of the present invention.
  • One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.
  • FIG. 1A shows a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention. Certain details and features have been left out of FIG. 1A that are apparent to a person of ordinary skill in the art.
  • Overmolded semiconductor package 100 which is also referred to as an “overmolded package” in the present application, includes component 102 , bond pads 104 a , 104 b , 104 c , and 104 d (hereinafter “bond pads 104 a through 104 d ”), wirebond cage 106 , and conductive layer 108 .
  • Wirebond cage 106 includes a number of wirebonds, such as wirebonds 110 a and 110 b . It is noted that only bond pads 104 a through 104 e and wirebonds 110 a through 110 e are discussed in detail herein to preserve brevity.
  • component 102 is situated on a substrate (not shown in FIG. 1A ).
  • Component 102 can be an active device, such as a semiconductor die, which can include RF circuitry, for example.
  • component 102 can be a passive device, such as an inductor.
  • bond pads 104 a through 104 d are situated on and along the perimeter of the substrate (not shown in FIG. 1A ).
  • Bond pads 104 a through 104 d can comprise a metal such as copper or aluminum and can be formed, for example, by depositing and patterning a layer of metal, such as copper or aluminum, and plating the layer of metal with gold.
  • Bond pads 104 a through 104 d can be connected to a reference potential (not shown in FIG. 1A ), which can be any constant DC plane that does not have an AC component.
  • wirebond 110 a forms a loop that extends between bond pads 104 a and 104 b and wirebond 110 b forms a loop that extends between bond pads 104 c and 104 d .
  • Wirebonds 110 a and 110 b can comprise gold or other suitable metal, for example.
  • wirebond 110 a can be attached to bond pads 104 a and 104 b and the respective ends of wirebond 110 b can be attached to bond pads 104 c and 104 d by utilizing a suitable bonding process, for example.
  • Wirebonds 110 a and 110 b form a portion of wirebond cage 106 , which extends along the perimeter of the substrate (not shown in FIG. 1A ).
  • conductive layer 108 is situated on an overmold (not shown in FIG. 1A ). Conductive layer 108 is also situated over component 102 , bond pads 104 a through 104 d , wirebonds 110 a and 110 b , and the substrate (not shown in FIG. 1A ).
  • conductive layer 108 can comprise a conductive coating, such as a conductive ink, which can include copper, silver, or other conductive metals.
  • conductive layer 108 can comprise a layer of copper, aluminum, or other suitable metal.
  • Conductive layer 108 is connected to a middle portion of each of the wirebonds (e.g. wirebonds 110 a and 110 b ) in wirebond cage 106 . Conductive layer 108 and wirebonds 110 a and 110 b will be further discussed below in relation to FIG. 1B .
  • FIG. 1B a cross-sectional view is shown of overmolded semiconductor package 100 in FIG. 1A along line 1 B- 1 B in FIG. 1A .
  • component 102 , bond pads 104 a through 104 d , wirebond cage 106 , conductive layer 108 , and wirebonds 110 a and 110 b correspond to the same elements in FIG. 1A and FIG. 1B .
  • component 102 and bond pads 104 a through 104 d are situated on substrate 114 , which can comprise a ceramic material, a laminate material, or other suitable type of material.
  • substrate 114 can include a patterned metal layer on top and bottom substrate surfaces and vias, for example.
  • the respective ends of wirebond 110 a are situated on bond pads 104 a and 104 b and middle portion 111 of wirebond 110 a is in contact with conductive layer 108 .
  • the respective ends of wirebond 110 b are situated on bond pads 104 c and 104 d and middle portion 113 of wirebond 110 b is in contact with conductive layer 108 .
  • the ends of each wirebond e.g. wirebonds 110 a and 110 b
  • are separated by wirebond loop width 120 and adjacent wirebonds e.g. wirebonds 110 a and 110 b
  • wirebond spacing 122 In the embodiment in FIGS.
  • wirebond loop width 120 can be different than wirebond spacing 122 .
  • wirebond loop width 120 can be substantially equal to wirebond spacing 122 .
  • Wirebond loop width 120 and wirebond spacing 122 can each range in value from microns to millimeters, for example. In the embodiment in FIGS. 1A and 1B , wirebond loop width 120 and wirebond spacing 122 can be selected to achieve EMI shielding for a particular frequency or a particular range of frequencies.
  • overmold 116 is situated over component 102 , bond pads 104 a through 104 d , and substrate 114 and encapsulates wirebond cage 106 , which includes wirebonds 110 a and 110 b .
  • Overmold 116 can comprise epoxy or other suitable molding compound and can be formed in a molding process in a manner known in the art.
  • conductive layer 108 is situated on top surface 118 of overmold 116 and situated over component 102 , bond pads 104 a through 104 d and substrate 114 . Conductive layer 108 is also situated over and in contact with wirebonds 110 a and 110 b .
  • Conductive layer 108 has thickness 124 , which can be between 25.0 microns and 50.0 microns, for example. In other embodiments, thickness 124 can be between 5.0 microns and 100.0 microns.
  • Conductive layer 108 has height 126 , which refers to the distance between the top surface of substrate 114 and top surface 118 of overmold 116 . Height 126 can be approximately 1.0 mm, for example. However, height 126 may also be greater or less than 1.0 mm.
  • EMI shield for component 102 .
  • the EMI shield can be formed during formation of overmolded semiconductor package 100 by bonding the ends of wirebonds to respective bond pads, which can be formed on the top surface of substrate 114 .
  • the ends of wirebond 110 a can be bonded to respective bond pads 104 a and 104 b , for example.
  • Overmold 116 can then be formed by utilizing a mold compound, such as epoxy, in a molding process as known in the art to cover component 102 , the bond pads (e.g. bond pads 104 a through 104 d ), and the top surface of substrate 114 and to encapsulate the wirebonds (e.g. wirebonds 110 a and 110 b ) that form wirebond cage 106 .
  • Overmold 116 is desirably formed such that the center portion of each wirebond (e.g. center portions 111 and 113 of respective wirebonds 110 a and 110 b ) in wirebond cage 106 is exposed above top surface 118 of overmold 116 .
  • overmold 116 may inadvertently cover the center portions of the wirebonds in wirebond cage 106 .
  • the covering portion of overmold 116 can be removed from the center portions of the wirebonds by utilizing a laser abrasion process, a mechanical milling process, a diamond polish process, or other suitable process.
  • Conductive layer 108 can then be formed by utilizing a screen printing process, spraying process, electroplating process, thermal spray deposition process, or other suitable process to apply a layer of conductive ink on top surface 118 of overmold 116 and on the exposed center portions of the wirebonds in wirebond cage 106 .
  • conductive layer 108 comprises a layer of metal
  • the layer of metal can be deposited on top surface 118 of overmold 116 and on the exposed center portions of the wirebonds by utilizing a chemical vapor deposition (CVD) process or other suitable deposition processes.
  • CVD chemical vapor deposition
  • the invention's overmolded package includes conductive layer 108 , which provides EMI shielding over component 102 , and wirebond cage 106 , which provides EMI shielding around component 102 .
  • the invention utilizes a conductive layer and a wirebond cage to achieve an effective EMI shield for an overmolded package.
  • the invention can provide an EMI shield between a component, such as an active device, inside the overmolded package and the environment outside of the package.
  • the invention advantageously achieves an EMI shield having a low manufacturing cost compared to a conventional prefabricated metal shield.
  • the conductive layer in the invention's EMI shield is significantly thinner than metal utilized to form the conventional prefabricated metal shield.
  • the invention's EMI shield results in a thinner overmolded package compared to an overmolded package that includes a conventional prefabricated metal shield.
  • the invention provides an EMI shield having a flexible design that can more easily accommodate variations in package size and has increased scalability compared to a conventional prefabricated metal shield. Moreover, since wirebonds are significantly thinner than the walls of the conventional prefabricated metal shield, the invention's EMI shield consumes less space in the overmolded package compared to the conventional prefabricated metal shield.
  • FIG. 2A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 2A that are apparent to a person of ordinary skill in the art.
  • Overmolded semiconductor package 200 which is also referred to as an “overmolded package” in the present application, includes components 202 and 203 , bond pads 204 a , 204 b , 204 c , and 204 d (hereinafter “bond pads 204 a through 204 d ”), bond pads 205 a , 205 b , 205 c , and 205 d (hereinafter “bond pads 205 a through 205 d ”), wirebond cage 206 , and conductive layer 208 .
  • Wirebond cage 206 includes wirebond cage section 207 , which includes wirebonds 210 a and 210 b , and wirebond cage section 209 , which includes wirebonds 215 a and 215 b . It is noted that only bond pads 204 a through 204 d and 205 a through 205 d and wirebonds 210 a , 210 b , 215 a , and 215 b are discussed in detail herein to preserve brevity.
  • components 202 and 203 are situated on a substrate (not shown in FIG. 2A ).
  • components 202 and 203 can each be an active device, such as a semiconductor die, which can include RF circuitry, for example.
  • component 202 can be a passive device, such as an inductor
  • component 203 can be an active device, such as a semiconductor die.
  • components 202 and 203 can each be a passive device.
  • bond pads 204 a through 204 d and 205 a through 205 d are situated on the substrate (not shown in FIG.
  • Bond pads 204 a through 204 d and 205 a through 205 d can be connected to a reference potential (not shown in FIG. 2A ), which can be any constant DC plane that does not have an AC component.
  • respective ends of wirebond 210 a are situated on bond pads 204 a and 204 b and respective ends of wirebond 210 b are situated on bond pads 204 c and 204 d .
  • Wirebonds 210 a and 210 b are substantially similar in composition and formation to wirebonds 110 a and 110 b in FIGS. 1A and 1B .
  • respective ends of wirebond 215 a are situated on bond pads 205 a and 205 b and respective ends of wirebond 215 b are situated on bond pads 205 c and 205 d .
  • Wirebonds 215 a and 215 b are also substantially similar in composition and formation to wirebonds 110 a and 110 b in FIGS. 1A and 1B .
  • Wirebonds 210 a and 210 b form a portion of wirebond cage section 207 , which extends along the perimeter of the substrate (not shown in FIG. 2A ), and wirebonds 215 a and 215 b form a portion of wirebond cage section 209 , which is situated between components 202 and 203 .
  • wirebond cage section 207 the ends of each wirebond (e.g. wirebond 210 a ) are separated by wirebond loop width 220 and adjacent wirebonds (e.g. wirebonds 210 a and 210 b ) are separated by wirebond spacing 222 .
  • wirebond cage section 209 the ends of each wirebond (e.g. wirebonds 215 a ) are separated by wirebond loop width 221 and adjacent wirebonds (e.g. wirebonds 215 a and 215 b ) are separated by wirebond spacing 223 .
  • wirebond spacing 223 In the embodiment in FIG.
  • wirebond loop width 220 can be different than wirebond spacing 222 and wirebond loop width 221 can be different than wirebond spacing 223 .
  • wirebond loop width 220 can be different than wirebond loop width 221 and wirebond spacing 222 can be different than wirebond spacing 223 .
  • wirebond loop width 220 can be substantially equal to equal to wirebond spacing 222 and wirebond loop width 221 can be substantially equal to wirebond spacing 223 .
  • Wirebond loop widths 220 and 221 and wirebond spacings 222 and 223 can each range in value from microns to millimeters, for example. The value of each of wirebond loop widths 220 and 221 and wirebond spacings 222 and 223 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • conductive layer 208 is situated on an overmold (not shown in FIG. 2A ) and also situated over components 202 and 203 , bond pads 204 a through 204 d and 205 a through 205 d , wirebonds 210 a , 210 b , 215 a , and 215 b , and the substrate (not shown in FIG. 2A ).
  • Conductive layer 208 is substantially similar in composition and formation to conductive layer 108 in FIGS. 1A and 1B .
  • conductive layer 208 can comprise a conductive coating, such as a conductive ink.
  • conductive layer 208 can comprise a layer of copper, aluminum, or other suitable metal.
  • Conductive layer 208 is connected to a middle portion of each of the wirebonds (e.g. wirebonds 210 a and 210 b ) in wirebond cage section 207 and connected to a middle portion of each of the wirebonds (e.g. wirebonds 215 a and 215 b ) in wirebond cage section 209 .
  • Conductive layer 208 and wirebonds 210 a and 210 b will be further discussed below in relation to FIG. 2B .
  • FIG. 2B a cross-sectional view is shown of overmolded semiconductor package 200 in FIG. 2A along line 2 B- 2 B in FIG. 2A .
  • components 202 and 203 , bond pads 204 a through 204 d , wirebond cage 206 , wirebond cage section 207 , conductive layer 208 , and wirebonds 210 a and 210 b correspond to the same elements in FIG. 2A and FIG. 2B .
  • components 202 and 203 and bond pads 204 a through 204 d are situated on substrate 214 , which is substantially similar in composition to substrate 114 in FIGS. 1A and 1B . Also shown in FIG.
  • the respective ends of wirebond 210 a are situated on bond pads 204 a and 204 b and middle portion 211 of wirebond 210 a is in contact with conductive layer 208 . Further shown in FIG. 2B , the respective ends of wirebond 210 b are situated on bond pads 204 c and 204 d and middle portion 213 of wirebond 210 b is in contact with conductive layer 208 .
  • overmold 216 is situated over components 202 and 203 , bond pads 204 a through 204 d , and substrate 214 and encapsulates wirebond cage 206 , which includes wirebonds 210 a and 210 b .
  • Overmold 216 is substantially similar in composition and formation to overmold 116 in FIG. 1B .
  • conductive layer 208 is situated on top surface 218 of overmold 216 and situated over components 202 and 203 , bond pads 204 a through 204 d and substrate 214 .
  • Conductive layer 208 is also situated over and in contact with wirebonds 210 a and 210 b .
  • Conductive layer 208 is substantially similar in composition, thickness, and formation to conductive layer 108 in FIGS. 1A and 1B .
  • conductive layer 208 and wirebond cage 206 which are electrically connected together, form an EMI shield for components 202 and 203 .
  • the EMI shield which includes conductive layer 208 and wirebond cage 206 , can be formed in a similar manner as the EMI shield in the embodiment in FIGS. 1A and 1B .
  • the invention's overmolded package includes conductive layer 208 , which provides EMI shielding over components 202 and 203 , wirebond cage section 207 , which provides EMI shielding around components 202 and 203 , and wirebond cage section 209 , which provides EMI shielding between components 202 and 203 .
  • the invention utilizes a conductive layer and wirebond cage sections to advantageously achieve an effective EMI shield between two components inside an overmolded package and the environment outside of the package and an effective EMI shield between the two components inside the package.
  • the embodiment in FIGS. 2A and 2B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B .
  • FIG. 3A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 3A that are apparent to a person of ordinary skill in the art.
  • Overmolded semiconductor package 300 which is also referred to as an “overmolded package” in the present application, includes component 302 , bond pads 304 a , 304 b , 304 c , 304 d , and 304 e (hereinafter “bond pads 304 a through 304 e ”), wirebond cage 306 , and conductive layer 308 .
  • component 302 is situated on a substrate (not shown in FIG. 3A ).
  • Component 302 can be an active device, such as a semiconductor die with RF circuitry.
  • component 302 can be a passive device, such as an inductor.
  • bond pads 304 a through 304 e are situated on and along the perimeter of the substrate (not shown in FIG. 3A ).
  • Bond pads 304 a through 304 e can comprise a metal such as copper or aluminum and can be formed, for example, by depositing and patterning a layer of metal, such as copper or aluminum, and plating the layer of metal with gold.
  • Bond pads 304 a through 304 e can be connected to a reference potential (not shown in FIG. 3A ), which can be any constant DC plane that does not have an AC component.
  • wirebonds 310 a through 310 e are situated on respective bond pads 304 a through 304 e and form wirebond cage 306 , which surrounds component 302 .
  • Wirebonds 310 a through 310 e can comprise gold or other suitable metal and can be connected to respective bond pads 304 a through 304 e by using a bonding process, for example.
  • wirebond spacing 312 refers to the distance between adjacent wirebonds (e.g. the distance between wirebonds 310 a and 310 b ).
  • Wirebond spacing 312 can range in value from microns to millimeters. In one embodiment, wirebond spacing 312 can be approximately 2.5 mm. The value of wirebond spacing 312 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • Conductive layer 308 is situated on overmold (not shown in FIG. 3A ). Conductive layer 308 is also situated over component 302 , bond pads 304 a through 304 e , wirebonds 310 a through 310 e , and the substrate (not shown in FIG. 3A ). Conductive layer 308 can comprise a conductive coating, such as a conductive ink, which can include copper, silver, or other conductive metals. In another embodiment, conductive layer 308 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 308 is connected to an end of each of the wirebonds (e.g. wirebonds 310 a through 310 e ) in wirebond cage 306 .
  • FIG. 3B a cross-sectional view is shown of overmolded semiconductor package 300 in FIG. 3A along line 3 B- 3 B in FIG. 3A .
  • component 302 , bond pads 304 a and 304 b , wirebond cage 306 , conductive layer 308 , wirebonds 310 a and 310 b , and wirebond spacing 312 correspond to the same elements in FIG. 3A and FIG. 3B .
  • component 302 and bond pads 304 a and 304 b are situated on substrate 314 , which can comprise a ceramic material, a laminate material, or other suitable type of material.
  • substrate 314 can include a patterned metal layer on top and bottom substrate surfaces and vias, for example.
  • overmold 316 is situated over component 302 , bond pads 304 a and 304 b , and substrate 314 and encapsulates wirebond cage 306 , which includes wirebonds 310 a and 310 b .
  • Overmold 316 is substantially similar in composition and formation as overmold 116 in FIG. 1B .
  • conductive layer 308 is situated on top surface 318 of overmold 316 and situated over component 302 , bond pads 304 a and 304 b and substrate 314 .
  • Conductive layer 308 is also situated over and in contact with wirebonds 310 a and 310 b of wirebond cage 306 .
  • Conductive layer 308 has thickness 320 and height 322 , which are substantially similar to thickness 124 and height 126 in FIG. 1B , respectively.
  • wirebonds 310 a and 310 b of wirebond cage 306 are situated between respective bond pads 304 a and 304 b and conductive layer 308 and also situated in (i.e. encapsulated by) overmold 316 .
  • one end of each of wirebonds 310 a and 310 b is bonded to respective bond pads 304 a and 304 b and the other end of each of wirebonds 310 a and 310 b is in contact with conductive layer 308 .
  • conductive layer 308 and wirebond cage 306 which are electrically connected together, form an EMI shield for component 302 .
  • the EMI shield can be formed during formation of overmolded semiconductor package 300 by bonding one end of each of the wirebonds (e.g. wirebond 310 a ) that form wirebond cage 306 to a bond pad (e.g. bond pad 304 a ) by using a suitable bonding process as is know in the art.
  • Overmold 316 can then be formed by utilizing a mold compound, such as epoxy, in a molding process as known in the art to cover component 302 , the bond pads (e.g. bond pads 304 a and 304 b ), and the top surface of substrate 314 and to encapsulate the wirebonds (e.g. wirebonds 310 a and 310 b ) that form wirebond cage 306 .
  • Overmold 316 is desirably formed such that the unattached ends of the wirebonds (e.g. wirebonds 310 a and 310 b ) in wirebond cage 306 are exposed above top surface 318 of overmold 316 .
  • the unattached wirebond ends can be exposed by utilizing a laser abrasion process, a mechanical milling process, a diamond polish process, or other suitable process to remove the covering portion of overmold 316 .
  • Conductive layer 308 can then be formed by utilizing a screen printing process, spraying process, electroplating process, or thermal spray deposition process to apply a layer of conductive ink on top surface 318 of overmold 316 and on the exposed ends of the wirebonds in wirebond cage 306 .
  • conductive layer 308 comprises a layer of metal
  • the layer of metal can be deposited on top surface 318 of overmold 316 and on the exposed wirebond ends by utilizing a CVD process or other suitable deposition processes.
  • the invention's overmolded package includes conductive layer 308 , which provides EMI shielding over component 302 , and wirebond cage 306 , which provides EMI shielding around component 302 .
  • the invention utilizes a conductive layer and a wirebond cage to achieve an effective EMI shield between a component inside an overmolded package and the environment outside of the package.
  • the embodiment in FIGS. 3A and 3B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B .
  • FIG. 4A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 4A that are apparent to a person of ordinary skill in the art.
  • Overmolded semiconductor package 400 which is also referred to as an “overmolded package” in the present application, includes components 402 and 403 , bond pads 404 a , 404 b , 405 a , and 405 b , wirebond cage 406 , and conductive layer 408 .
  • Wirebond cage 406 includes wirebond cage section 407 , which includes wirebonds 410 a and 410 b , and wirebond cage section 409 , which includes wirebonds 415 a and 415 b .
  • bond pads 404 a , 404 b , 405 a , and 405 b and wirebonds 410 a , 410 b , 415 a , and 415 b are discussed in detail herein to preserve brevity.
  • components 402 and 403 are situated on a substrate (not shown in FIG. 4A ).
  • components 402 and 403 can each be an active device, such as a semiconductor die, which can include RF circuitry, for example.
  • component 402 can be a passive device, such as an inductor
  • component 403 can be an active device, such as a semiconductor die.
  • components 402 and 403 can each be a passive device.
  • bond pads 404 a , 404 b , 405 a , and 405 b are situated on the substrate (not shown in FIG.
  • Bond pads 404 a , 404 b , 405 a , and 405 b can be connected to a reference potential (not shown in FIG. 4A ), which can be any constant DC plane that does not have an AC component.
  • wirebonds 410 a and 410 b are situated on bond pads 404 a and 404 b and respective ends of wirebonds 415 a and 415 b are situated on bond pads 405 a and 405 b .
  • Wirebonds 410 a , 410 b , 415 a , and 415 b are substantially similar in composition and formation to wirebonds 310 a through 310 e in FIG. 3A .
  • Wirebonds 410 a and 410 b form a portion of wirebond cage section 407 , which extends along the perimeter of the substrate (not shown in FIG. 4A ), and wirebonds 415 a and 415 b form a portion of wirebond cage section 409 , which is situated between components 402 and 403 .
  • wirebond spacing 412 in wirebond cage section 407 , adjacent wirebonds (e.g. wirebonds 410 a and 410 b ) are separated by wirebond spacing 412 .
  • wirebond spacing 412 In wirebond cage section 409 , adjacent wirebonds (e.g. wirebonds 415 a and 415 b ) are separated by wirebond spacing 413 .
  • wirebond spacing 412 can be different than wirebond spacing 413 .
  • wirebond spacing 412 can be substantially equal to wirebond spacing 413 .
  • Wirebond spacing 412 and wirebond spacing 413 can range in value from microns to millimeters, for example. The value of each of wirebond spacings 412 and 413 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • conductive layer 408 is situated on an overmold (not shown in FIG. 4A ) and also situated over components 402 and 403 , bond pads 404 a , 404 b , 405 a , and 405 b , wirebonds 410 a , 410 b , 415 a , and 415 b , and the substrate (not shown in FIG. 4A ).
  • Conductive layer 408 is substantially similar in composition and formation to conductive layer 308 in FIGS. 3A and 3B .
  • conductive layer 408 can comprise a conductive coating, such as a conductive ink.
  • conductive layer 408 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 408 is connected to an end of each of the wirebonds (e.g. wirebonds 410 a and 410 b ) in wirebond cage section 407 and connected to an end of each of the wirebonds (e.g. wirebonds 415 a and 415 b ) in wirebond cage section 409 . Conductive layer 408 and wirebonds 410 a and 410 b will be further discussed below in relation to FIG. 4B .
  • FIG. 4B a cross-sectional view is shown of overmolded semiconductor package 400 in FIG. 4A along line 4 B- 4 B in FIG. 4A .
  • components 402 and 403 , bond pads 404 a and 404 b , wirebond cage 406 , wirebond cage section 407 , conductive layer 408 , wirebonds 410 a and 410 b , and wirebond spacing 412 correspond to the same elements in FIG. 4A and FIG. 4B .
  • components 402 and 403 and bond pads 404 a and 404 b are situated on substrate 414 , which is substantially similar in composition to substrate 314 in FIGS. 3A and 3B .
  • wirebonds 410 a and 410 b are situated between respective bond pads 404 a and 404 b and conductive layer 408 .
  • overmold 416 is situated over components 402 and 403 , bond pads 404 a and 404 b , and substrate 414 and encapsulates wirebond cage 406 , which includes wirebonds 410 a and 410 b .
  • Overmold 416 is substantially similar in composition and formation to overmold 316 in FIG. 3B .
  • conductive layer 408 is situated on top surface 418 of overmold 416 and situated over components 402 and 403 , bond pads 404 a and 404 b and substrate 414 .
  • Conductive layer 408 is also situated over and in contact with wirebonds 410 a and 410 b and is substantially similar in composition, thickness, and formation to conductive layer 308 in FIGS. 3A and 3B .
  • conductive layer 408 and wirebond cage 406 which are electrically connected together, form an EMI shield for components 402 and 403 .
  • the EMI shield which includes conductive layer 408 and wirebond cage 406 , can be formed in a similar manner as the EMI shield in the embodiment in FIGS. 3A and 3B .
  • the invention's overmolded package includes conductive layer 408 , which provides EMI shielding over components 402 and 403 , wirebond cage section 407 , which provides EMI shielding around components 402 and 403 , and wirebond cage section 409 , which provides EMI shielding between components 402 and 403 .
  • the invention utilizes a conductive layer and wirebond cage sections to advantageously achieve an effective EMI shield between two components inside an overmolded package and the environment outside of the package and an effective EMI shield between the two components inside the package.
  • the embodiment in FIGS. 4A and 4B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B .
  • FIG. 5 shows a flowchart illustrating an exemplary method according to one embodiment of the present invention. Certain details and features have been left out of flowchart 500 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art.
  • bond pads are formed on a substrate that includes one or more components and wirebonds are attached to the bond pads to form a wirebond cage.
  • bonds pads 104 a through 104 d in FIG. 1B can be formed on substrate 114 , which includes component 102 , by depositing and patterning a layer of copper, aluminum, or other suitable metal.
  • wirebonds 110 a and 110 b can be attached to respective bond pads 104 a and 104 b and bond pads 104 c and 104 d by using a suitable bonding process to form wirebond cage 106 .
  • an overmold is formed over one or more components, the wirebond cage, the bond pads, and the substrate.
  • overmold 116 in FIG. 1B which can comprise an epoxy molding compound, can be formed over component 102 , wirebond cage 106 , which includes wirebonds 110 a and 110 b , bond pads 104 a through 104 d , and substrate 114 in a molding process in a manner known in the art.
  • a conductive layer is formed on a top surface of the overmold such that the conductive layer is in contact with the wirebond cage.
  • overmold 116 can be formed such that middle portions 111 and 113 of respective wirebonds 110 a and 110 b are exposed.
  • Conductive layer 108 in FIG. 1B can then be formed by applying a conductive ink over exposed middle portions 111 and 113 of respective wirebonds 110 a and 110 b and on top surface 118 of overmold 116 .
  • the conductive ink can be applied by utilizing a spraying process, electroplating process, thermal spray deposition process, or other suitable process, for example.
  • the invention utilizes a conductive layer and a wirebond cage to advantageously achieve an effective EMI shield between one or more components inside an overmolded package and the environment outside of the package. Additionally, in the embodiments in FIGS. 2A , 2 B, 4 A, and 4 B, the invention utilizes a wirebond cage section to achieve an effective EMI shield between two components inside the package. Furthermore, in the embodiments in FIGS.
  • the invention advantageously achieves an effective EMI shield for an overmolded package that has a flexible design, is cost effective, and does not substantially increase the size of the overmolded package.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.

Description

    RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 13/311,493, filed on Dec. 5, 2011, entitled “OVERMOLDED SEMICONDUCTOR PACKAGE WITH WIREBONDS FOR ELECTROMAGNETIC SHIELDING,” which is a divisional of U.S. patent application Ser. No. 12/970,705, filed on Dec. 16, 2010, now U.S. Pat. No. 8,071,431, entitled “OVERMOLDED SEMICONDUCTOR PACKAGE WITH A WIREBOND CAGE FOR EMI SHIELDING,” which is a divisional of U.S. patent application Ser. No. 11/499,285, filed on Aug. 4, 2006, now U.S. Pat. No. 8,399,972, entitled “OVERMOLDED SEMICONDUCTOR PACKAGE WITH A WIREBOND CAGE FOR EMI SHIELDING,” which is a continuation-in-part of, and claims benefit of the filing date of, U.S. patent application Ser. No. 10/793,618, filed on Mar. 4, 2004, now U.S. Pat. No. 7,198,987, entitled “OVERMOLDED SEMICONDUCTOR PACKAGE WITH AN INTEGRATED EMI AND RFI SHIELD,” the benefits of the filing dates of which are hereby claimed and the disclosures of which are hereby expressly incorporated by reference in their entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is generally in the field of semiconductor devices. More particularly, the invention is in the field of semiconductor device packaging.
  • 2. Related Art
  • Portable electronic devices, such as cell phones, typically utilize multi-component semiconductor modules to provide a high level of circuit integration in a single molded package. The multi-component semiconductor module can include, for example, a semiconductor die and a number of electronic components, which are mounted on a circuit board. The circuit board including the semiconductor die and electronic components can be encapsulated in a molding process to form an overmolded semiconductor package. To ensure an acceptable level of performance in devices such as cell phones, which are required to properly operate in diverse environments, the overmolded semiconductor package must be shielded from Electro-Magnetic Interference (EMI), which includes Radio Frequency Interference (RFI). However, semiconductor device manufacturers are challenged to provide effective EMI shielding for an overmolded semiconductor package without increasing the size of the package and without substantially increasing packaging cost.
  • In one approach, EMI shielding is provided a prefabricated metal shield, which is formed over the overmolded semiconductor package. The prefabricated metal shield typically includes a wall, which is formed around the overmolded semiconductor package, and a cover, which is attached to the wall and situated a sufficient distance above the overmolded package to avoid interfering with the package. As a result, the prefabricated metal shield undesirably increases the thickness of the final overmolded package. Also, the formation of the prefabricated metal shield requires an extra process step and additional materials, which significantly increases packaging cost.
  • In another approach, conductive foam or rubber is applied over the overmolded semiconductor package to absorb and trap EMI. However, the conductive foam or rubber must be applied manually and requires special materials and an extra process, which significantly increases packaging cost. Additionally, the conductive foam or rubber undesirably increases the thickness of the final overmolded package.
  • Thus, there is a need in the art for a cost-effective EMI shield for an overmolded semiconductor package that does not substantially increase package thickness.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to an overmolded semiconductor package with a wirebond cage for EMI shielding. The present invention addresses and resolves the need in the art for a cost-effective EMI shield for an overmolded semiconductor package that does not substantially increase package thickness.
  • According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. For example, the component can be an active device or a passive device. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component.
  • According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. For example, the conductive layer may be conductive ink. For example, each of the wirebonds can have a first and second ends and a middle portion, where the first and second ends are connected to respective bond pads on the substrate and the middle portion is connected to the conductive layer. For example, each of the wirebonds can have first and second ends, where the first end is connected to a bond pad on the substrate and the second end is connected to the conductive layer.
  • According to one embodiment, the invention is a method for achieving the above-described structure. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 1B illustrates a cross sectional view of the exemplary structure of FIG. 1A.
  • FIG. 2A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 2B illustrates a cross sectional view of the exemplary structure of FIG. 2A.
  • FIG. 3A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 3B illustrates a cross sectional view of the exemplary structure of FIG. 3A.
  • FIG. 4A illustrates a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention.
  • FIG. 4B illustrates a cross sectional view of the exemplary structure of FIG. 4A.
  • FIG. 5 is a flowchart corresponding to exemplary method steps according to one embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The present invention is directed to an overmolded semiconductor package with a wirebond cage for EMI shielding. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.
  • The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.
  • FIG. 1A shows a top view of an exemplary overmolded semiconductor package in accordance with one embodiment of the present invention. Certain details and features have been left out of FIG. 1A that are apparent to a person of ordinary skill in the art. Overmolded semiconductor package 100, which is also referred to as an “overmolded package” in the present application, includes component 102, bond pads 104 a, 104 b, 104 c, and 104 d (hereinafter “bond pads 104 a through 104 d”), wirebond cage 106, and conductive layer 108. Wirebond cage 106 includes a number of wirebonds, such as wirebonds 110 a and 110 b. It is noted that only bond pads 104 a through 104 e and wirebonds 110 a through 110 e are discussed in detail herein to preserve brevity.
  • As shown in FIG. 1A, component 102 is situated on a substrate (not shown in FIG. 1A). Component 102 can be an active device, such as a semiconductor die, which can include RF circuitry, for example. In one embodiment, component 102 can be a passive device, such as an inductor. Also shown in FIG. 1A, bond pads 104 a through 104 d are situated on and along the perimeter of the substrate (not shown in FIG. 1A). Bond pads 104 a through 104 d can comprise a metal such as copper or aluminum and can be formed, for example, by depositing and patterning a layer of metal, such as copper or aluminum, and plating the layer of metal with gold. Bond pads 104 a through 104 d can be connected to a reference potential (not shown in FIG. 1A), which can be any constant DC plane that does not have an AC component.
  • Further shown in FIG. 1A, respective ends of wirebond 110 a are situated on bond pads 104 a and 104 b and respective ends of wirebond 110 b are situated on bond pads 104 c and 104 d. Thus, wirebond 110 a forms a loop that extends between bond pads 104 a and 104 b and wirebond 110 b forms a loop that extends between bond pads 104 c and 104 d. Wirebonds 110 a and 110 b can comprise gold or other suitable metal, for example. The respective ends of wirebond 110 a can be attached to bond pads 104 a and 104 b and the respective ends of wirebond 110 b can be attached to bond pads 104 c and 104 d by utilizing a suitable bonding process, for example. Wirebonds 110 a and 110 b form a portion of wirebond cage 106, which extends along the perimeter of the substrate (not shown in FIG. 1A).
  • Also shown in FIG. 1A, conductive layer 108 is situated on an overmold (not shown in FIG. 1A). Conductive layer 108 is also situated over component 102, bond pads 104 a through 104 d, wirebonds 110 a and 110 b, and the substrate (not shown in FIG. 1A). In the present embodiment, conductive layer 108 can comprise a conductive coating, such as a conductive ink, which can include copper, silver, or other conductive metals. In another embodiment, conductive layer 108 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 108 is connected to a middle portion of each of the wirebonds (e.g. wirebonds 110 a and 110 b) in wirebond cage 106. Conductive layer 108 and wirebonds 110 a and 110 b will be further discussed below in relation to FIG. 1B.
  • Referring now to FIG. 1B, a cross-sectional view is shown of overmolded semiconductor package 100 in FIG. 1A along line 1B-1B in FIG. 1A. In particular, component 102, bond pads 104 a through 104 d, wirebond cage 106, conductive layer 108, and wirebonds 110 a and 110 b correspond to the same elements in FIG. 1A and FIG. 1B. As shown in FIG. 1B, component 102 and bond pads 104 a through 104 d are situated on substrate 114, which can comprise a ceramic material, a laminate material, or other suitable type of material. Although not shown in FIG. 1B, substrate 114 can include a patterned metal layer on top and bottom substrate surfaces and vias, for example.
  • Also shown in FIG. 1B, the respective ends of wirebond 110 a are situated on bond pads 104 a and 104 b and middle portion 111 of wirebond 110 a is in contact with conductive layer 108. Further shown in FIG. 1B, the respective ends of wirebond 110 b are situated on bond pads 104 c and 104 d and middle portion 113 of wirebond 110 b is in contact with conductive layer 108. Also shown in FIG. 1B, the ends of each wirebond (e.g. wirebonds 110 a and 110 b) are separated by wirebond loop width 120 and adjacent wirebonds (e.g. wirebonds 110 a and 110 b) are separated by wirebond spacing 122. In the embodiment in FIGS. 1A and 1B, wirebond loop width 120 can be different than wirebond spacing 122. In one embodiment, wirebond loop width 120 can be substantially equal to wirebond spacing 122. Wirebond loop width 120 and wirebond spacing 122 can each range in value from microns to millimeters, for example. In the embodiment in FIGS. 1A and 1B, wirebond loop width 120 and wirebond spacing 122 can be selected to achieve EMI shielding for a particular frequency or a particular range of frequencies.
  • Further shown in FIG. 1B, overmold 116 is situated over component 102, bond pads 104 a through 104 d, and substrate 114 and encapsulates wirebond cage 106, which includes wirebonds 110 a and 110 b. Overmold 116 can comprise epoxy or other suitable molding compound and can be formed in a molding process in a manner known in the art. Also shown in FIG. 1B, conductive layer 108 is situated on top surface 118 of overmold 116 and situated over component 102, bond pads 104 a through 104 d and substrate 114. Conductive layer 108 is also situated over and in contact with wirebonds 110 a and 110 b. Conductive layer 108 has thickness 124, which can be between 25.0 microns and 50.0 microns, for example. In other embodiments, thickness 124 can be between 5.0 microns and 100.0 microns. Conductive layer 108 has height 126, which refers to the distance between the top surface of substrate 114 and top surface 118 of overmold 116. Height 126 can be approximately 1.0 mm, for example. However, height 126 may also be greater or less than 1.0 mm.
  • In overmolded semiconductor package 100, conductive layer 108 and wirebond cage 106, which are electrically connected together, form an EMI shield for component 102. The EMI shield can be formed during formation of overmolded semiconductor package 100 by bonding the ends of wirebonds to respective bond pads, which can be formed on the top surface of substrate 114. The ends of wirebond 110 a can be bonded to respective bond pads 104 a and 104 b, for example. Overmold 116 can then be formed by utilizing a mold compound, such as epoxy, in a molding process as known in the art to cover component 102, the bond pads (e.g. bond pads 104 a through 104 d), and the top surface of substrate 114 and to encapsulate the wirebonds (e.g. wirebonds 110 a and 110 b) that form wirebond cage 106.
  • Overmold 116 is desirably formed such that the center portion of each wirebond (e.g. center portions 111 and 113 of respective wirebonds 110 a and 110 b) in wirebond cage 106 is exposed above top surface 118 of overmold 116. However, overmold 116 may inadvertently cover the center portions of the wirebonds in wirebond cage 106. In such case, the covering portion of overmold 116 can be removed from the center portions of the wirebonds by utilizing a laser abrasion process, a mechanical milling process, a diamond polish process, or other suitable process. Conductive layer 108 can then be formed by utilizing a screen printing process, spraying process, electroplating process, thermal spray deposition process, or other suitable process to apply a layer of conductive ink on top surface 118 of overmold 116 and on the exposed center portions of the wirebonds in wirebond cage 106. In an embodiment in which conductive layer 108 comprises a layer of metal, the layer of metal can be deposited on top surface 118 of overmold 116 and on the exposed center portions of the wirebonds by utilizing a chemical vapor deposition (CVD) process or other suitable deposition processes.
  • In the embodiment in FIGS. 1A and 1B, the invention's overmolded package includes conductive layer 108, which provides EMI shielding over component 102, and wirebond cage 106, which provides EMI shielding around component 102. Thus, in the embodiment in FIGS. 1A and 1B, the invention utilizes a conductive layer and a wirebond cage to achieve an effective EMI shield for an overmolded package. For example, in the embodiment in FIGS. 1A and 1B, the invention can provide an EMI shield between a component, such as an active device, inside the overmolded package and the environment outside of the package.
  • Also, by forming an EMI shield that includes a wirebond cage, which includes multiple wirebonds, and a conductive layer, which is formed over an overmold, the invention advantageously achieves an EMI shield having a low manufacturing cost compared to a conventional prefabricated metal shield. Additionally, the conductive layer in the invention's EMI shield is significantly thinner than metal utilized to form the conventional prefabricated metal shield. As a result, the invention's EMI shield results in a thinner overmolded package compared to an overmolded package that includes a conventional prefabricated metal shield.
  • Furthermore, by utilizing wirebonds to form an EMI shield, the invention provides an EMI shield having a flexible design that can more easily accommodate variations in package size and has increased scalability compared to a conventional prefabricated metal shield. Moreover, since wirebonds are significantly thinner than the walls of the conventional prefabricated metal shield, the invention's EMI shield consumes less space in the overmolded package compared to the conventional prefabricated metal shield.
  • FIG. 2A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 2A that are apparent to a person of ordinary skill in the art. Overmolded semiconductor package 200, which is also referred to as an “overmolded package” in the present application, includes components 202 and 203, bond pads 204 a, 204 b, 204 c, and 204 d (hereinafter “bond pads 204 a through 204 d”), bond pads 205 a, 205 b, 205 c, and 205 d (hereinafter “bond pads 205 a through 205 d”), wirebond cage 206, and conductive layer 208. Wirebond cage 206 includes wirebond cage section 207, which includes wirebonds 210 a and 210 b, and wirebond cage section 209, which includes wirebonds 215 a and 215 b. It is noted that only bond pads 204 a through 204 d and 205 a through 205 d and wirebonds 210 a, 210 b, 215 a, and 215 b are discussed in detail herein to preserve brevity.
  • As shown in FIG. 2A, components 202 and 203 are situated on a substrate (not shown in FIG. 2A). In the embodiment in FIG. 2A, components 202 and 203 can each be an active device, such as a semiconductor die, which can include RF circuitry, for example. In one embodiment, component 202 can be a passive device, such as an inductor, and component 203 can be an active device, such as a semiconductor die. In another embodiment, components 202 and 203 can each be a passive device. Also shown in FIG. 2A, bond pads 204 a through 204 d and 205 a through 205 d are situated on the substrate (not shown in FIG. 2A) and are substantially similar in composition and formation to bond pads 104 a through 104 d in FIGS. 1A and 1B. Bond pads 204 a through 204 d and 205 a through 205 d can be connected to a reference potential (not shown in FIG. 2A), which can be any constant DC plane that does not have an AC component.
  • Further shown in FIG. 2A, respective ends of wirebond 210 a are situated on bond pads 204 a and 204 b and respective ends of wirebond 210 b are situated on bond pads 204 c and 204 d. Wirebonds 210 a and 210 b are substantially similar in composition and formation to wirebonds 110 a and 110 b in FIGS. 1A and 1B. Also shown in FIG. 2A, respective ends of wirebond 215 a are situated on bond pads 205 a and 205 b and respective ends of wirebond 215 b are situated on bond pads 205 c and 205 d. Wirebonds 215 a and 215 b are also substantially similar in composition and formation to wirebonds 110 a and 110 b in FIGS. 1A and 1B. Wirebonds 210 a and 210 b form a portion of wirebond cage section 207, which extends along the perimeter of the substrate (not shown in FIG. 2A), and wirebonds 215 a and 215 b form a portion of wirebond cage section 209, which is situated between components 202 and 203.
  • Further shown in FIG. 2A, in wirebond cage section 207, the ends of each wirebond (e.g. wirebond 210 a) are separated by wirebond loop width 220 and adjacent wirebonds (e.g. wirebonds 210 a and 210 b) are separated by wirebond spacing 222. In wirebond cage section 209, the ends of each wirebond (e.g. wirebonds 215 a) are separated by wirebond loop width 221 and adjacent wirebonds (e.g. wirebonds 215 a and 215 b) are separated by wirebond spacing 223. In the embodiment in FIG. 2A, wirebond loop width 220 can be different than wirebond spacing 222 and wirebond loop width 221 can be different than wirebond spacing 223. Also, wirebond loop width 220 can be different than wirebond loop width 221 and wirebond spacing 222 can be different than wirebond spacing 223. In one embodiment, wirebond loop width 220 can be substantially equal to equal to wirebond spacing 222 and wirebond loop width 221 can be substantially equal to wirebond spacing 223. Wirebond loop widths 220 and 221 and wirebond spacings 222 and 223 can each range in value from microns to millimeters, for example. The value of each of wirebond loop widths 220 and 221 and wirebond spacings 222 and 223 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • Also shown in FIG. 2A, conductive layer 208 is situated on an overmold (not shown in FIG. 2A) and also situated over components 202 and 203, bond pads 204 a through 204 d and 205 a through 205 d, wirebonds 210 a, 210 b, 215 a, and 215 b, and the substrate (not shown in FIG. 2A). Conductive layer 208 is substantially similar in composition and formation to conductive layer 108 in FIGS. 1A and 1B. In the embodiment in FIG. 2A, conductive layer 208 can comprise a conductive coating, such as a conductive ink. In another embodiment, conductive layer 208 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 208 is connected to a middle portion of each of the wirebonds (e.g. wirebonds 210 a and 210 b) in wirebond cage section 207 and connected to a middle portion of each of the wirebonds (e.g. wirebonds 215 a and 215 b) in wirebond cage section 209. Conductive layer 208 and wirebonds 210 a and 210 b will be further discussed below in relation to FIG. 2B.
  • Referring now to FIG. 2B, a cross-sectional view is shown of overmolded semiconductor package 200 in FIG. 2A along line 2B-2B in FIG. 2A. In particular, components 202 and 203, bond pads 204 a through 204 d, wirebond cage 206, wirebond cage section 207, conductive layer 208, and wirebonds 210 a and 210 b correspond to the same elements in FIG. 2A and FIG. 2B. As shown in FIG. 2B, components 202 and 203 and bond pads 204 a through 204 d are situated on substrate 214, which is substantially similar in composition to substrate 114 in FIGS. 1A and 1B. Also shown in FIG. 2B, the respective ends of wirebond 210 a are situated on bond pads 204 a and 204 b and middle portion 211 of wirebond 210 a is in contact with conductive layer 208. Further shown in FIG. 2B, the respective ends of wirebond 210 b are situated on bond pads 204 c and 204 d and middle portion 213 of wirebond 210 b is in contact with conductive layer 208.
  • Further shown in FIG. 2B, overmold 216 is situated over components 202 and 203, bond pads 204 a through 204 d, and substrate 214 and encapsulates wirebond cage 206, which includes wirebonds 210 a and 210 b. Overmold 216 is substantially similar in composition and formation to overmold 116 in FIG. 1B. Also shown in FIG. 2B, conductive layer 208 is situated on top surface 218 of overmold 216 and situated over components 202 and 203, bond pads 204 a through 204 d and substrate 214. Conductive layer 208 is also situated over and in contact with wirebonds 210 a and 210 b. Conductive layer 208 is substantially similar in composition, thickness, and formation to conductive layer 108 in FIGS. 1A and 1B.
  • In overmolded semiconductor package 200, conductive layer 208 and wirebond cage 206, which are electrically connected together, form an EMI shield for components 202 and 203. In the embodiment in FIGS. 2A and 2B, the EMI shield, which includes conductive layer 208 and wirebond cage 206, can be formed in a similar manner as the EMI shield in the embodiment in FIGS. 1A and 1B.
  • In the embodiment in FIGS. 2A and 2B, the invention's overmolded package includes conductive layer 208, which provides EMI shielding over components 202 and 203, wirebond cage section 207, which provides EMI shielding around components 202 and 203, and wirebond cage section 209, which provides EMI shielding between components 202 and 203. Thus, in the embodiment in FIGS. 2A and 2B, the invention utilizes a conductive layer and wirebond cage sections to advantageously achieve an effective EMI shield between two components inside an overmolded package and the environment outside of the package and an effective EMI shield between the two components inside the package. The embodiment in FIGS. 2A and 2B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B.
  • FIG. 3A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 3A that are apparent to a person of ordinary skill in the art. Overmolded semiconductor package 300, which is also referred to as an “overmolded package” in the present application, includes component 302, bond pads 304 a, 304 b, 304 c, 304 d, and 304 e (hereinafter “bond pads 304 a through 304 e”), wirebond cage 306, and conductive layer 308. Wirebond cage 304 includes wirebonds 310 a, 310 b, 310 c, 310 d, and 310 e (hereinafter “wirebonds 310 a through 310 e”). It is noted that only bond pads 304 a through 304 e and wirebonds 310 a through 310 e are discussed in detail herein to preserve brevity.
  • As shown in FIG. 3A, component 302 is situated on a substrate (not shown in FIG. 3A). Component 302 can be an active device, such as a semiconductor die with RF circuitry. In one embodiment, component 302 can be a passive device, such as an inductor. Also shown in FIG. 3A, bond pads 304 a through 304 e are situated on and along the perimeter of the substrate (not shown in FIG. 3A). Bond pads 304 a through 304 e can comprise a metal such as copper or aluminum and can be formed, for example, by depositing and patterning a layer of metal, such as copper or aluminum, and plating the layer of metal with gold. Bond pads 304 a through 304 e can be connected to a reference potential (not shown in FIG. 3A), which can be any constant DC plane that does not have an AC component.
  • Further shown in FIG. 3A, wirebonds 310 a through 310 e are situated on respective bond pads 304 a through 304 e and form wirebond cage 306, which surrounds component 302. Wirebonds 310 a through 310 e can comprise gold or other suitable metal and can be connected to respective bond pads 304 a through 304 e by using a bonding process, for example. Also shown in FIG. 3A, wirebond spacing 312 refers to the distance between adjacent wirebonds (e.g. the distance between wirebonds 310 a and 310 b). Wirebond spacing 312 can range in value from microns to millimeters. In one embodiment, wirebond spacing 312 can be approximately 2.5 mm. The value of wirebond spacing 312 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • Further shown in FIG. 3A, conductive layer 308 is situated on overmold (not shown in FIG. 3A). Conductive layer 308 is also situated over component 302, bond pads 304 a through 304 e, wirebonds 310 a through 310 e, and the substrate (not shown in FIG. 3A). Conductive layer 308 can comprise a conductive coating, such as a conductive ink, which can include copper, silver, or other conductive metals. In another embodiment, conductive layer 308 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 308 is connected to an end of each of the wirebonds (e.g. wirebonds 310 a through 310 e) in wirebond cage 306.
  • Referring now to FIG. 3B, a cross-sectional view is shown of overmolded semiconductor package 300 in FIG. 3A along line 3B-3B in FIG. 3A. In particular, component 302, bond pads 304 a and 304 b, wirebond cage 306, conductive layer 308, wirebonds 310 a and 310 b, and wirebond spacing 312 correspond to the same elements in FIG. 3A and FIG. 3B. As shown in FIG. 3B, component 302 and bond pads 304 a and 304 b are situated on substrate 314, which can comprise a ceramic material, a laminate material, or other suitable type of material. Although not shown in FIG. 3B, substrate 314 can include a patterned metal layer on top and bottom substrate surfaces and vias, for example.
  • Also shown in FIG. 3B, overmold 316 is situated over component 302, bond pads 304 a and 304 b, and substrate 314 and encapsulates wirebond cage 306, which includes wirebonds 310 a and 310 b. Overmold 316 is substantially similar in composition and formation as overmold 116 in FIG. 1B. Further shown in FIG. 3B, conductive layer 308 is situated on top surface 318 of overmold 316 and situated over component 302, bond pads 304 a and 304 b and substrate 314. Conductive layer 308 is also situated over and in contact with wirebonds 310 a and 310 b of wirebond cage 306. Conductive layer 308 has thickness 320 and height 322, which are substantially similar to thickness 124 and height 126 in FIG. 1B, respectively.
  • Further shown in FIG. 3B, wirebonds 310 a and 310 b of wirebond cage 306 are situated between respective bond pads 304 a and 304 b and conductive layer 308 and also situated in (i.e. encapsulated by) overmold 316. In particular, one end of each of wirebonds 310 a and 310 b is bonded to respective bond pads 304 a and 304 b and the other end of each of wirebonds 310 a and 310 b is in contact with conductive layer 308.
  • In overmolded semiconductor package 300, conductive layer 308 and wirebond cage 306, which are electrically connected together, form an EMI shield for component 302. The EMI shield can be formed during formation of overmolded semiconductor package 300 by bonding one end of each of the wirebonds (e.g. wirebond 310 a) that form wirebond cage 306 to a bond pad (e.g. bond pad 304 a) by using a suitable bonding process as is know in the art. Overmold 316 can then be formed by utilizing a mold compound, such as epoxy, in a molding process as known in the art to cover component 302, the bond pads ( e.g. bond pads 304 a and 304 b), and the top surface of substrate 314 and to encapsulate the wirebonds (e.g. wirebonds 310 a and 310 b) that form wirebond cage 306.
  • Overmold 316 is desirably formed such that the unattached ends of the wirebonds (e.g. wirebonds 310 a and 310 b) in wirebond cage 306 are exposed above top surface 318 of overmold 316. However, if overmold 316 inadvertently covers the unattached ends of the wirebonds in wirebond cage 306, the unattached wirebond ends can be exposed by utilizing a laser abrasion process, a mechanical milling process, a diamond polish process, or other suitable process to remove the covering portion of overmold 316. Conductive layer 308 can then be formed by utilizing a screen printing process, spraying process, electroplating process, or thermal spray deposition process to apply a layer of conductive ink on top surface 318 of overmold 316 and on the exposed ends of the wirebonds in wirebond cage 306. In an embodiment in which conductive layer 308 comprises a layer of metal, the layer of metal can be deposited on top surface 318 of overmold 316 and on the exposed wirebond ends by utilizing a CVD process or other suitable deposition processes.
  • In the embodiment of the invention in FIGS. 3A and 3B, the invention's overmolded package includes conductive layer 308, which provides EMI shielding over component 302, and wirebond cage 306, which provides EMI shielding around component 302. Thus, in the embodiment in FIGS. 3A and 3B, the invention utilizes a conductive layer and a wirebond cage to achieve an effective EMI shield between a component inside an overmolded package and the environment outside of the package. The embodiment in FIGS. 3A and 3B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B.
  • FIG. 4A shows a top view of an exemplary overmolded semiconductor package in accordance to one embodiment of the present invention. Certain details and features have been left out of FIG. 4A that are apparent to a person of ordinary skill in the art. Overmolded semiconductor package 400, which is also referred to as an “overmolded package” in the present application, includes components 402 and 403, bond pads 404 a, 404 b, 405 a, and 405 b, wirebond cage 406, and conductive layer 408. Wirebond cage 406 includes wirebond cage section 407, which includes wirebonds 410 a and 410 b, and wirebond cage section 409, which includes wirebonds 415 a and 415 b. It is noted that only bond pads 404 a, 404 b, 405 a, and 405 b and wirebonds 410 a, 410 b, 415 a, and 415 b are discussed in detail herein to preserve brevity.
  • As shown in FIG. 4A, components 402 and 403 are situated on a substrate (not shown in FIG. 4A). In the embodiment in FIG. 4A, components 402 and 403 can each be an active device, such as a semiconductor die, which can include RF circuitry, for example. In one embodiment, component 402 can be a passive device, such as an inductor, and component 403 can be an active device, such as a semiconductor die. In another embodiment, components 402 and 403 can each be a passive device. Also shown in FIG. 4A, bond pads 404 a, 404 b, 405 a, and 405 b are situated on the substrate (not shown in FIG. 4A) and are substantially similar in composition and formation to bond pads 304 a through 3043 in FIG. 3A. Bond pads 404 a, 404 b, 405 a, and 405 b can be connected to a reference potential (not shown in FIG. 4A), which can be any constant DC plane that does not have an AC component.
  • Further shown in FIG. 4A, respective ends of wirebonds 410 a and 410 b are situated on bond pads 404 a and 404 b and respective ends of wirebonds 415 a and 415 b are situated on bond pads 405 a and 405 b. Wirebonds 410 a, 410 b, 415 a, and 415 b are substantially similar in composition and formation to wirebonds 310 a through 310 e in FIG. 3A. Wirebonds 410 a and 410 b form a portion of wirebond cage section 407, which extends along the perimeter of the substrate (not shown in FIG. 4A), and wirebonds 415 a and 415 b form a portion of wirebond cage section 409, which is situated between components 402 and 403.
  • Also shown in FIG. 4A, in wirebond cage section 407, adjacent wirebonds (e.g. wirebonds 410 a and 410 b) are separated by wirebond spacing 412. In wirebond cage section 409, adjacent wirebonds (e.g. wirebonds 415 a and 415 b) are separated by wirebond spacing 413. In the embodiment in FIG. 4A, wirebond spacing 412 can be different than wirebond spacing 413. In one embodiment, wirebond spacing 412 can be substantially equal to wirebond spacing 413. Wirebond spacing 412 and wirebond spacing 413 can range in value from microns to millimeters, for example. The value of each of wirebond spacings 412 and 413 can be selected to provide EMI shielding for a particular frequency or range of frequencies.
  • Also shown in FIG. 4A, conductive layer 408 is situated on an overmold (not shown in FIG. 4A) and also situated over components 402 and 403, bond pads 404 a, 404 b, 405 a, and 405 b, wirebonds 410 a, 410 b, 415 a, and 415 b, and the substrate (not shown in FIG. 4A). Conductive layer 408 is substantially similar in composition and formation to conductive layer 308 in FIGS. 3A and 3B. In the embodiment in FIG. 4A, conductive layer 408 can comprise a conductive coating, such as a conductive ink. In another embodiment, conductive layer 408 can comprise a layer of copper, aluminum, or other suitable metal. Conductive layer 408 is connected to an end of each of the wirebonds (e.g. wirebonds 410 a and 410 b) in wirebond cage section 407 and connected to an end of each of the wirebonds (e.g. wirebonds 415 a and 415 b) in wirebond cage section 409. Conductive layer 408 and wirebonds 410 a and 410 b will be further discussed below in relation to FIG. 4B.
  • Referring now to FIG. 4B, a cross-sectional view is shown of overmolded semiconductor package 400 in FIG. 4A along line 4B-4B in FIG. 4A. In particular, components 402 and 403, bond pads 404 a and 404 b, wirebond cage 406, wirebond cage section 407, conductive layer 408, wirebonds 410 a and 410 b, and wirebond spacing 412 correspond to the same elements in FIG. 4A and FIG. 4B. As shown in FIG. 4B, components 402 and 403 and bond pads 404 a and 404 b are situated on substrate 414, which is substantially similar in composition to substrate 314 in FIGS. 3A and 3B. Also shown in FIG. 4B, wirebonds 410 a and 410 b are situated between respective bond pads 404 a and 404 b and conductive layer 408.
  • Further shown in FIG. 4B, overmold 416 is situated over components 402 and 403, bond pads 404 a and 404 b, and substrate 414 and encapsulates wirebond cage 406, which includes wirebonds 410 a and 410 b. Overmold 416 is substantially similar in composition and formation to overmold 316 in FIG. 3B. Also shown in FIG. 4B, conductive layer 408 is situated on top surface 418 of overmold 416 and situated over components 402 and 403, bond pads 404 a and 404 b and substrate 414. Conductive layer 408 is also situated over and in contact with wirebonds 410 a and 410 b and is substantially similar in composition, thickness, and formation to conductive layer 308 in FIGS. 3A and 3B.
  • In overmolded semiconductor package 400, conductive layer 408 and wirebond cage 406, which are electrically connected together, form an EMI shield for components 402 and 403. In the embodiment in FIGS. 4A and 4B, the EMI shield, which includes conductive layer 408 and wirebond cage 406, can be formed in a similar manner as the EMI shield in the embodiment in FIGS. 3A and 3B.
  • In the embodiment in FIGS. 4A and 4B, the invention's overmolded package includes conductive layer 408, which provides EMI shielding over components 402 and 403, wirebond cage section 407, which provides EMI shielding around components 402 and 403, and wirebond cage section 409, which provides EMI shielding between components 402 and 403. Thus, in the embodiment in FIGS. 4A and 4B, the invention utilizes a conductive layer and wirebond cage sections to advantageously achieve an effective EMI shield between two components inside an overmolded package and the environment outside of the package and an effective EMI shield between the two components inside the package. The embodiment in FIGS. 4A and 4B also provides similar advantages as discussed above for the embodiment in FIGS. 1A and 1B.
  • FIG. 5 shows a flowchart illustrating an exemplary method according to one embodiment of the present invention. Certain details and features have been left out of flowchart 500 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. At step 502, bond pads are formed on a substrate that includes one or more components and wirebonds are attached to the bond pads to form a wirebond cage. For example, bonds pads 104 a through 104 d in FIG. 1B can be formed on substrate 114, which includes component 102, by depositing and patterning a layer of copper, aluminum, or other suitable metal. For example, wirebonds 110 a and 110 b can be attached to respective bond pads 104 a and 104 b and bond pads 104 c and 104 d by using a suitable bonding process to form wirebond cage 106.
  • At step 504, an overmold is formed over one or more components, the wirebond cage, the bond pads, and the substrate. For example, overmold 116 in FIG. 1B, which can comprise an epoxy molding compound, can be formed over component 102, wirebond cage 106, which includes wirebonds 110 a and 110 b, bond pads 104 a through 104 d, and substrate 114 in a molding process in a manner known in the art. At step 506, a conductive layer is formed on a top surface of the overmold such that the conductive layer is in contact with the wirebond cage. For example, overmold 116 can be formed such that middle portions 111 and 113 of respective wirebonds 110 a and 110 b are exposed. Conductive layer 108 in FIG. 1B can then be formed by applying a conductive ink over exposed middle portions 111 and 113 of respective wirebonds 110 a and 110 b and on top surface 118 of overmold 116. The conductive ink can be applied by utilizing a spraying process, electroplating process, thermal spray deposition process, or other suitable process, for example.
  • As a result of the process in flowchart 500, an EMI shield, which includes the wirebond cage and the conductive layer, is formed in an overmolded package. For example, an EMI shield, which includes wirebond cage 106 and conductive layer 108, which are electrically connected together, is formed in overmolded semiconductor package 100 in FIGS. 1A and 1B.
  • Thus, as discussed above, in the embodiments in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B, the invention utilizes a conductive layer and a wirebond cage to advantageously achieve an effective EMI shield between one or more components inside an overmolded package and the environment outside of the package. Additionally, in the embodiments in FIGS. 2A, 2B, 4A, and 4B, the invention utilizes a wirebond cage section to achieve an effective EMI shield between two components inside the package. Furthermore, in the embodiments in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B, the invention advantageously achieves an effective EMI shield for an overmolded package that has a flexible design, is cost effective, and does not substantially increase the size of the overmolded package.
  • From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
  • Thus, an overmolded semiconductor package with wirebond cage for EMI shielding has been described.

Claims (21)

What is claimed is:
1. A packaged radio-frequency (RF) module comprising:
a packaging substrate having a reference potential layer;
an RF component positioned over the packaging substrate;
an overmold implemented over the packaging substrate to substantially encapsulate the RF component, the overmold including an upper surface;
a conductive layer implemented on the upper surface of the overmold; and
a plurality of wirebonds implemented on the packaging substrate, each of the plurality of wirebonds having a first end electrically connected to the reference potential layer and a second end electrically connected to the conductive layer, the plurality of wirebonds arranged in a pattern relative to the RF component to yield electromagnetic shielding with respect to the RF component.
2. The packaged RF module of claim 1 wherein a combination of the conductive layer, the reference potential layer, and the plurality of wirebonds results in electromagnetic shielding with respect to a volume that covers the RF component.
3. The packaged RF module of claim 2 wherein the pattern of the wirebonds defines a boundary of the volume.
4. The packaged RF module of claim 1 wherein the pattern of the wirebonds includes a segment that separate a region associated with the RF component and another region on the packaging substrate, such that the pattern of the wirebonds provides the electromagnetic shielding between the region and the other region.
5. The packaged RF module of claim 1 wherein the pattern of the wirebonds includes a perimeter around the RF component, such that the pattern of the wirebonds provides the electromagnetic shielding between a region within the perimeter and a region outside of the perimeter.
6. The packaged RF module of claim 5 wherein the perimeter is substantially at or near the perimeter of the packaging substrate.
7. The packaged RF module of claim 1 wherein the packaging substrate includes a laminate substrate or a ceramic substrate.
8. The packaged RF module of claim 1 wherein the RF component is positioned directly on the packaging substrate.
9. The packaged RF module of claim 1 wherein the RF component includes a semiconductor die having an RF circuitry.
10. The packaged RF module of claim 1 wherein the RF component includes a passive device.
11. The packaged RF module of claim 1 further comprising a plurality of bond pads implemented on the packaging substrate and electrically connected to the reference potential layer, such that the first end of each of one or more of the plurality of wirebonds is attached to a corresponding bond pad.
12. The packaged RF module of claim 11 wherein each wirebond has associated with it a corresponding bond pad.
13. The packaged RF module of claim 11 wherein each wirebond extends generally upward between the corresponding bond pad and the conductive layer.
14. The packaged RF module of claim 13 wherein each wirebond is substantially straight.
15. The packaged RF module of claim 1 wherein a spacing between an adjacent pair of wirebonds is selected to provide the electromagnetic shielding for a particular frequency or range of frequencies.
16. The packaged RF module of claim 15 wherein the spacing is substantially uniform among the adjacent pairs of wirebonds.
17. The packaged RF module of claim 1 wherein the conductive layer includes a sprayed-on conductive layer.
18. A radio-frequency (RF) device comprising:
a circuit board; and
a packaged device mounted on the circuit board, the packaged device including a packaging substrate having a reference potential layer, and an RF component positioned over the packaging substrate, the packaged device further including an overmold implemented over the packaging substrate to substantially encapsulate the RF component, the overmold including an upper surface, the packaged device further including a conductive layer implemented on the upper surface of the overmold, the packaged device further including a plurality of wirebonds implemented on the packaging substrate, each of the plurality of wirebonds having a first end electrically connected to the reference potential layer and a second end electrically connected to the conductive layer, the plurality of wirebonds arranged in a pattern relative to the RF component to yield electromagnetic shielding with respect to the RF component.
19. The RF device of claim 17 wherein the RF device is a cellular phone.
20. The RF device of claim 17 wherein the electromagnetic shielding includes either or both of shielding between a region on the packaging substrate associated with the RF component and another region on the packaging substrate, and shielding between a region on the packaging substrate associated with the RF component and another region exterior to the packaged device.
21. A shielded radio-frequency (RF) module comprising:
a packaging substrate having a ground;
a conductive layer implemented over a region on the packaging substrate; and
a plurality of wirebonds configured to provide an electrical connection between the conductive layer and the ground, the plurality of wirebonds arranged in a pattern to yield electromagnetic shielding with respect to the region.
US14/720,872 2004-03-04 2015-05-25 Packaged radio-frequency module having wirebond shielding Abandoned US20150255402A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/720,872 US20150255402A1 (en) 2004-03-04 2015-05-25 Packaged radio-frequency module having wirebond shielding

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/793,618 US7198987B1 (en) 2004-03-04 2004-03-04 Overmolded semiconductor package with an integrated EMI and RFI shield
US11/499,285 US8399972B2 (en) 2004-03-04 2006-08-04 Overmolded semiconductor package with a wirebond cage for EMI shielding
US12/970,705 US8071431B2 (en) 2004-03-04 2010-12-16 Overmolded semiconductor package with a wirebond cage for EMI shielding
US13/311,493 US9041168B2 (en) 2004-03-04 2011-12-05 Overmolded semiconductor package with wirebonds for electromagnetic shielding
US14/720,872 US20150255402A1 (en) 2004-03-04 2015-05-25 Packaged radio-frequency module having wirebond shielding

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/311,493 Continuation US9041168B2 (en) 2004-03-04 2011-12-05 Overmolded semiconductor package with wirebonds for electromagnetic shielding

Publications (1)

Publication Number Publication Date
US20150255402A1 true US20150255402A1 (en) 2015-09-10

Family

ID=39033454

Family Applications (6)

Application Number Title Priority Date Filing Date
US11/499,285 Active 2025-12-27 US8399972B2 (en) 2004-03-04 2006-08-04 Overmolded semiconductor package with a wirebond cage for EMI shielding
US12/970,705 Expired - Lifetime US8071431B2 (en) 2004-03-04 2010-12-16 Overmolded semiconductor package with a wirebond cage for EMI shielding
US13/311,436 Active 2025-01-25 US9054115B2 (en) 2004-03-04 2011-12-05 Methods for fabricating an overmolded semiconductor package with wirebonds for electromagnetic shielding
US13/311,493 Active 2025-02-19 US9041168B2 (en) 2004-03-04 2011-12-05 Overmolded semiconductor package with wirebonds for electromagnetic shielding
US14/720,873 Abandoned US20150255403A1 (en) 2004-03-04 2015-05-25 Methods related to fabrication of shielded radio-frequency module
US14/720,872 Abandoned US20150255402A1 (en) 2004-03-04 2015-05-25 Packaged radio-frequency module having wirebond shielding

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US11/499,285 Active 2025-12-27 US8399972B2 (en) 2004-03-04 2006-08-04 Overmolded semiconductor package with a wirebond cage for EMI shielding
US12/970,705 Expired - Lifetime US8071431B2 (en) 2004-03-04 2010-12-16 Overmolded semiconductor package with a wirebond cage for EMI shielding
US13/311,436 Active 2025-01-25 US9054115B2 (en) 2004-03-04 2011-12-05 Methods for fabricating an overmolded semiconductor package with wirebonds for electromagnetic shielding
US13/311,493 Active 2025-02-19 US9041168B2 (en) 2004-03-04 2011-12-05 Overmolded semiconductor package with wirebonds for electromagnetic shielding
US14/720,873 Abandoned US20150255403A1 (en) 2004-03-04 2015-05-25 Methods related to fabrication of shielded radio-frequency module

Country Status (2)

Country Link
US (6) US8399972B2 (en)
WO (1) WO2008018959A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170118877A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with bond wires to provide internal shielding between electronic components
US10134682B2 (en) 2015-10-22 2018-11-20 Avago Technologies International Sales Pte. Limited Circuit package with segmented external shield to provide internal shielding between electronic components
US10163808B2 (en) 2015-10-22 2018-12-25 Avago Technologies International Sales Pte. Limited Module with embedded side shield structures and method of fabricating the same
US11239178B2 (en) * 2018-11-29 2022-02-01 Advanced Semiconductor Engineering, Inc. Semiconductor package structures and methods of manufacturing the same

Families Citing this family (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US20080112151A1 (en) 2004-03-04 2008-05-15 Skyworks Solutions, Inc. Overmolded electronic module with an integrated electromagnetic shield using SMT shield wall components
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8373264B2 (en) 2008-07-31 2013-02-12 Skyworks Solutions, Inc. Semiconductor package with integrated interference shielding and method of manufacture thereof
KR101533866B1 (en) * 2008-07-31 2015-07-03 스카이워크스 솔루션즈, 인코포레이티드 Semiconductor package with integrated interference shielding and method of manufacture thereof
US8012868B1 (en) * 2008-12-15 2011-09-06 Amkor Technology Inc Semiconductor device having EMI shielding and method therefor
JP2012019091A (en) * 2010-07-08 2012-01-26 Sony Corp Module and portable terminal
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR20120026909A (en) * 2010-09-10 2012-03-20 삼성전자주식회사 Semiconductor package and method of fabricating the same
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8966747B2 (en) 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
US9402319B2 (en) 2011-05-11 2016-07-26 Vlt, Inc. Panel-molded electronic assemblies
US9071335B2 (en) * 2011-07-08 2015-06-30 Skyworks Solutions, Inc. Radio-frequency modules having tuned shielding-wirebonds
US9679869B2 (en) 2011-09-02 2017-06-13 Skyworks Solutions, Inc. Transmission line for high performance radio frequency applications
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
CN102364683A (en) * 2011-10-21 2012-02-29 华为终端有限公司 Packaging structure and method thereof, and electronic equipment
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
WO2013181280A2 (en) * 2012-05-31 2013-12-05 Skyworks Solutions , Inc. Semiconductor package having a metal paint layer
US20130323409A1 (en) * 2012-05-31 2013-12-05 Skyworks Solutions, Inc. Systems and methods for controlling electromagnetic interference for integrated circuit modules
US9754896B2 (en) * 2012-05-31 2017-09-05 Skyworks Solutions, Inc. Systems and methods for providing electromagnetic interference shielding for integrated circuit modules
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
EP3567629A3 (en) 2012-06-14 2020-01-22 Skyworks Solutions, Inc. Power amplifier modules including related systems, devices, and methods
KR101516930B1 (en) 2012-07-13 2015-05-04 스카이워크스 솔루션즈, 인코포레이티드 Racetrack design in radio frequency shielding applications
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9202747B2 (en) * 2012-09-28 2015-12-01 Skyworks Solutions, Inc. Segmented conductive top layer for radio frequency isolation
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
CN104066273A (en) * 2013-03-20 2014-09-24 深南电路有限公司 Package substrate and manufacturing method thereof, and substrate assembly
US9788466B2 (en) 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9736925B2 (en) 2014-01-31 2017-08-15 Stmicroelectronics S.R.L. Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9761537B2 (en) 2014-09-30 2017-09-12 Skyworks Solutions, Inc. Shielded radio-frequency module having reduced area
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9936580B1 (en) 2015-01-14 2018-04-03 Vlt, Inc. Method of forming an electrical connection to an electronic module
US9967984B1 (en) 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
CN106033755A (en) * 2015-03-17 2016-10-19 晟碟信息科技（上海）有限公司 Semiconductor device possessing electromagnetic interference shielding and substrate band
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
US9714879B2 (en) 2015-08-21 2017-07-25 Nxp Usa, Inc. Electrically conductive barriers for integrated circuits
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10903734B1 (en) 2016-04-05 2021-01-26 Vicor Corporation Delivering power to semiconductor loads
US10158357B1 (en) 2016-04-05 2018-12-18 Vlt, Inc. Method and apparatus for delivering power to semiconductors
US10785871B1 (en) 2018-12-12 2020-09-22 Vlt, Inc. Panel molded electronic assemblies with integral terminals
US11336167B1 (en) 2016-04-05 2022-05-17 Vicor Corporation Delivering power to semiconductor loads
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10134686B2 (en) * 2016-09-30 2018-11-20 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
US10271421B2 (en) 2016-09-30 2019-04-23 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) shielding between inductors of a radio frequency (RF) module
US10178757B2 (en) 2016-09-30 2019-01-08 Avago Technologies International Sales Pte. Limited Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
US10076023B2 (en) * 2016-09-30 2018-09-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages
US9953931B1 (en) 2016-10-25 2018-04-24 Advanced Semiconductor Engineering, Inc Semiconductor device package and a method of manufacturing the same
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US20180228016A1 (en) * 2017-02-09 2018-08-09 Qualcomm Incorporated Wire-bond cage in conformal shielding
US10497650B2 (en) 2017-04-13 2019-12-03 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
CN214254388U (en) * 2018-06-01 2021-09-21 株式会社村田制作所 High frequency module
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11038267B2 (en) * 2018-07-31 2021-06-15 Skyworks Solutions, Inc. Apparatus and methods for electromagnetic shielding using an outer cobalt layer
JP7103301B2 (en) * 2018-08-03 2022-07-20 株式会社村田製作所 module
JP7036087B2 (en) * 2018-08-03 2022-03-15 株式会社村田製作所 module
KR102279979B1 (en) * 2018-08-03 2021-07-21 가부시키가이샤 무라타 세이사쿠쇼 Module
US10615130B1 (en) 2018-11-29 2020-04-07 Nxp Usa, Inc. Devices and methods for isolating signals in semiconductor devices
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
JP6900947B2 (en) 2018-12-28 2021-07-14 株式会社村田製作所 High frequency module and communication equipment
US10879191B2 (en) 2019-01-07 2020-12-29 Qualcomm Incorporated Conformal shielding for solder ball array
US10892229B2 (en) 2019-04-05 2021-01-12 Nxp Usa, Inc. Media shield with EMI capability for pressure sensor
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
US11127645B2 (en) * 2019-06-19 2021-09-21 Nxp Usa, Inc. Grounding lids in integrated circuit devices
US11450618B2 (en) 2020-01-17 2022-09-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of compartment shielding using bond wires
CN113140539B (en) * 2020-01-17 2023-07-25 星科金朋私人有限公司 Semiconductor device and method of zone shielding using bond wires
JP7282048B2 (en) * 2020-02-12 2023-05-26 三菱電機株式会社 Power semiconductor device and manufacturing method thereof
TWI767243B (en) * 2020-05-29 2022-06-11 矽品精密工業股份有限公司 Electronic package
KR20220000087A (en) 2020-06-25 2022-01-03 삼성전기주식회사 Electronic device module
TWI798647B (en) * 2021-02-23 2023-04-11 華泰電子股份有限公司 Electronic package and method of manufacture thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020179321A1 (en) * 2001-05-30 2002-12-05 Ericsson Inc. Liquid dielectrick tuning of an integrated circuit
US20040262645A1 (en) * 2001-05-18 2004-12-30 Corporation For National Research Initiatives Radio frequency microelectromechanical systems (MEMS) devices on low-temperature co-fired ceramic (LTCC) substrates
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3721746A (en) * 1971-10-01 1973-03-20 Motorola Inc Shielding techniques for r.f. circuitry
US4151637A (en) * 1978-02-07 1979-05-01 Universal Instruments Corporation Dip component lead cut and clinch apparatus
US4296421A (en) 1978-10-26 1981-10-20 Canon Kabushiki Kaisha Ink jet recording device using thermal propulsion and mechanical pressure changes
US4241497A (en) * 1979-01-11 1980-12-30 The Singer Company P.C. Board lead trimming method
US4245385A (en) * 1979-07-09 1981-01-20 Universal Instruments Corporation Radial lead component insertion machine
US4447945A (en) * 1980-05-01 1984-05-15 Contact Systems, Inc. Cut and clinch mechanism for use in electrical component assembly apparatus
US4588998A (en) 1983-07-27 1986-05-13 Ricoh Company, Ltd. Ink jet head having curved ink
US4516140A (en) 1983-12-27 1985-05-07 At&T Teletype Corporation Print head actuator for an ink jet printer
US4732313A (en) * 1984-07-27 1988-03-22 Kabushiki Kaisha Toshiba Apparatus and method for manufacturing semiconductor device
GB8510621D0 (en) * 1985-04-26 1985-06-05 Pickering Electronics Ltd Potted electronic components
FR2598258B1 (en) * 1986-04-30 1988-10-07 Aix Les Bains Composants METHOD OF ENCAPSULATING INTEGRATED CIRCUITS.
US4897673A (en) 1989-02-28 1990-01-30 Juki Corporation Method for connecting nozzle tube of ink jet nozzle with piezoelectric element
JPH03165058A (en) * 1989-11-24 1991-07-17 Mitsubishi Electric Corp Semiconductor device
JPH0458596A (en) 1990-06-28 1992-02-25 Nippon Telegr & Teleph Corp <Ntt> Electromagnetic shield
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5166864A (en) * 1991-05-17 1992-11-24 Hughes Aircraft Company Protected circuit card assembly and process
US5205770A (en) * 1992-03-12 1993-04-27 Micron Technology, Inc. Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology
US5459501A (en) 1993-02-01 1995-10-17 At&T Global Information Solutions Company Solid-state ink-jet print head
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5428508A (en) * 1994-04-29 1995-06-27 Motorola, Inc. Method for providing electromagnetic shielding of an electrical circuit
JP3570447B2 (en) 1994-12-21 2004-09-29 セイコーエプソン株式会社 Laminated inkjet recording head, method of manufacturing the same, and recording apparatus
JPH08222885A (en) 1995-02-16 1996-08-30 Sumise Device:Kk Electromagnetic shielding film for package and its formation
JP3368451B2 (en) * 1995-03-17 2003-01-20 富士通株式会社 Circuit board manufacturing method and circuit inspection device
US5837251A (en) * 1995-09-13 1998-11-17 Fordham University Compositions and methods using complexes of heat shock proteins and antigenic molecules for the treatment and prevention of neoplastic diseases
US6242842B1 (en) * 1996-12-16 2001-06-05 Siemens Matsushita Components Gmbh & Co. Kg Electrical component, in particular saw component operating with surface acoustic waves, and a method for its production
EP1118467B1 (en) 1996-04-10 2006-01-25 Seiko Epson Corporation Ink jet recording head
SE511426C2 (en) * 1996-10-28 1999-09-27 Ericsson Telefon Ab L M Apparatus and method of shielding electronics
US6150193A (en) 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6566596B1 (en) * 1997-12-29 2003-05-20 Intel Corporation Magnetic and electric shielding of on-board devices
US6350951B1 (en) * 1997-12-29 2002-02-26 Intel Corporation Electric shielding of on-board devices
TW401724B (en) * 1998-01-27 2000-08-11 Hitachi Cable Wiring board, semiconductor, electronic device, and circuit board for electronic parts
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
AU2341900A (en) * 1998-09-03 2000-04-10 Lockheed Martin Corporation Automated fuel tank assembly system and method
US6202294B1 (en) * 1998-09-25 2001-03-20 Lucent Technologies Inc. EMI/RFI shield assembly cover removal tool
JP2000307289A (en) * 1999-04-19 2000-11-02 Nec Corp Electronic part assembly
US6462436B1 (en) * 1999-08-13 2002-10-08 Avaya Technology Corp. Economical packaging for EMI shields on PCB
BR0014718A (en) 1999-10-12 2003-07-15 Shielding For Electronics Inc Emi containment device
US20010033478A1 (en) 2000-04-21 2001-10-25 Shielding For Electronics, Inc. EMI and RFI shielding for printed circuit boards
TW455964B (en) * 2000-07-18 2001-09-21 Siliconware Precision Industries Co Ltd Multi-chip module package structure with stacked chips
US6967288B2 (en) * 2000-08-18 2005-11-22 Mitsubishi Denki Kabushiki Kaisha Shield cable method of manufacturing shield cable, and discharge lamp lighting device using shield cable
US6757181B1 (en) 2000-08-22 2004-06-29 Skyworks Solutions, Inc. Molded shield structures and method for their fabrication
US6426881B1 (en) * 2000-10-04 2002-07-30 Arthur A. Kurz Shielding arrangement for inter-component shielding in electronic devices
DE10152408A1 (en) * 2000-10-25 2002-05-16 Matsushita Electric Ind Co Ltd System for automatic mounting of electronic components onto a circuit board uses camera scanning of board
DE10112234C1 (en) * 2001-03-06 2002-07-25 Schott Glas Ceramic hob comprises a cooking plate made from glass-ceramic or glass, an electric hot conductor layer, and an insulating layer arranged between the cooking plate and conductor layer
US6900383B2 (en) 2001-03-19 2005-05-31 Hewlett-Packard Development Company, L.P. Board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces
US20030002271A1 (en) * 2001-06-27 2003-01-02 Nokia Corporation Integrated EMC shield for integrated circuits and multiple chip modules
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6486549B1 (en) 2001-11-10 2002-11-26 Bridge Semiconductor Corporation Semiconductor module with encapsulant base
US6717485B2 (en) 2002-02-19 2004-04-06 Hewlett-Packard Development Company, L.P. Interference signal decoupling using a board-level EMI shield that adheres to and conforms with printed circuit board component and board surfaces
JP2003249607A (en) * 2002-02-26 2003-09-05 Seiko Epson Corp Semiconductor device and manufacturing method therefor, circuit board and electronic device
GB0305461D0 (en) 2003-03-10 2003-04-16 Transense Technologies Plc Improvements in the construction of saw devices
US6994901B1 (en) * 2002-11-12 2006-02-07 Dana Corporation Heat shield having a fold-over edge crimp with variable width and method of making same
TW200411871A (en) * 2002-12-30 2004-07-01 Advanced Semiconductor Eng Thermal-enhance package and manufacturing method thereof
TW565009U (en) * 2003-01-20 2003-12-01 Benq Corp Electronic module having ball grid array
TWI235469B (en) * 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
US6873043B2 (en) * 2003-03-10 2005-03-29 Delphi Technologies, Inc. Electronic assembly having electrically-isolated heat-conductive structure
WO2004093505A2 (en) * 2003-04-15 2004-10-28 Wavezero, Inc. Emi shielding for electronic component packaging
US7088009B2 (en) * 2003-08-20 2006-08-08 Freescale Semiconductor, Inc. Wirebonded assemblage method and apparatus
JP2005072113A (en) 2003-08-21 2005-03-17 Ngk Insulators Ltd Piezoelectric/electrostrictive device
US7030469B2 (en) 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
US20080112151A1 (en) 2004-03-04 2008-05-15 Skyworks Solutions, Inc. Overmolded electronic module with an integrated electromagnetic shield using SMT shield wall components
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US6974724B2 (en) * 2004-04-28 2005-12-13 Nokia Corporation Shielded laminated structure with embedded chips
US7633170B2 (en) * 2005-01-05 2009-12-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and manufacturing method thereof
JP2007189199A (en) 2005-12-12 2007-07-26 Tdk Corp Capacitor and method of manufacturing same
JP5639738B2 (en) 2008-02-14 2014-12-10 日本碍子株式会社 Method for manufacturing piezoelectric / electrostrictive element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040262645A1 (en) * 2001-05-18 2004-12-30 Corporation For National Research Initiatives Radio frequency microelectromechanical systems (MEMS) devices on low-temperature co-fired ceramic (LTCC) substrates
US20020179321A1 (en) * 2001-05-30 2002-12-05 Ericsson Inc. Liquid dielectrick tuning of an integrated circuit
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170118877A1 (en) * 2015-10-22 2017-04-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit package with bond wires to provide internal shielding between electronic components
US10134682B2 (en) 2015-10-22 2018-11-20 Avago Technologies International Sales Pte. Limited Circuit package with segmented external shield to provide internal shielding between electronic components
US10163808B2 (en) 2015-10-22 2018-12-25 Avago Technologies International Sales Pte. Limited Module with embedded side shield structures and method of fabricating the same
US11239178B2 (en) * 2018-11-29 2022-02-01 Advanced Semiconductor Engineering, Inc. Semiconductor package structures and methods of manufacturing the same

Also Published As

Publication number Publication date
US9054115B2 (en) 2015-06-09
US20110084368A1 (en) 2011-04-14
US8071431B2 (en) 2011-12-06
US9041168B2 (en) 2015-05-26
US20150255403A1 (en) 2015-09-10
US8399972B2 (en) 2013-03-19
US20070241440A1 (en) 2007-10-18
WO2008018959A2 (en) 2008-02-14
US20120146178A1 (en) 2012-06-14
WO2008018959A3 (en) 2008-04-03
US20120137514A1 (en) 2012-06-07

Similar Documents

Publication Publication Date Title
US9041168B2 (en) Overmolded semiconductor package with wirebonds for electromagnetic shielding
TWI381497B (en) Overmolded semiconductor package with an integrated antenna
CN101814484B (en) Chip package and manufacturing method thereof
CN101996962B (en) Electronic component module and radio communications equipment
US7445968B2 (en) Methods for integrated circuit module packaging and integrated circuit module packages
US7198987B1 (en) Overmolded semiconductor package with an integrated EMI and RFI shield
US5397917A (en) Semiconductor package capable of spreading heat
KR20230034994A (en) Semiconductor device and manufacturing method thereof
US20070267725A1 (en) Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package
US10141268B2 (en) Circuit package with internal and external shielding
US20040195591A1 (en) Digital and RF system and method therefor
US10847480B2 (en) Semiconductor package with in-package compartmental shielding and fabrication method thereof
EP3678175A1 (en) Semiconductor package with in-package compartmental shielding
CN106711123A (en) Semiconductor package and method of manufacturing the same
JP4284744B2 (en) High frequency integrated circuit device
US20200168560A1 (en) Semiconductor package with in-package compartmental shielding and fabrication method thereof
US11515282B2 (en) Electromagnetic shields with bonding wires for sub-modules
CN106653734B (en) Semiconductor device with electromagnetic interference shielding and method of manufacturing the same
US20220310530A1 (en) Application of conductive via or trench for intra module emi shielding
US20230411304A1 (en) Semiconductor device and method for making the same
CN117878099A (en) Semiconductor device and method of forming graphene core shell embedded in shielding layer
CN115692326A (en) Electronic package and manufacturing method thereof

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONMENT FOR FAILURE TO CORRECT DRAWINGS/OATH/NONPUB REQUEST