CN106033755A - Semiconductor device possessing electromagnetic interference shielding and substrate band - Google Patents
Semiconductor device possessing electromagnetic interference shielding and substrate band Download PDFInfo
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- CN106033755A CN106033755A CN201510115569.7A CN201510115569A CN106033755A CN 106033755 A CN106033755 A CN 106033755A CN 201510115569 A CN201510115569 A CN 201510115569A CN 106033755 A CN106033755 A CN 106033755A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48484—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) being a plurality of pre-balls disposed side-to-side
- H01L2224/48485—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) being a plurality of pre-balls disposed side-to-side the connecting portion being a wedge bond, i.e. wedge on pre-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A semiconductor device and a substrate band are disclosed. The semiconductor device comprises a substrate and a conductive block arranged on a surface of the substrate. The substrate comprises a grounded conductive pattern on the surface of the substrate. The grounded conductive pattern surrounds a target area. The conductive block is electrically connected to the grounded conductive pattern and provides electromagnetic interference (EMI) shielding for the target area at a transverse direction of the surface of the substrate.
Description
Technical field
This technology relates to semiconductor device.
Background technology
The a large amount of of demand of portable consumer electronics are increased the demand promoted high-capacity storage device.All
Such as the non-volatile memory semiconductor device of flash-storing card, just become to be widely used with satisfied numeral letter
Breath storage and the growing demand of exchange.Their portability, multi-functional and robust set
Meter and their highly reliable and Large Copacity make such memory device in multiple electronic installation
Use is preferable, and described electronic installation such as includes digital camera, digital music player, video
Game machine, PDA and cell phone.
Along with electronic unit becomes less and works, by electromagnetic interference (EMI) with penetrate in higher frequency
Noise and crosstalk that frequency interference (RFI) causes are more problematic.Electromagnetism (EM) radiation is carried fast
The circuit of the signal of speed change is launched as the side-product of its normal operating.Such electromagnetic radiation is by EMI
And/or RFI is incorporated into other circuit, cause less desirable interference or noise.
Have been made by making great efforts to apply conduction plated film in band rank or single unit rank to shield
Cover transmitting and the reception of EM and/or RF radiation.Fig. 1 is the tradition applying EMI shielding in band rank
The flow chart of method.As it is shown in figure 1, in naked core adhering step 110, multiple semiconductor bare chip quilts
It is arranged on each the single substrate being arranged in substrate band.Then, in wire bonding step 120,
Form multiple wire bonding to electrically connect each semiconductor bare chip and substrate.Then, in molding step 130
In, moulding compound is formed on whole substrate band with encapsulating semiconductor naked core and wire bonding.Then, exist
In EMI plating steps 140, EMI screen layer is applied on the top surface of moulding compound.Finally, at list
One changes in step 150, by cutting EMI screen layer, moulding compound between neighbouring semiconductor device
And substrate, substrate band is separated with the single single semiconductor device turning to packing forms.According to said method,
EMI can be more efficiently provided to shield in band rank, but only on the top of single semiconductor device
Thering is provided EMI shielding on surface, therefore semiconductor device still lacks the EMI shielding on its side surface.
Fig. 2 is the flow chart applying traditional method that EMI shields in unit rank.As in figure 2 it is shown,
It is being similar to the naked core adhering step 210 described in Fig. 1, wire bonding step 220 and molding step 230
Afterwards, the single semiconductor device of unification in unification step 240.Then step is adhered at packaging body
In rapid 250, semiconductor device is transferred and passes through such as to use double faced adhesive tape to be adhered on common carrier.
Then in EMI plating steps 260, the outer surface EMI screen layer plated film that semiconductor device exposes.
Then, in packaging body release steps 270, there is the single semiconductor device of EMI screen layer 380
Part is discharged from the carrier being located below to carry out further technique.According to said method, EMI shielding is permissible
It is not provided in only on the top surface of semiconductor device, and provides on the side surface of semiconductor device.But
It is such technique shortcoming with the most inefficient and additional pollution, inefficient is drawn by cell level other places reason
Rising, additional pollutes the double faced adhesive tape used in encapsulation adhering step 250.
Technology contents
In the one side of this technology, semiconductor device includes substrate, is included on the surface of described substrate
The conductive pattern of ground connection, the conductive pattern surrounding target region of described ground connection；And conductive barrier, if
Putting on the surface of described substrate, described conductive barrier is electrically connected to the conductive pattern of described ground connection and is
Described target area provides electromagnetic interference (EMI) to shield on the horizontal direction on the surface of described substrate.
In an embodiment, the conductive pattern of ground connection comprise enclose described target area continuously or the mark of segmentation
Line or the multiple discrete bond pads being distributed in around described target area.
In an embodiment, conductive barrier comprise by linear arrangement and be bonded on described conductive pattern multiple
At least one lead-in wire fence that feed-through collar is constituted, and each feed-through collar has arc.Each lead-in wire fence
In described feed-through collar there is identical ring height and identical ring span.Multiple drawing is included in conductive barrier
In the case of line fence, the plurality of lead-in wire fence is parallel to each other, and in different lead-in wire fences
Described feed-through collar has an identical ring span, but offsets from each other along the bearing of trend of described lead-in wire fence.
Therefore, the described lead-in wire fence horizontal direction on the surface of described substrate and be perpendicular to described lead-in wire fence
There is on bearing of trend Integral net shaped projection.The feed-through collar of different lead-in wire fences has different rings height.
The feed-through collar of same lead-in wire fence is continuously connected one by one.The feed-through collar of same lead-in wire fence by
Wall scroll bonding wire is formed.Alternatively, the described feed-through collar of same lead-in wire fence is with rule therebetween
Interval is spaced from each other.
In an embodiment, semiconductor device is additionally included in the wire bonding in described target area, wherein,
Described wire bonding and at least one lead-in wire fence are formed in same lead key closing process.Lead-in wire fence by
Gold wire, copper lead-in wire or silver alloy lead-in wire are formed.
In an embodiment, described conductive barrier is by resin matrix and to be dispersed in leading in described resin matrix
The conductive paste dam that electricity granule is constituted.Described conductive paste dam is the continuous print dam enclosing described target area completely
Or it is made up of the discrete portions being distributed in around described target area.Resin includes epoxy resin, and
Conductive particle includes gold grain, copper granule or Argent grain.
In an embodiment, target area is at least region and the EMI inducing at EMI sensing element place
One of the region at element place.EMI sensing element includes memorizer naked core, and EMI inducing element
Including controller naked core.
In an embodiment, semiconductor device can also include the moulding compound encapsulating conductive barrier；And cover
It is parallel to the EMI screen layer on the surface of the moulding compound on the surface of substrate.
In the another aspect of this technology, substrate band includes the multiple substrates being arranged as matrix form.Each
Substrate includes the conductive pattern of ground connection on a surface of a substrate, the conductive pattern surrounding target of described ground connection
Region.
Accompanying drawing explanation
Fig. 1 is the flow chart of traditional manufacture method of the semiconductor device with EMI screen layer.
Fig. 2 is the flow chart of another traditional manufacture method of the semiconductor device with EMI screen layer.
Fig. 3 A, 3B and 3C are the schematic side of the semiconductor device of the first embodiment according to this technology
Figure, plan view and axonometric chart.
Fig. 3 D is that the diagrammatic plan of the semiconductor device of the change case of the first embodiment according to this technology regards
Figure.
Fig. 4 A and 4B is the signal of the semiconductor device of the change case of the first embodiment according to this technology
Side view and plan view.
Fig. 5 A and 5B is the semiconductor device of another change case of the first embodiment according to this technology
Diagrammatic side view and plan view.
Fig. 6 is the schematic side of the semiconductor device of another change case of the first embodiment according to this technology
Figure.
Fig. 7 A and 7B is the semiconductor device of another change case of the first embodiment according to this technology
Diagrammatic side view and plan view.
Fig. 8 is the schematic perspective of the semiconductor device of another change case of the first embodiment according to this technology
Figure.
Fig. 9 is the schematic isometric of the semiconductor device of the second embodiment according to this technology.
Figure 10 is the schematic isometric of the semiconductor device of the change case of the second embodiment according to this technology.
Figure 11 is that the signal of the semiconductor device of another change case of the second embodiment according to this technology is stood
Body figure.
Figure 12 is the schematic plan view of the substrate band of the embodiment according to this technology.
Detailed description of the invention
The embodiment relating to semiconductor device is described referring now to Fig. 3 A to 12.It should be understood that this
Technology can realize with multiple different form and be understood not to be limited in reality presented herein
Execute in example.And be to provide these embodiments and make the disclosure be clearly with complete and to this area
Technical staff gives full expression to this technology.It is included in by claims it is true that this technology is intended to covering
The equivalent of alternative, modification and these embodiments in the scope and spirit of the present invention of definition.
Additionally, in the following detailed description of this technology, propose multiple detail to provide thorough to this technology
Understanding.But, those of ordinary skill in the art are it should be clear that this technology can need not these tools
The details of body and be implemented.
As the term "left", "right" that may be used here, " top ", " end ", " on ", D score, " vertical
Straight " and/or " horizontal " merely for convenience and descriptive purpose, and it is not intended to limit this technology
Description, can be with exchange position with the cited as many project of project.Additionally, unless context
Clearly dictate otherwise, as used herein, article " " and " one " be intended to include odd number and
Both plural forms.Term " substantially " and/or " about " mean that the size specified or parameter can be right
Change in the acceptable fabrication tolerance of given application.In one embodiment, acceptable system
Making tolerance is ± 0.25%.
Run through accompanying drawing, the same or analogous parts identical mode mark of identical last two digits
Note.
With reference to Fig. 3 A to Fig. 8, the change according to first embodiment He the first embodiment of this technology will be described
The semiconductor device of example.Fig. 3 A, 3B and 3C are partly leading of the first embodiment according to this technology respectively
The diagrammatic side view of body device 300, plan view and axonometric chart.As shown in Figure 3A, semiconductor device
300 include that substrate 310, substrate 310 have the conductive pattern of the ground connection of the upper surface at substrate 310,
Such as continuous print conductive trace 320；And such as lead-in wire the leading of fence 330 being arranged on conductive pattern
Power block.Semiconductor device 300 can also include that at least one element needing EMI to protect is (described
Element is such as arranged on the semiconductor bare chip 340 on substrate 310), encapsulating conductive barrier and quasiconductor naked
The moulding compound 350 of core 340 and the top EMI screen layer 360 being applied on the top surface of moulding compound 350.
Semiconductor device 300 can also include electrically connecting semiconductor bare chip 340 and the wire bonding of substrate 310
370.It should be noted that for the clearness described, electrical connection semiconductor bare chip and the lead-in wire key of substrate
It is combined in side view and plan view and has been not shown, and moulding compound and top EMI screen layer regard in plane
Figure and axonometric chart have been not shown.
Substrate 310 can be the patch panel of such as flexible printed circuit board (FPCB), described flexible print
Printed circuit board has electrolyte core and is formed thereon and electrical conductance patterns on lower both sides.Core can be by respectively
Kind of dielectric substance is formed, and seems such as, polyimide laminates, includes the asphalt mixtures modified by epoxy resin of FR4 and FR5
Fat, Bismaleimide Triazine (BT) etc..In an alternate embodiment, core can be pottery or
Organically.The conductive pattern of ground connection is such as via the intermediate layer (not shown) being arranged in substrate 310 even
Receive earthing potential.The conductive pattern of ground connection is around the target area on substrate.As shown in Figure 3 B,
Target area can include all effective real estate region A on substrate 310 so that the conduction of ground connection
Pattern such as continuous print conductive trace 320 is arranged as the periphery along substrate 310, with to being arranged on substrate
All elements on 310 provide the EMI shielding from outside EM radiation.Mesh shown by Fig. 3 B
Mark region A is only example, and structure, number and the layout that target area A is on substrate can be
Further embodiment changes.It addition, multiple target areas may reside on substrate, and according to substrate
Design, the size and dimension of each target area can with the every other target area on substrate not
With.
As shown in Figure 3 B, the conductive pattern of ground connection can be the continuous print conduction mark enclosing target area A
Line 320.Such continuous print conductive trace 320 can be at other conductive pattern prepared on substrate 310
It is made up of the metal that typically copper or copper are gold-plated during (not shown).Continuous print conductive trace 320 has
Have substantially with the top surface plane of substrate 310 upper surface or the upper table of slightly lower than substrate 310
The upper surface (as shown in Figure 3A) in face.Alternatively, the conductive pattern of ground connection can be the conduction mark of segmentation
Line.Such as, in the case of substrate has rectangular profile, the conductive trace of segmentation can be designed as four
Individual continuous print line segment, each line segment is arranged along a corresponding limit of substrate.The conductive pattern of above-mentioned ground connection
Case 320 only example, and the structure of the conductive pattern of the ground connection on substrate can be in further embodiment
Middle change.
Conductive pattern that the conductive barrier being arranged on the conductive pattern of ground connection is electrically connected to ground and be
Target area A provides electromagnetic interference (EMI) to shield on the horizontal direction on the surface of substrate 310.?
In semiconductor device 300 shown in Fig. 3 A-3C, conductive barrier is by being linearly arranged in continuous print conduction mark
The lead-in wire fence 330 that multiple feed-through collars 332 on line 320 are constituted.Lead-in wire fence 330 role with
Wire netting is similar, in order to shield electromagnetic radiation.Each feed-through collar 332 has arc, and the two ends of ring are by drawing
Line bonding attaches on conductive trace 320, and described wire bonding is known to those skilled in the art, all
As ball is bonded, seam bonding, therefore the details of wire bonding will not further describe at this.Lead-in wire fence 330
Feed-through collar 332 can be continuously formed one by one by wire bonding apparatus, this wire bonding
Device includes for supplying the lead bonding apparatus being referred to as chopper with bonding wire and fixing substrate 310
Static workbench.When forming lead-in wire fence 330, chopper exists round the periphery of target area A
Move above the continuous print conductive trace 320 of substrate 310 and carry out wire bonding.Feed-through collar 332 is permissible
The whole periphery of surrounding target region A is formed on continuous print conductive trace 320, thus completely enclosed mesh
Mark region A, as shown in Figure 3 D.In this situation, need to close last of this lead-in wire fence 330
Individual wire bonding 334 separates with first wire bonding 333 of the fence 330 that starts to go between, thus for splitting
Cutter provides enough spaces to form last wire bonding 334 on continuous print conductive trace 320.
This can be accomplished by: forms less ring span for last feed-through collar, with the
Leaving gap between one wire bonding 333 and last wire bonding 334, as shown in Figure 3 D；Or
Person forms bigger ring span for last feed-through collar thus strides across the first wire bonding 333, or
For last feed-through collar with lead-in wire fence in before the bearing of trend of feed-through collar there is one partially
The side moving angle upwardly extends lead-in wire.Alternatively, lead-in wire fence can be segmentation.Such as, such as Fig. 3 B
Shown in, lead-in wire fence 330 is constituted by four separate section.Feed-through collar in each segment 332 1 connects
One be formed continuously.Adjacent legs bonding in each end of adjacent segment can separate, thus is chopper
The space providing enough forms corresponding wire bonding on continuous conduction trace 320.
The conductive lead wire forming lead-in wire fence 330 includes bonding wire well known by persons skilled in the art, bag
Include gold wire, copper lead-in wire or silver alloy lead-in wire etc..Conductive lead wire can have in about 10 μm to big
Diameter in the range of about 50 μm, although the bigger diameter of the conductive lead wire of lead-in wire fence 330 is permissible
Make that there is more preferable EMI shield effectiveness.
As shown in Figure 3A, the feed-through collar 332 in lead-in wire fence 320 can have identical ring height H
With identical ring span S.The ring height H of the feed-through collar 332 of lead-in wire fence 330 is provided to draw
Line fence 330 substantially shield be arranged on by lead-in wire fence 330 around target area A in partly lead
Body naked core 340.Such as, the summit of feed-through collar 332 can be substantially in the semiconductor bare chip with the top
At the level that the top surface of 340 is identical.In such a case, at summit and the molding of feed-through collar 332
Enough cap space (cap of such as 50 μm to 100 μm will be had between the top surface of material 350
Space), to avoid damaging feed-through collar 332 in the moulding technology of next encapsulating lead-in wire fence 330.
And, such relatively small cap space also makes go between fence 330 and top EMI screen layer 360
Coordinate to provide the complete EMI shielding on the top and side surface of semiconductor device 300.Lead-in wire
Ring span S of ring 332 can be arranged based on ring height H and frequency of electromagnetic radiation.Little ring span S
Improve the density of the feed-through collar gone between in fence, thus improve the EMI shielding to the radiation of altofrequency EM
Ability.But little ring span S causes the wide aspect ratio between ring height H and ring span S, causes
For bearing the mechanical strength of the more weak feed-through collar of the impact applied in ensuing moulding technology.Example
As, according to the embodiment of this technology, what ring height H can be designed as ring span S about 60% arrives
100%, especially, the 80% of ring span S.Ring span S such as can be configured so that and arrives in 100 μm
In the range of 500 μm.
Lead-in wire fence 330 can be connected semiconductor bare chip 340 and the wire bonding of substrate 310 with being formed
Formed on the identical wire bonding apparatus of 370, in identical lead key closing process.Accordingly, as
The increase of the lead-in wire fence of the EMI shielding on the side surface of semiconductor device 300 can be fully integrated
The traditional technique for forming the semiconductor device with EMI shielding in band rank as shown in Figure 1
In, and on the top surface of semiconductor device, not only provide EMI in band rank and shield, and also
EMI shielding is provided on the side surface of semiconductor device.In lead key closing process, go between fence 330
In feed-through collar 332 in wire bonding apparatus with the identical formation that arranges, thus it is high to have identical ring
Degree H and ring span S, in order to improve yield.In this example, lead-in wire fence can be with wall scroll lead-in wire even
Formed continuously and do not cut off and go between to improve production capacity further, in this technique and WO2012/155345
Describe is similar, and it is incorporated herein by reference.
The semiconductor bare chip 330 being arranged in the target area A on substrate 310 may include that such as deposits
The EMI sensing element of reservoir naked core, or launch such as controller naked core or the altofrequency of EM radiation
The EMI inducing element of element.Two kinds of elements can also all be arranged in the A of target area so that can
To shield whole semiconductor device from the impact from outside EM radiation.Connect semiconductor bare chip 330
Any wire bonding well known by persons skilled in the art can be used to tie with the wire bonding 370 of substrate 310
Structure, and will not be described in further detail.
Moulding compound 350 is applied in moulding technology well known by persons skilled in the art, and its encapsulating is arranged on
Lead-in wire fence 330, semiconductor bare chip 340 and wire bonding 370 on substrate 310 and other element
(not shown).Top EMI screen layer 360 can be with the conductive material of such as copper with known sputter or electricity
Depositing process applies.
According to this technology, the conductive barrier of the EMI shielding on the side surface of semiconductor device is formed
In moulding compound, such as the lead key closing process before unification technique is formed.Therefore by so
Conductive barrier and the top EMI screen layer that is applied on the top surface of moulding compound, can be real in band rank
The most complete EMI shielding, the EMI shielding on its top being included in semiconductor device and side surface.Right
Than in realizing in the other traditional method of cell level as shown in Figure 2, improve and there is EMI shielding
The production capacity of semiconductor device, efficiency and reliability.According to first embodiment, by lead-in wire fence as leading
Power block, such conductive barrier efficiently and can be easily formed by lead key closing process, institute
State lead key closing process can be readily integrated in the traditional technique with band rank as shown in Figure 1,
Thus further enhance efficiency and reliability.
Fig. 4 A and Fig. 4 B shows the change case of the first embodiment of this technology.Shown in Fig. 4 A and 4B
The semiconductor device 400 gone out is substantially identical with shown by Fig. 3 A to 3C, except the conduction of ground connection
Outside pattern.Therefore, only further describe the difference of the conductive pattern about ground connection, and its of change case
Its aspect will not be repeated.
As illustrated in figures 4 a and 4b, the conductive pattern of ground connection includes being distributed in around the A of target area many
The bond pads 420 of individual discrete ground connection.Each end of the feed-through collar of lead-in wire fence 430 is wirebonded to
In adjacent bond pads 420 so that ring span S of feed-through collar is fixed to adjacent bond pads
Interval between 420.In contrast to the embodiment shown in Fig. 3 A to 3C, due to save for formed from
The liner dissipated rather than the conductive material of continuous print conductive trace, the substrate 410 of semiconductor device 400 can
To be formed with low cost.But, due to continuous print conductive trace, partly leading shown by Fig. 3 A to 3C
Body device 300 provides more freely to regulate the structure of feed-through collar and to strengthen Earthing Reliability.According to
This technology, the conductive pattern of ground connection includes and encloses the continuous conduction trace of target area (such as at figure
Continuous print conductive trace 320 shown in 3A-3C, encloses the trace of the segmentation of target area or encloses
Multiple discrete bond pads (such as, the bonding lining shown in Fig. 4 A and 4B around target area distribution
Pad 420),
Fig. 5 A, Fig. 5 B and Fig. 6 show two other change case of the first embodiment of this technology.Figure
The semiconductor device 600 shown in semiconductor device 500 and Fig. 6 shown in 5A and Fig. 5 B and Fig. 3 A
Essentially identical to those shown in 3C, in addition to lead-in wire fence.Therefore, pass is only further described
In the difference of lead-in wire fence, and the other side of change case will not be repeated.
As shown in Figure 5 A and 5B, conductive barrier includes the multiple lead-in wire fences being parallel to each other, such as two
Individual lead-in wire fence 530 and 535.This technology is not limited to this, and if needing conductive barrier to have
More wires fence.Feed-through collar in different lead-in wire fences can have same or analogous structure,
The most identical ring span and/or identical ring height, so the lead-in wire key when forming different lead-in wire fences
Conjunction equipment can use identical setting.The feed-through collar of different lead-in wire fences is along the extension of lead-in wire fence
Direction offsets from each other.Such as, the feed-through collar of the lead-in wire fence 530 shown in Fig. 5 A and lead-in wire fence 535
Feed-through collar there is identical ring height and identical ring span, and offset half their ring span；
And the feed-through collar of the feed-through collar of the lead-in wire fence 630 shown in Fig. 6 and lead-in wire fence 635 has identical ring
Span but the most different ring height, and offset half their ring span.It is to say, at Fig. 5 A
In shown embodiment, the feed-through collar of different lead-in wire fences has identical ring height, and shown in Fig. 6
Embodiment in, the feed-through collars of different lead-in wire fences have different ring height.In both cases, draw
Line fence the horizontal direction of substrate surface and being perpendicular to go between fence bearing of trend on there is integral net
The projection of shape.Such reticulated structure reduces in horizontal direction (such as, the method for paper in Fig. 5 A and Fig. 6
Line direction) on the opening size of lead-in wire fence, thus strengthen the terminal density of conductive barrier, to high frequency
The radiation of rate EM provides relatively reliable and effective shielding.
In the above-described embodiments, the feed-through collar of lead-in wire fence is continuously formed one by one.Alternatively,
According to another change case of this technology, as in the semiconductor device 700 shown by Fig. 7 A and 7B,
The feed-through collar of lead-in wire fence can also be spaced from each other with the interval of rule therebetween.Owing to saving lead-in wire material
Material and the time of lead key closing process, semiconductor device 700 can have lower cost and higher product
Amount, but compromise be the side table of the semiconductor device caused due to terminal density that lead-in wire fence 730 is relatively low
The EMI shield effectiveness of the minimizing on face.The other side of semiconductor device 700 substantially arrives with Fig. 3 A
Those shown in 3C are identical, and will not be repeated.
In the above-described embodiments, the conductive pattern of ground connection and lead-in wire fence are arranged along the edge of substrate
Think that whole semiconductor device provides the EMI shielding from outside EM radiation.This technology is not limited to
This.Semiconductor device 800 in another change case of the first embodiment as this technology shown in Fig. 8
In, continuous print conductive trace 820 and lead-in wire fence 830 as conductive pattern are only provided as base
Single element 845 in the target area B of a part for plate 810 is around.Element 845 can be
Launch the EM source element of EM radiation.Therefore by shielding element 845 individually, can effectively subtract
Few other semiconductor bare chip 840 for being arranged on same substrate 810 neighbouring EM source element 845
EMI, other semiconductor bare chip 840 such as memorizer naked core described.Semiconductor device 800 can also wrap
The conductive pattern including extra ground connection and the conduction resistance of the lead-in wire fence such as arranged along the edge of substrate
Gear, thinks that whole semiconductor device provides the EMI shielding from outside EM radiation.Semiconductor device
The other side of part 800 is substantially identical with those shown in Fig. 3 A to 3C, and will be not at this
Repeat.
The conductive barrier of the first embodiment according to this technology includes the fence that goes between, but this technology is not limited to
This.In the semiconductor device according to the second embodiment and the change case of second embodiment of this technology, lead
Power block can be the conductive paste dam being made up of with the conductive particle being dispersed in resin matrix resin matrix,
It will describe with reference to Fig. 9 to Figure 11.
Semiconductor device 900 and 1000 shown in Fig. 9 and Figure 10 substantially with in Fig. 3 A to 3C
Those illustrated are identical, in addition to conductive barrier is conductive paste dam.Therefore, only further describe about
The difference of conductive barrier, and the other side of change case will not be repeated.
As shown in Figure 9, conductive paste dam 930 is the continuous print dam enclosing target area A completely.Cream
Matrix can include epoxy resin, and conductive particle includes gold grain, copper granule or Argent grain etc..Can
Alternatively, as shown in Figure 10, conductive paste dam 1030 is by the discrete portions being distributed in around the A of target area
Constitute.By ink-jetting process well known by persons skilled in the art, conductive paste dam 930 and 1030 can be executed
Not shown in conductive pattern Fig. 9 and Figure 10 of ground connection under being added to) on, this ink-jetting process is in encapsulating
Semiconductor bare chip, wire bonding and the moulding technology on conductive paste dam on substrate and unification technique afterwards
Carry out before.Such as, the liquid of the cream being made up of epoxy resin and Argent grain can be applied to by nozzle
Above the conductive pattern of the ground connection on substrate, nozzle moves along the periphery of target area A, and cream subsequently
Heat or ultraviolet curing process solidify, thus on substrate, defines the cream dam of solid-state.Conductive paste dam 930
With 1030 conductive patterns being electrically connected to ground to carry out EMI shielding.The width on conductive paste dam and height
Can be controlled by technological parameters such as the translational speeds of the viscosity of such as cream, nozzle diameter and nozzle.
Correspondingly, it is possible to achieve the EMI shielding of band rank.Additionally, apply the conductive paste as conductive barrier
The technique on dam can also be integrated in other technique before moulding technology, such as forms epoxy on substrate
The ink-jetting process of resin pad.
Figure 11 shows another change case of second embodiment of this technology.Semiconductor device shown in Figure 11
Part 1100 is the most same as shown in Figure 8, in addition to conductive barrier is conductive paste dam.Therefore,
The other side of change case will not be repeated.
Figure 12 is the flat of the substrate band 1200 of the semiconductor device for manufacturing the embodiment according to this technology
Face view.As shown in figure 12, substrate band 1200 includes the multiple substrates 1210 being arranged in matrix
And multiple substrates 1210 are delimitated by line 1230 therebetween.Each substrate 1210 include around
The conductive pattern of the ground connection of the target area A on the surface of substrate 1210 such as continuous print conductive trace
1220.The details of substrate 1210 is the most same as described above, and therefore will not be repeated.
Substrate band according to this technology, conductive barrier can be arranged on before molding and unification technique
On the ground connection conductive pattern of the substrate 1210 on substrate band 1200.Therefore the shielding of band rank EMI is permissible
It is provided to the semiconductor device of manufacture with such substrate band, enabling apply molding in band rank
EMI shielding on the side surface of the semiconductor device beyond top EMI shielding on the top surface of material.Cause
This, improve the production capacity of semiconductor device, efficiency and the reliability with EMI shielding.
Aforementioned the description that the present invention is detailed is presented only for the purpose of illustration and description.Be not intended to be
Exhaustive or limit the present invention in disclosed precise forms.Many can be had according to above-mentioned teaching
Modifications and variations.Described embodiment is chosen so as to explain the principle of the present invention and actual application thereof best
So that those skilled in the art are best with various embodiments and be applicable to intended specific use
Various amendments utilize the present invention.The claim that the scope of the present invention is intended to by enclosing at this defines.
Claims (20)
1. a semiconductor device, including:
Substrate, the conductive pattern of the ground connection being included on the surface of described substrate, the conductive pattern of described ground connection
Case surrounding target region；And
Conductive barrier, is arranged on the surface of described substrate, and described conductive barrier is electrically connected to described ground connection
Conductive pattern and on the horizontal direction on the surface of described substrate, provide electromagnetism for described target area
Interference (EMI) shielding.
2. semiconductor device as claimed in claim 1, wherein, the conductive pattern of described ground connection comprises and encloses
Close described target area continuously or the trace of segmentation or be distributed in around described target area multiple
Discrete bond pads.
3. semiconductor device as claimed in claim 2, wherein, described conductive barrier comprises by linear rows
Arrange and be bonded at least one lead-in wire fence that multiple feed-through collars on described conductive pattern are constituted, and often
Individual feed-through collar has arc.
4. semiconductor device as claimed in claim 3, wherein, the described lead-in wire in each lead-in wire fence
Ring has identical ring height and identical ring span.
5. semiconductor device as claimed in claim 4, wherein, described conductive barrier comprises and is parallel to each other
Multiple lead-in wire fences, and the described feed-through collar in different lead-in wire fences have identical ring across
Degree, but offset from each other along the bearing of trend of described lead-in wire fence.
6. semiconductor device as claimed in claim 5, wherein, described lead-in wire fence is at described substrate
The horizontal direction on surface and be perpendicular on the bearing of trend of described lead-in wire fence that there is Integral net shaped projection.
7. semiconductor device as claimed in claim 6, wherein, the described lead-in wire of different lead-in wire fences
Ring has different ring height.
8. the semiconductor device as described in one of claim 3-6, wherein, same lead-in wire fence described
Feed-through collar is continuously connected one by one.
9. semiconductor device as claimed in claim 8, wherein, the described feed-through collar of same lead-in wire fence
Formed by wall scroll bonding wire.
10. the semiconductor device as described in one of claim 3-6, wherein, the institute of same lead-in wire fence
State feed-through collar to be spaced from each other with the interval of rule therebetween.
11. semiconductor device as claimed in claim 3, are additionally included in the lead-in wire in described target area
Bonding, wherein, described wire bonding and at least one lead-in wire fence are formed in same lead key closing process.
12. semiconductor device as claimed in claim 3, wherein, described lead-in wire fence by gold wire,
Copper lead-in wire or silver alloy lead-in wire are formed.
13. semiconductor device as claimed in claim 2, wherein, described conductive barrier is by resin base
The conductive paste dam that body and the conductive particle being dispersed in described resin matrix are constituted.
14. semiconductor device as claimed in claim 13, wherein, described conductive paste dam is to enclose completely
The continuous print dam of described target area or be made up of the discrete portions being distributed in around described target area.
15. semiconductor device as claimed in claim 13, wherein, described resin includes epoxy resin,
And described conductive particle includes gold grain, copper granule or Argent grain.
16. semiconductor device as described in one of claim 1-7,11-15, wherein, described target area
Territory is at least one of the region at EMI sensing element place and the region at EMI inducing element place.
17. semiconductor device as claimed in claim 16, wherein, described EMI sensing element includes
Memorizer naked core, and described EMI inducing element includes controller naked core.
18. semiconductor device as claimed in claim 1, also include,
Moulding compound, encapsulates described conductive barrier；And
EMI screen layer, covers the surface of described moulding compound, and the surface of described moulding compound is parallel to described base
The surface of plate.
19. 1 kinds of substrate bands, including, it being arranged as multiple substrates of matrix form, each substrate is included in
The conductive pattern of the ground connection on the surface of described substrate, the conductive pattern surrounding target region of described ground connection.
20. substrate bands as claimed in claim 19, wherein, the conductive pattern of described ground connection comprises and encloses
Described target area continuously the trace of segmentation or be distributed in around described target area multiple discrete
Bond pads.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510115569.7A CN106033755A (en) | 2015-03-17 | 2015-03-17 | Semiconductor device possessing electromagnetic interference shielding and substrate band |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510115569.7A CN106033755A (en) | 2015-03-17 | 2015-03-17 | Semiconductor device possessing electromagnetic interference shielding and substrate band |
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| CN201510115569.7A Pending CN106033755A (en) | 2015-03-17 | 2015-03-17 | Semiconductor device possessing electromagnetic interference shielding and substrate band |
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Cited By (1)
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| CN112234048A (en) * | 2020-12-14 | 2021-01-15 | 甬矽电子(宁波)股份有限公司 | Electromagnetic shielding module packaging structure and electromagnetic shielding module packaging method |
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Application publication date: 20161019 |