CN105990317A - Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof - Google Patents
Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof Download PDFInfo
- Publication number
- CN105990317A CN105990317A CN201510088691.XA CN201510088691A CN105990317A CN 105990317 A CN105990317 A CN 105990317A CN 201510088691 A CN201510088691 A CN 201510088691A CN 105990317 A CN105990317 A CN 105990317A
- Authority
- CN
- China
- Prior art keywords
- substrate
- ground connection
- conductive member
- engagement pad
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The present invention discloses a device with an electromagnetic interference shield layer and a semiconductor and a manufacture method thereof. The semiconductor device comprises: a substrate comprising at least one grounding contact pad on the surface of the substrate; at least one semiconductor naked core arranged on the surface of the substrate; a molding compound configured to package at least one semiconductor naked core; an electromagnetic interference (EMI) shielding layer configured to at least partially cover the outer surface of the molding compound; and a conductive member formed above the substrate, packaged in the molding compound and having a first end and a second end opposite to the first end, wherein the first end is joint on the grounding contact pad, and the second end is terminated on the electromagnetic interference shield layer on the surface of the surface above the substrate.
Description
Technical field
This technology relates to semiconductor device.
Background technology
Quick growth in portable consumer electronics product demand drives the demand of high capacity storage device.
The Nonvolatile semiconductor memory device of such as flash-storing card just becomes to be widely used for meeting day by day to increase
Long digital information storage and the demand of exchange.Their portability, multi-functional and durable design and
Their high reliability and Large Copacity have made such storage device be ideally used to broad category of electricity
Sub-device, for example, include digital camera, digital music player, video game console, PDA and shifting
Mobile phone.
Although known multiple packaging structure, but flash-storing card generally can be fabricated to system in package
(system-in-a-package, SiP) or multi-chip module (MCM), plurality of semiconductor bare chip
(die) construction with stacking is arranged on substrate.Figure 1A and 1B is to have different stacked structures
The diagrammatic side view of Conventional semiconductor devices 100A and 100B.Semiconductor device 100A and 100B is equal
Including multiple nonvolatile memory naked cores 120 being arranged on substrate 110 and be arranged on depositing of top
The controller naked core 130 of reservoir naked core 120.Memory naked core 120 is stacked self, or has
Offset configuration (Figure 1A) or there is the vertical configuration (Figure 1B) being separated by separate layer 122.Although
Not showing in figs. 1 a and 1b, memory naked core 120 and controller naked core 130 are formed naked
Naked core bond pad on the upper surface of core, and substrate 110 is formed with connecing on the upper surface of substrate 110
Touch pad.Wire bonding 140 can be formed at naked core the 120th, 130 naked core bond pad and substrate 110
Between engagement pad, the 120th, naked core 130 is electrically connected to substrate 110.For protection purposes, memory
Naked core 120 and controller naked core 130 are encapsulated in moulding compound 150.
Owing to electronic unit becomes less and runs under higher frequency, by electromagnetic interference (EMI) with penetrate
Noise and crosstalk that frequency interference (RFI) causes are of much attention.Electromagnetic radiation is by carrying Rapid Variable Design
The circuit transmission of signal, as the accessory substance of its conventional operation.Such electromagnetic radiation causes to it
EMI and/or RFI of his circuit, causes less desirable interference or noise.
Make in transmission and the reception to shielding EMI and/or RFI of semiconductor package body rank
Effort.For example, such as the common manufacturing method of Fig. 2 and Fig. 3 A-3G can be passed through, by EMI screen layer
Put on as shown in Figure 1A and 1B with the single semiconductor device of packaging body form.Fig. 2 is to manufacture
There is the flow chart of the method for the Conventional semiconductor devices of EMI shielding, and Fig. 3 A-3G is at Fig. 2
The diagrammatic side view of the semiconductor device of the different phase of the manufacture method illustrating.First, attach at naked core
In step 210, as shown in Figure 3A, multiple semiconductor bare chip 330 are installed in and are arranged in substrate band 310
In each single substrate 320 on.In substrate band 310, single substrate 320 by be referred to as line
The reservation region of 315 separates.Then, in wire bonding step 220, as shown in Figure 3 B, multiple
Wire bonding 340 is formed as electrically connecting corresponding semiconductor bare chip 330 and substrate 320.Then, at mould
Moulding in step 230, as shown in Figure 3 C, moulding compound 350 is formed above whole substrate band 310, with
Encapsulation semiconductor bare chip 330 and wire bonding 340.Then in singulation step 240, such as Fig. 3 D
Shown in, by cutting through moulding compound 350 between adjacent semiconductor devices 360 and substrate 320,
Substrate band 310 after encapsulation is separated into the separate semiconductor device 360 of singualtion with the form of packaging body.
Then, attach in step 250 at packaging body, as shown in FIGURE 3 E, such as by using two-sided tape (not
Illustrate), the semiconductor device 360 of the form of multiple packaging bodies is transferred and is attached to common carrier 370
On.Then in EMI application step 260, as illustrated in Figure 3 F, being exposed of semiconductor device 360
Outer surface be coated with the EMI screen layer 380 being made of an electrically conducting material.Then in packaging body release steps
In 270, there is the separate semiconductor device 360 of EMI screen layer 380 carrier 370 from below and discharge,
For further technique.Such common manufacturing method has as a drawback that, such as due to packaging body level
Other places bring inefficient of reason and the two-sided tape for example carrying out use in comfortable packaging body attaching step 250
Additional pollution.Other details of this conventional method are in WO2013/086741 and WO2013/159307
Describing, entire contents is incorporated herein by.
Technology contents
At an aspect of this technology, semiconductor device includes: substrate, including on a surface of a substrate
At least one is grounded engagement pad；At least one semiconductor bare chip, on a surface of a substrate；Moulding compound, envelope
Fill at least one semiconductor bare chip；Electromagnetic interference (EMI) screen layer, at least partly covers moulding compound
Outer surface；And conductive member, it is formed at surface, be encapsulated in moulding compound.Conductive member has
Having the first end and second end relative with the first end, the first termination is combined in ground connection engagement pad, the second end
Electromagnetic interference shield layer on the surface of the moulding compound terminating in surface.
In an embodiment, conductive member includes at least one conductive lead wire, the first end lead-in wire of conductive lead wire
It is bonded in ground connection engagement pad and the second end of conductive lead wire electrically and physically contacts with electromagnetic interference
Screen layer.Conductive lead wire has arc.Conductive member includes more than one conductive lead wire, multiple conductions
The respective second end in contact electromagnetic interference shield layer of each of lead-in wire.
Or, conductive member includes at least one bus, and the part of the first end of bus is bonded on
Ground engagement pad on and bus second end electricity ground and physically contact with electromagnetic interference shield layer.Bus has
Have " C " shape or serpentine.
In an embodiment, conductive member includes silver alloy, gold, aluminium or copper.EMI screen layer is continuous
Layer or grid.EMI screen layer includes silver alloy, copper or gold.
In an embodiment, it is grounded the corner that engagement pad is positioned at substrate.This substrate is additionally included in the surface of substrate
The ground connection conduction interbed of lower section, this ground connection conduction interbed is electrically connected to be grounded engagement pad, and electromagnetic interference
Screen layer electrically and physically contacts with ground connection conduction interbed.
At an aspect of this technology, disclose the method manufacturing the semiconductor device using substrate band.Base
Strip has and includes first substrate and the second substrate adjacent with first substrate, and first substrate has first
The first ground connection engagement pad on the surface of substrate, second substrate has on the surface of second substrate second
Ground connection engagement pad.First ground connection engagement pad is adjacent with the second ground connection engagement pad.The method includes: arranges and leads
Electric components, above bridge joint side on the first substrate and second substrate, the first termination of conductive member is bonded to this
Second termination of the first ground connection engagement pad and conductive member is bonded to the second ground connection engagement pad；Encapsulate the first half
Conductor naked core, the second semiconductor bare chip and conductive member are in moulding compound；At first substrate and second substrate
Between form groove, thus separate leading on the sidewall of conductive member and the groove being exposed in moulding compound
The smooth end of two of electric components；Electromagnetic interference (EMI) screen layer is applied at least to include the side of groove
On the surface being exposed of the moulding compound of wall, thus physically smooth with electric contact conductive member two
End；And it by forming the fluting extending from this groove, is kept completely separate first substrate and second substrate.
In an embodiment, first cutting tool with the first width is used to form groove；And make apparatus
The second cutting tool having the second width less than the first width is kept completely separate first substrate and second substrate.
In an embodiment, conductive member includes at least one conductive lead wire.The method is additionally included in arrangement and leads
Before electrical lead, the surface of first substrate is arranged at least one first semiconductor bare chip, and
At least one second semiconductor bare chip is arranged on the surface of two substrates.Conductive lead wire is for electrical connection first
Semiconductor bare chip and the same lead-in wire of first substrate and electrical connection the second semiconductor bare chip and second substrate
Bonding technology is arranged.Or, conductive member includes bus, and arrange the first semiconductor bare chip and
Before second semiconductor bare chip, with this bus of surface mounting technique (SMT) technology arrangement.By spattering
Penetrate or plating process applies this electromagnetic interference shield layer.
Brief description
Figure 1A and Figure 1B is the diagrammatic side view of Conventional semiconductor devices.
Fig. 2 is the flow chart of the manufacture method of the Conventional semiconductor devices with EMI screen layer.
Fig. 3 A to Fig. 3 G is showing of the semiconductor device of the different step in the manufacture method shown in Fig. 2
Meaning side view.
Fig. 4 is the system of the semiconductor device with EMI screen layer of an embodiment according to this technology
Make the flow chart of method.
Fig. 5 A to Fig. 5 H is showing of the semiconductor device of the different step in the manufacture method shown in Fig. 4
Meaning side view.
Fig. 6 A to Fig. 6 C is showing of three embodiments of the semiconductor device of the step illustrating in figure 5d
Meaning side view.
Fig. 7 A and Fig. 7 B is putting of two embodiments of the semiconductor device of the step illustrating in fig. 5h
Big diagrammatic side view.
Fig. 8 A and Fig. 8 B is two enforcements of the conductive member of the bus form according to this technology respectively
The perspective illustration of example.
Fig. 9 A to Fig. 9 H is Fig. 8 A of the different step being shown with the manufacture method that figure 4 illustrates
The diagrammatic side view of the semiconductor device of the bus illustrating.
Figure 10 A and Figure 10 B is two embodiments of the semiconductor device in the stage shown in Fig. 9 H
Signal enlarged side view.
Figure 11 A, Figure 11 B and Figure 11 C are the semiconductor device of an embodiment according to this technology respectively
Schematic plan view and two diagrammatic side view.
Figure 12 A, Figure 12 B and Figure 12 C are the semiconductor of another embodiment according to this technology respectively
The schematic plan view of device and two diagrammatic side view.
Figure 13 A and Figure 13 B is two of the semiconductor device of the further embodiment according to this technology and shows
Meaning side view.
Figure 14 A and Figure 14 B is two of the semiconductor device of the further embodiment according to this technology and shows
Meaning side view.
Detailed description of the invention
Describe referring now to Fig. 4 to 14B and relate to semiconductor device, substrate, substrate band and semiconductor dress
The embodiment of the manufacture method put.It is appreciated that this technology can be embodied in many different forms and should not
It is considered limited to embodiments described herein.But, these embodiments are provided so that the disclosure will
It is abundant and complete, and this technology is entirely delivered to those skilled in the art.This technology is intended to cover
Covering replacement, modification and the equivalent of these embodiments, these embodiments are included in by claims
In the scope and spirit of this technology defining.In addition, in the appended detailed description of this technology, elaborate
Many specific details, to provide the complete understanding of this technology.But, for those skilled in the art
Speech is it is clear that this technology can be implemented in the case of not having such specific detail.
At this use term "left", "right", " top ", " bottom ", " on ", D score, " vertically " and/
Or " level " is only for convenient and illustration purpose, it is not intended that limit description of the invention, because institute
The project quoted can change in position.And, as used herein, " one " is also intended to include list
Number and the form of plural number, unless content clearly demonstrates really not so.Term " substantially ", " approx "
And/or " about " be meant that fixed yardstick or parameter can in order to give application and in acceptable manufacture
Tolerance changes.In one embodiment, can accept manufacture tolerance is ± 0.25%.
In all the drawings, same or like component marks in a like fashion, has identical
Rear two digits.
The manufacture of the semiconductor device of the embodiment according to this technology is described below with reference to Fig. 4 to Figure 10 B
Method.Fig. 4 is the manufacture of the semiconductor device with EMI screen layer of the embodiment according to this technology
Method.Fig. 5 A to Fig. 5 H is the semiconductor device of the different step in the manufacture method shown in Fig. 4
Diagrammatic side view.
As shown in Figure 4, the step 410 that the method for this semiconductor device starts from preparing substrate band is manufactured.
For example, as shown in Figure 5A, substrate band 500 include first substrate 510 and with this first substrate 510 phase
Adjacent second substrate 520.First substrate 510 and second substrate 520 are by being also generally referred to as ruling 505
Predetermined reservation region separate.Each substrate can include at least one ground connection on the upper surface of this substrate
Engagement pad.Ground connection engagement pad herein refers to the engagement pad electrically connecting with ground level.For example, such as Fig. 5 A
Shown in, first substrate 510 has the first ground connection engagement pad 512 on the upper surface of this first substrate 510,
And second substrate 520 has the second ground connection engagement pad 522 on the upper surface of this second substrate 520.
One of one of first ground connection engagement pad 512 adjacent second ground engagement pad 522 in position.Each
Substrate may also comprise engagement pad at least one on the upper surface being positioned at substrate.For example, first substrate 510
Including engagement pad 514 at least one, and second substrate 520 includes engagement pad 524 at least one.
Substrate band 500 and the substrate in this substrate band 500 are only illustrated by way of example, and in other embodiments
In, the construction of each substrate on substrate band, quantity and arrangement can be different.For example, such as Fig. 6 A extremely
Shown in the plane of Fig. 6 C, substrate band 600 can include being arranged in matrix by line 605 separation
Multiple substrates 610.Ground connection engagement pad 612 (being only labelled with one of them) in each substrate 610
It is positioned at the respective corner of substrate 610.In other embodiments, the ground connection in each substrate 612 connects
Touch pad may be alternatively located at the position different from the corner shown in Fig. 6 A-6C, its along the periphery of substrate at base
On the upper surface of plate.
Returning to reference to Fig. 5 A, substrate band 500 can be lead-in wire strip, such as flexible printed circuit board
(FPCB), this flexible printed circuit board has dielectric core and the conductive pattern in upper and lower both sides.Core can
To be formed by various dielectric materials, such as pi lamination, include FR4 and FR5 epoxy resin,
Amine triazine (BT) etc..In an alternate embodiment, this core can be ceramic or organic.Additionally, base
Strip 500 is additionally may included in the ground connection conduction interbed 530 below the upper surface of this substrate band 510, with
It is mutually coupled, respectively the first ground mat 512 and the second ground mat 522 electrically.
Then, in the naked core attachment process shown in Fig. 5 B, at least one first semiconductor bare chip 516
It is directed at first substrate 510, and use naked core attaching film (DAF) layer 515 to be arranged in the first base
On the surface of plate 510, naked core attaches film (DAF) layer 515 and is fixed to the first semiconductor bare chip 516
First substrate 510.Similarly, at least one second semiconductor bare chip 526 is directed at second substrate 520,
And use naked core attaching film (DAF) layer 525 to be arranged on the surface of second substrate 520, naked core
Attach film (DAF) layer 525 and second semiconductor bare chip 526 is fixed to second substrate 520.Then,
In the technique of the wire bonding shown in Fig. 5 C, wire bonding 518 electrically connects the first semiconductor bare chip 516
With first substrate 510, and wire bonding 528 electrically connects the second semiconductor bare chip 526 and second substrate
520.Above naked core attach step and wire bonding step can use well known to those skilled in the art arbitrarily
Naked core attaches technology and Wire Bonding Technology, will not be described in further detail.
Then, in the step 420 arranging conductive member, conductive member is arranged as bridging adjacent one another are
First substrate and second substrate above.First termination of conductive member is bonded to the first ground connection engagement pad, and
The second relative termination is bonded to the second ground connection engagement pad adjacent with the first ground connection engagement pad.Such as Fig. 5 D institute
Showing, this conductive member 540 is one section of arc conductive lead wire, by lead-in wire well known by persons skilled in the art
Bonding method, its first termination is combined in the first ground connection engagement pad 512 and the second end 522 is bonded on phase
In adjacent second ground connection engagement pad.Therefore the wire bonding being formed at each ground connection engagement pad can have this area skill
Any wire bonding structure known to art personnel, such as ball bonding, seam bonding (stitch bond) or
Seam bonding on projection.Conductive lead wire 540 can include gold thread, aluminum steel, copper cash or silver alloy wire.
The camber of adjustable conductive lead wire 540 in the technique of wire bonding, to guarantee the good of bonding wire
Mechanical strength and stability, for bearing the potential impact in the subsequent technique of such as moulding technology.
In the case of the conductive lead wire that conductive member is shown in Fig. 5 D, the step of arrangement conductive lead wire
440 can be at same lead-in wire in the same lead key closing process of electrical connection semiconductor bare chip and counterpart substrate
Bonding apparatus performs.In the case, output and the efficiency of this manufacture method can be improved.Or,
Can perform to arrange that conduction is drawn before arranging the first semiconductor bare chip 516 and the second semiconductor bare chip 526
Line.
As shown in Figure 6A, conductive member 640 can include the line direction (figure being placed along substrate band 600
X direction shown in 6A) two of two adjacent substrate 610 adjacently single between engagement pad
Conductive lead wire.Or, as shown in Figure 6B, conductive member 640 can include being arranged in two adjacent substrate
Between two of 610 adjacently engagement pad 612 and along substrate band 600 line direction arrangement many
Individual conductive lead wire.Conductive lead wire 620 can have arc as shown in Figure 5 D, its have identical camber or
The different camber of person.Or, as shown in Figure 6 C, conductive member 640 may also comprise and is placed along substrate
Two of two adjacent substrate 610 of the column direction (the y direction shown in Fig. 6 A) with 600 adjacent
Single conductive lead wire between ground engagement pad 612.Conductive lead wire 640 is only illustrated by way of example, at other
In embodiment, the respective conductive lead wire quantity on substrate band and arrangement can be different.
Then, it in molding step 430, as shown in fig. 5e, is arranged on the surface of substrate band 500
The semiconductor bare chip including the first semiconductor bare chip the 516th, the second semiconductor bare chip 526 and conduction structure
Part 540 is encapsulated in moulding compound 550.Molding step 430 can use well known to those skilled in the art
Arbitrary mould molding technology, will not be described in further detail.
Then, in the step 440 separating conductive member, groove 560 is on the direction along line 505
It is linearly formed in the region of the line 505 between first substrate 510 and second substrate 520.For example,
Substrate band 500 can be located at the encapsulation of the first cutting tool (not shown) being provided with such as diamond saw blade
On body buck, this first cutting tool is arranged on above platform and and scribe-lane alignment.Then cutting work is reduced
Tool is to cut moulding compound 500.In cutting technique, for cooling and the purpose cleaned, water flow jet arrives
On cutting surfaces so that the cutting surfaces of exposure is smooth clean.The minimum-depth of groove 560 depends on leading
Electric components 540, thus cut through conductive member 540, and the groove 560 being exposed in moulding compound 550
Sidewall on two of conductive member 540 smooth ends.The width of groove 560 is about 10-50 μm.With
The Conventional monolithic step illustrating in fig. 3d is different, and the groove 560 in Fig. 5 F extends only to substrate band
The upper surface of 500, without completely separable first substrate 510 and second substrate 520.So, substrate
Band 500 still keeps structural intergrity so that follow-up EMI coating process can in substrate band rank not
Being that independent packaging body rank performs, the degree of depth of groove 560 can be different from the degree of depth shown in Fig. 5 F.Example
As in other embodiments, groove 560 may also extend into leading below the upper surface of substrate band 500
Electricity interbed 530 level.As long as conductive member 540 can be separated, groove 560 also can have and is less than
The degree of depth shown in Fig. 5 F.
Then, in the step 450 of EMI coating, as illustrated in fig. 5h, by for example sputtering or plating
Layer process, electromagnetic interference (EMI) screen layer 570 is applied at least to include the sidewall of groove 560
On the surface being exposed of moulding compound 550, thus contact physically and electrically the two of conductive member 540
Individual smooth end.For example, substrate band 500 is placed in the process chamber, be then made of copper, thickness about
EMI screen layer 570 for 2-5 μm is applied by sputtering technology, produces on the surface of moulding compound 500
Smooth and firm EMI shielding.So, EMI screen layer 570 is electrically connected via conductive member 540
It is connected to be grounded engagement pad 512 and 522, thus ground connection is used for arranging EMI shielding.Electromagnetic interference (EMI)
Screen layer 570 can be made up of other conductive materials, for example silver alloy, gold, copper or aluminium.Owing to dividing
After separating process, the surface being exposed of the smooth end of conductive member 540 is smooth clean, follow-up applying
EMI screen layer 570 and conductive member 540 have good Ohmic contact.Electromagnetic interference (EMI) shields
Layer 570 can have various construction, for example, cover pantostrat or the grid of the whole outer surface of moulding compound.
Finally, at singulation step 460, as illustrated in fig. 5h, first substrate 510 and second substrate 520
It is kept completely separate by forming fluting 580, there is with singualtion the semiconductor dress of EMI screen layer 570
Put.As shown in the zoomed-in view of Fig. 7 A and Fig. 7 B, fluting 780 is formed at first substrate 710 He
Between second substrate 720.For example, substrate band 500 is arranged on the previous steps 440 separating conductive member
On the identical packaging body buck of middle use.This packaging body buck is provided with the second cutting tool (not shown),
Alignment according to step 440 is arranged, at groove 760s and at first substrate 710 and second substrate 720
Between scribe-lane alignment so that fluting 780 aligns with groove 760, and from slot 760 bottom prolong
Stretch.Width for forming the second cutting tool of fluting 780 is less than for forming the first of groove 760
The width of cutting tool so that the width of fluting 780 is less than the width of groove 760.In the case,
In cutting technique, the second cutting tool will not contact and damage on the sidewall being deposited on groove 760
EMI screen layer 770.In the case that substrate band is thin, the such as thickness of substrate band be about 100 μm or
In the case of person 130 μm, groove 760 extends only to the surface of substrate band as shown in Figure 7 A, to protect
Hold the mechanical strength of substrate band, in order to process.So, EMI screen layer 770 is only via conductive member
740 ground connection.As comparison, as shown in Figure 7 B, in the case of substrate tape thickness, such as substrate band
Thickness be about 170 μm or 210 μm or above in the case of, groove 760 may be further extended
Level (for example, the lower face 70 μm at substrate band of the ground connection interbed 730 of the lower face of substrate band
The degree of depth).EMI screen layer 770 is grounded via conductive member 740 and ground connection interbed 730 simultaneously, enters
One step improves the reliability of EMI shielding.
An embodiment according to this technology, EMI screen layer can be in substrate band rank before singualtion
Apply.For keeping the structural intergrity of substrate band, only part cutting substrate band, to be formed at adjacent substrate
Between groove.But, it due to the reduction day by day of the thickness of substrate band, is difficult to control groove and extends to base
The degree of depth of the ground connection conduction interbed below the upper surface of strip makes the EMI screen layer of follow-up applying possible
The ground connection conduction interbed that contact exposes, and maintain the mechanical strength of substrate band.In the case, conduct electricity
Component is formed at surface, and its first end engages in ground connection engagement pad on a surface of a substrate, and its
The second relative end lifts and contacts EMI screen layer.So, EMI screen layer can be via conduction
Component is reliably grounded.
In the embodiment above, conductive member can include at least one conductive lead wire.This technology is not limited to this.
For example, conductive member can be bus, for example, use in surface mounting technique (SMT) technique
Copper current divider or copper jumper.Fig. 8 A and Fig. 8 B is that the signal of two embodiments of this bus is saturating
View.Two bus are respectively provided with warp architecture, and the Part I 801 of bus is in the first end, conduction
The Part II 802 of bar is at the second end, and the Part III 803 of bus is at the first end 801 and
Between two ends 802 and above the first end 801 and the second end 802.Bus has the cross section shape of rectangle
Shape.Bus can be made up of other conductive materials different from copper, such as silver alloy or gold.Bus is only
Being illustrated by way of example, the construction of bus can be different in other embodiments.
Fig. 9 A to Fig. 9 H be shown with the bus shown in Fig. 8 A semiconductor device at Fig. 4
Shown in the diagrammatic side view of different step of manufacture method.Embodiment shown in Fig. 9 A to Fig. 9 H
Basic identical with the embodiment shown in Fig. 5 A to Fig. 5 H, except construction and the arrangement conduction of conductive member
Outside the opportunity of component.Therefore, only will be described with the difference with regard to conductive member, and herein no longer
Repeat other aspects of embodiment.
As shown in Figure 9 B, in the step arranging conductive member, the bus 940 illustrating in fig. 8 a
It is arranged as bridge joint above first substrate 910 adjacent one another are and second substrate 920.Conductive member 940
Part I at the first end is bonded in the first ground connection engagement pad 912, at the second of the second relative end
Part is bonded in the second ground connection engagement pad 922 adjacent with the first ground connection engagement pad 912, and the 3rd
Part is across between first substrate 910 and second substrate 920 and at first substrate 910 and second substrate
Above in the of 920.As shown in Fig. 9 C and Fig. 9 D, arrange that the step of bus 940 attaches step prior to naked core
And lead key closing process, typically perform with surface mounting technique (SMT) technique.For example, by
Surface mounting technique (SMT) technique is commonly referred to as picking up and placing machine of " chip mounter ", leads
Electricity bar 940 is placed such that Part I 941 is grounded in engagement pad 912 and Part II 942 first
In the second ground connection engagement pad 922.Due in SMT technique, bus 940 to substrate with very
Big impact, attaches step prior to the naked core as shown in Fig. 9 C and Fig. 9 D and lead key closing process performs
Arrange bus 940 step, thus avoid arrange bus 940 on tape have parts bear
Face rings.Each ground mat can be coated with the solder of such as silver alloy, and bus 940 is via follow-up time
Stream technique is joined on ground mat.Can be by the those skilled in the art for example being pasted by conducting paste
Known other joint technologies any perform joint, will not be described in further detail.
As shown in fig. 9f, after the molding process, groove 960 is formed at first substrate 960 and the second base
Between plate 902, on the sidewall with the conductive member 940 in splitting die plastics 950 and exposure groove 960
Two of conductive member 940 smooth ends.With in the previous embodiments there is little circular section shape
Conductive lead wire compare, the bus in the present embodiment has rectangular cross sectional shape, and it is exposed to groove 960
Sidewall on contact area bigger.Thus, in the follow-up EMI application step shown in Fig. 9 G,
EMI screen layer 970 has the contact area bigger with conductive member 940, therefore realizes more reliable connecing
Ground effect.
As shown in the zoomed-in view of Figure 10 A and 10B, recessed by for example using width to be less than for being formed
Second cutting tool (not shown) of the width of the first cutting tool of groove 1060, fluting 1080 formation
Between first substrate 1010 and second substrate 1020, extend from groove 1060.In the case,
In singulation step, the second cutting tool will not contact and damage on the sidewall being deposited on groove 1060
EMI screen layer 1070.In the case that substrate band is thin, such as thickness is 100 μm or 130 μm
In the case of, groove 1060 extends only to the surface of substrate band as shown in Figure 10 A, to keep substrate
The mechanical strength of band, in order to process.So, EMI screen layer 1070 is only via conductive member 1040
Ground connection.As comparison, as shown in Figure 10 B, in the case of substrate tape thickness, such as thickness is 170 μm
Or 210 μm or above in the case of, groove 1060 may be further extended under the surface of substrate band
The level of the ground connection interbed 1030 of side.EMI screen layer 1070 is simultaneously via conductive member 1040 with connect
Ground interbed 1030 is grounded, and improves the reliability of EMI shielding further.
Manufacture in order to top method half according to this technology will be further described with reference to Figure 11 A to Figure 14 B
The embodiment of conductor device.It should be noted that for purposes of clarity, moulding material and EMI screen layer are not
It is shown in the plane of Figure 11 B and Figure 12 B.
Figure 11 A is the schematic plan view of the semiconductor device of the embodiment according to this technology, and Figure 11 B
It is the diagrammatic side view obtaining from y and the x direction shown in Figure 11 A respectively with Figure 11 C.Such as Figure 11 A
To shown in Figure 11 C, semiconductor device includes substrate 1110；At least one semiconductor bare chip 1116, example
It such as memory naked core or controller naked core, is arranged on the upper surface of substrate 1110；Moulding compound 1150,
Encapsulate at least one semiconductor bare chip 1116；With electromagnetic interference (EMI) screen layer 1170, at least partly
Cover the outer surface of moulding compound 1150.Substrate 1110 includes at least one ground mat 1114, is positioned at for example
Corner on the surface of substrate 1110.Semiconductor device also includes at least one conductive member, is formed
It above substrate 1110, is encapsulated in moulding compound 1150.Conductive member 1140 have the first end and
Second end, this first termination is combined in ground connection engagement pad 1112, and this second end terminates on substrate 1110
EMI screen layer 1170 on the side surface of the moulding compound 1150 of side.It should be noted that EMI screen layer 1170
Not shown in Figure 11 C, with the conductive member that is shown clearly on the side surface of moulding compound 1150
Second end.As shown in Figure 11 B, conductive member 1140 is the wall scroll conductive lead wire with arc.Partly lead
Body device can include the more than one conductive member 1140 being arranged in each ground connection engagement pad 1112.Connect
The quantity of ground engagement pad 1112 and conductive member 1140 and arrangement only illustrate, in an illustrative manner at other
Embodiment can be changed.
Semiconductor device may also comprise wire bonding 1118, is used for electrically connecting semiconductor bare chip the 1116th, base
Plate 1110 and the passive device (not shown) being arranged on substrate 1110.
Semiconductor device may additionally include the ground connection conduction interbed 1130 of the lower face of substrate 1110.Should
Ground connection conduction interbed 1130 is electrically connected to be grounded engagement pad 1112.EMI screen layer 1170 is electrically and thing
Ground connection conduction interbed 1130 on the side surface of substrate 1110 for the reason ground contact.Or, EMI screen layer
On 1170 outer surfaces that can be made only in moulding compound 1150, and do not extend to below substrate surface.EMI
Screen layer 1170 can have various construction, for example, cover the pantostrat of the whole outer surface of moulding compound 1150
Or grid.
Conductive member shown in Figure 11 A to Figure 11 C is single conductive lead wire.Or, conduction structure
Part can include a plurality of conductive lead wire.As shown in Figure 12 A to Figure 12 C, conductive member 1240 includes multiple
Conductive lead wire, includes three conductive lead wires in this example.First termination of every conductive lead wire is combined in and connects
In ground engagement pad 1212, the second end in contact EMI screen layer 1240.Second end of conductive lead wire is at molding
Identical height is may extend on the side surface of material 1259, or as shown in Figure 12 A and Figure 12 C,
Different height is may extend on the side surface of moulding compound 1259.Owing to more than one bonding wire is sudden and violent
Being exposed on the side surface of moulding compound 1250, EMI screen layer 1270 has bigger with conductive member 1240
Contact area, thus realize the effect of more reliable ground connection.
Figure 13 A to Figure 14 B is the enforcement according to this technology using the bus shown in Fig. 8 A and 8B
The diagrammatic side view of two semiconductor devices of example.Half of embodiment according to Figure 13 A to 14B
Conductor device is substantially identical with shown in Figure 11 A to 12B, in addition to conductive member.Therefore, only
Will be described with the difference with regard to conductive member, and other aspects of embodiment are not repeated herein.
As illustrated in figures 13 a and 13b, conductive member includes at least one conduction with " C " shape shape
Bar 1340, it is bonded in ground connection engagement pad 1312 at the Part I of the first end, and its second end is electrical
Ground and physically contact with EMI screen layer 1370.As a comparison, as shown in figs. 14 a-b, conduct electricity
Component includes that at least one has the bus of serpentine shape 1440, and it is at the Part I of the first end
Being bonded in ground connection engagement pad 1412, its second end electrically and physically contacts with EMI screen layer 1470.
According to this technology, before singualtion, EMI screen layer can be applied in substrate band rank.For keeping
The integrality of substrate band, only part cutting substrate band, thus the groove being formed between adjacent substrate.So
And, it due to the reduction day by day of the thickness of substrate band, is difficult to control groove and extends to the upper surface at substrate band
The degree of depth of lower section ground connection conduction interbed makes the EMI screen layer of follow-up applying may contact the ground connection exposing
Conduction interbed, and maintain the mechanical strength of substrate band.In the case, semiconductor device also includes leading
Electric components, its first end engages in ground connection engagement pad on a surface of a substrate, and the second relative end is at base
Lift above plate and contact EMI screen layer.So, EMI screen layer can via conductive member
By ground ground connection.
The foregoing detailed description of the present invention is for purpose of illustration and description.It is not intended to exhaustive or limit this
Invention is to disclosed accurate form.In the above teachings, many modifications and variations are possible.Choosing
Select described embodiment so that the principle of this technology and the application of its reality are most preferably described, so that
Those skilled in the art can be in various embodiments and by being suitable for each of contemplated particular use
Plant modification ground and most preferably use this technology.The scope of the present invention is intended to be defined by the appended claims.
Claims (21)
1. a semiconductor device, comprising:
Substrate, including at least one ground connection engagement pad on a surface of the substrate；
At least one semiconductor bare chip, on a surface of the substrate；
Moulding compound, encapsulates this at least one semiconductor bare chip；
Electromagnetic interference (EMI) screen layer, at least partly covers the outer surface of this moulding compound；And
Conductive member, is formed at this surface, is encapsulated in this moulding compound, and has the first end
And second end relative with this first end, this first termination is combined in this ground connection engagement pad, this second end
This electromagnetic interference shield layer on the surface of the moulding compound terminating in this surface.
2. semiconductor device as claimed in claim 1, wherein this conductive member includes that at least one conducts electricity
Lead-in wire, the first end wire bonding of this conductive lead wire in this ground connection engagement pad and this conductive lead wire the
Two ends electrically and physically contact with this electromagnetic interference shield layer.
3. semiconductor device as claimed in claim 2, wherein this conductive lead wire has arc.
4. semiconductor device as claimed in claim 3, wherein this conductive member includes more than one leading
Electrical lead, this electromagnetic interference shield layer of respective second end in contact of each of the plurality of conductive lead wire.
5. semiconductor device as claimed in claim 1, wherein this conductive member includes that at least one conducts electricity
Bar, the part of the first end of this bus is bonded in this ground connection engagement pad, and the second end of this bus
Electricity ground and physically contact with this electromagnetic interference shield layer.
6. semiconductor device as claimed in claim 5, wherein this bus has " C " shape or " S "
Shape.
7. semiconductor device as claimed in claim 1, wherein this conductive member include silver alloy, gold,
Aluminium or copper.
8. semiconductor device as claimed in claim 1, wherein this ground connection engagement pad is positioned at the angle of this substrate
Portion.
9. semiconductor device as claimed in claim 1, wherein this substrate is additionally included in the surface of this substrate
The ground connection conduction interbed of lower section, this ground connection conduction interbed is electrically connected to this ground connection engagement pad, and this electromagnetism
Interference shielding layer electrically and physically contacts with this ground connection conduction interbed.
10. semiconductor device as claimed in claim 1, wherein this electromagnetic interference shield layer is pantostrat
Or grid.
11. semiconductor devices as claimed in claim 1, wherein this electromagnetic interference shield layer includes silver conjunction
Gold, copper or gold.
12. 1 kinds use the method that semiconductor device prepared by substrate band, and this substrate band has and includes the first base
Plate and the second substrate adjacent with this first substrate, this first substrate has on the surface of this first substrate
First ground connection engagement pad, this second substrate have on the surface of this second substrate second ground connection contact
Pad, this first ground connection engagement pad is adjacent with this second ground connection engagement pad, and the method includes:
Arrange conductive member, bridge above this first substrate and above second substrate, this conductive member
First termination is bonded to the second termination of this first ground connection engagement pad and this conductive member and is bonded to this and second connects
Ground engagement pad；
Encapsulate this first semiconductor bare chip, this second semiconductor bare chip and this conductive member in moulding compound；
Form groove between this first substrate and this second substrate, thus separate this conductive member and sudden and violent
The smooth end of two of the conductive member being exposed on the sidewall of the groove in this moulding compound；
Electromagnetic interference (EMI) screen layer is applied at least to include the quilt of the moulding compound of the sidewall of this groove
On the surface exposing, thus physically contact that two of this conductive member are smooth to hold with electric；And
It by forming the fluting extending from this groove, is kept completely separate this first substrate and this second substrate.
13. methods as claimed in claim 12, wherein this conductive member includes that at least one conduction is drawn
Line, this conductive lead wire has the arc above this first substrate and second substrate.
14. methods as claimed in claim 13, before being additionally included in this conductive lead wire of arrangement, this
At least one first semiconductor bare chip is arranged on the surface of one substrate, and on the surface of this second substrate
Arranging at least one second semiconductor bare chip, wherein this conductive lead wire is being used for electrically connecting this first semiconductor
Naked core and this first substrate and the same lead-in wire electrically connecting this second semiconductor bare chip and this second substrate
Bonding technology is arranged.
15. methods as claimed in claim 12, wherein this conductive member includes at least one bus,
This bus has the Part I at its first end, the Part II at its second end and at first
Dividing the Part III between Part II, this Part I is bonded in this first ground connection engagement pad, should
Part II is bonded in this second ground connection engagement pad, and this Part III is at this first substrate and second substrate
Top.
16. methods as claimed in claim 15, are additionally included in and arrange at least on the surface of this first substrate
One the first semiconductor bare chip, and on the surface of this second substrate, arrange at least one second semiconductor
Naked core, wherein before arranging this first semiconductor bare chip and this second semiconductor bare chip, installs with surface
This bus of technology (SMT) technology arrangement.
17. methods as claimed in claim 12, wherein this conductive member include silver alloy, gold, aluminium or
Person's copper.
18. methods as claimed in claim 12, wherein this first ground connection engagement pad is positioned at this first substrate
Corner, and this second ground connection engagement pad be positioned at this second substrate corner.
19. methods as claimed in claim 12, wherein use first cutting tool with the first width
Form this groove；And use second cutting tool with the second width less than this first width complete
Separate this first substrate and this second substrate.
20. methods as claimed in claim 12, wherein this bus is additionally included in this first substrate and
Below two substrates and be electrically connected to this first ground connection engagement pad and second ground connection engagement pad ground connection conduction
Interbed,
This groove extends to this ground connection conduction interbed；And
The electromagnetic interference shield layer of this applying electricly and physically contacts with this ground connection conduction interbed.
21. methods as claimed in claim 12, wherein apply this electromagnetism by sputtering or plating process
Interference shielding layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510088691.XA CN105990317A (en) | 2015-02-25 | 2015-02-25 | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510088691.XA CN105990317A (en) | 2015-02-25 | 2015-02-25 | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105990317A true CN105990317A (en) | 2016-10-05 |
Family
ID=57037791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510088691.XA Pending CN105990317A (en) | 2015-02-25 | 2015-02-25 | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990317A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507824A (en) * | 2017-09-13 | 2017-12-22 | 尚睿微电子（上海）有限公司 | A kind of encapsulating structure with electro-magnetic screen function and preparation method thereof |
| WO2018224051A1 (en) * | 2017-06-08 | 2018-12-13 | 唯捷创芯(天津)电子技术股份有限公司 | Anti-electromagnetic interference radio frequency module and implementation method therefor |
| CN109727928A (en) * | 2017-10-30 | 2019-05-07 | 长鑫存储技术有限公司 | Semiconductor package and manufacturing method with electromagnetic interference shield |
| CN112385141A (en) * | 2018-07-10 | 2021-02-19 | 华为技术有限公司 | Improved harmonic termination integrated passive device |
| CN112992707A (en) * | 2021-04-29 | 2021-06-18 | 甬矽电子(宁波)股份有限公司 | Electromagnetic shielding structure manufacturing process and electromagnetic shielding structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1856878A (en) * | 2003-09-25 | 2006-11-01 | 飞思卡尔半导体公司 | Method of forming a semiconductor package and structure thereof |
| US7342303B1 (en) * | 2006-02-28 | 2008-03-11 | Amkor Technology, Inc. | Semiconductor device having RF shielding and method therefor |
| CN101276805A (en) * | 2007-06-15 | 2008-10-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure with electromagnetic interference shield function and manufacturing method thereof |
| CN101617400A (en) * | 2007-01-31 | 2009-12-30 | 富士通微电子株式会社 | Semiconductor device and manufacture method thereof |
| US20100207259A1 (en) * | 2008-02-05 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
| US7898066B1 (en) * | 2007-05-25 | 2011-03-01 | Amkor Technology, Inc. | Semiconductor device having EMI shielding and method therefor |
| CN102074552A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing methods thereof |
| US8008753B1 (en) * | 2008-04-22 | 2011-08-30 | Amkor Technology, Inc. | System and method to reduce shorting of radio frequency (RF) shielding |
| CN102244069A (en) * | 2011-06-13 | 2011-11-16 | 日月光半导体制造股份有限公司 | Semiconductor structure with concave part and manufacturing method thereof |
-
2015
- 2015-02-25 CN CN201510088691.XA patent/CN105990317A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1856878A (en) * | 2003-09-25 | 2006-11-01 | 飞思卡尔半导体公司 | Method of forming a semiconductor package and structure thereof |
| US7342303B1 (en) * | 2006-02-28 | 2008-03-11 | Amkor Technology, Inc. | Semiconductor device having RF shielding and method therefor |
| CN101617400A (en) * | 2007-01-31 | 2009-12-30 | 富士通微电子株式会社 | Semiconductor device and manufacture method thereof |
| US7898066B1 (en) * | 2007-05-25 | 2011-03-01 | Amkor Technology, Inc. | Semiconductor device having EMI shielding and method therefor |
| CN101276805A (en) * | 2007-06-15 | 2008-10-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure with electromagnetic interference shield function and manufacturing method thereof |
| US20100207259A1 (en) * | 2008-02-05 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
| US8008753B1 (en) * | 2008-04-22 | 2011-08-30 | Amkor Technology, Inc. | System and method to reduce shorting of radio frequency (RF) shielding |
| CN102074552A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing methods thereof |
| CN102244069A (en) * | 2011-06-13 | 2011-11-16 | 日月光半导体制造股份有限公司 | Semiconductor structure with concave part and manufacturing method thereof |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018224051A1 (en) * | 2017-06-08 | 2018-12-13 | 唯捷创芯(天津)电子技术股份有限公司 | Anti-electromagnetic interference radio frequency module and implementation method therefor |
| US11264335B2 (en) | 2017-06-08 | 2022-03-01 | Vanchip (Tianjin) Technology Co., Ltd. | Anti-electromagnetic interference radio frequency module and implementation method therefor |
| CN107507824A (en) * | 2017-09-13 | 2017-12-22 | 尚睿微电子（上海）有限公司 | A kind of encapsulating structure with electro-magnetic screen function and preparation method thereof |
| CN109727928A (en) * | 2017-10-30 | 2019-05-07 | 长鑫存储技术有限公司 | Semiconductor package and manufacturing method with electromagnetic interference shield |
| CN109727928B (en) * | 2017-10-30 | 2021-02-26 | 长鑫存储技术有限公司 | Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof |
| CN112385141A (en) * | 2018-07-10 | 2021-02-19 | 华为技术有限公司 | Improved harmonic termination integrated passive device |
| CN112385141B (en) * | 2018-07-10 | 2024-04-12 | 华为技术有限公司 | Improved harmonic termination integrated passive device |
| CN112992707A (en) * | 2021-04-29 | 2021-06-18 | 甬矽电子(宁波)股份有限公司 | Electromagnetic shielding structure manufacturing process and electromagnetic shielding structure |
| CN112992707B (en) * | 2021-04-29 | 2021-08-06 | 甬矽电子(宁波)股份有限公司 | Electromagnetic shielding structure manufacturing process and electromagnetic shielding structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102067310B (en) | Stacking of wafer-level chip scale packages having edge contacts and manufacture method thereof | |
| US10490478B2 (en) | Chip packaging and composite system board | |
| US6462273B1 (en) | Semiconductor card and method of fabrication | |
| CN101512762B (en) | Stackable packages for three-dimensional packaging of semiconductor dice | |
| US9299670B2 (en) | Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof | |
| CN103325779B (en) | Methods of making microelectronic packages | |
| CN103208487B (en) | Method and apparatus for relatively thin stack package structure | |
| KR101734882B1 (en) | Stackable molded microelectronic packages with area array unit connectors | |
| CN1937194A (en) | Method of making stacked die package | |
| CN105990317A (en) | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof | |
| US9761569B2 (en) | Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production thereof | |
| CN103229293A (en) | Semiconductor chip package, semiconductor module, and method for manufacturing same | |
| US10854557B2 (en) | Semiconductor device packaging with metallic shielding layer | |
| US20090321950A1 (en) | Stacked semiconductor package with localized cavities for wire bonding | |
| CN108695269A (en) | Semiconductor device packages and its manufacturing method | |
| KR20160135688A (en) | A thin sandwitch embedded package | |
| US11670600B2 (en) | Panel level metal wall grids array for integrated circuit packaging | |
| CN104094401B (en) | For the tail circuit connector of semiconductor device | |
| CN107622996A (en) | Three-dimensional high-density fan-out package structure and its manufacture method | |
| CN112768437B (en) | Multilayer stack packaging structure and preparation method thereof | |
| US20130009294A1 (en) | Multi-chip package having leaderframe-type contact fingers | |
| CN106409785A (en) | Thin type array plastic packaging part and production method thereof | |
| US11616017B2 (en) | Integrated circuit package structure, integrated circuit package unit and associated packaging method | |
| CN104008982B (en) | Chip packaging process and chip package | |
| JPS63204635A (en) | Memory module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161005 |