CN109727928B - Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof - Google Patents
Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof Download PDFInfo
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- CN109727928B CN109727928B CN201711041958.5A CN201711041958A CN109727928B CN 109727928 B CN109727928 B CN 109727928B CN 201711041958 A CN201711041958 A CN 201711041958A CN 109727928 B CN109727928 B CN 109727928B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure with electromagnetic interference shielding and a manufacturing method thereof. The package structure includes: a rewiring structure, an electromagnetic interference shielding structure, and a plurality of chips. The electromagnetic interference shielding structure has a sidewall frame portion and a top layer, the sidewall frame portion is directly formed on a metal pad on the rewiring structure. The manufacturing method comprises the following steps: and forming a rewiring structure, depositing a side wall frame part on a metal pad on the rewiring structure, molding and thinning the plastic package body to expose the top end of the side wall frame part, and depositing metal to form a top layer of the electromagnetic interference shielding structure. According to the electromagnetic interference shielding structure, the lower part of the side wall frame part is not connected by adopting the solder but directly formed on the metal pad, so that the short circuit caused by climbing of the solder, holes in the solder and the penetration of the solder into the rewiring structure is avoided.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor package structure with electromagnetic interference shielding and a manufacturing method thereof.
Background
In recent years, electronic products have become thinner and smaller, microelectronic packages have been developed to be smaller, higher speed, higher density and systematized, and System In Package (SIP) is also applied more and more in the field of semiconductor packaging. In the design of system-in-package (soc), Electromagnetic Interference (EMI) is an important consideration, especially for components sensitive to EMI and components generating EMI, and the EMI shielding problem needs to be considered in the package design. The package structure of the related art is provided with an emi shielding structure having a sidewall frame portion and connected to a pad of the rewiring structure by solder. However, during reflow, the solder under the side frame portion melts and climbs along the side frame portion, thereby causing a hole to be formed in the solder under the side frame portion. In addition, during the reflow soldering process, the redistribution structure generates thermal stress under the action of temperature to cause the redistribution structure to form micro-cracks, and the molten solder can diffuse into the redistribution structure along the micro-cracks and possibly cause the redistribution circuit to be short-circuited.
The above description is intended only to aid those skilled in the art in understanding the background of the invention and is not intended to be a representation that is known or suggested to those skilled in the art.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a chip stack three-dimensional package structure to solve or alleviate the problems in the prior art, and at least provide a useful choice.
Technical solution according to an embodiment of the present invention is achieved as described above, and according to an embodiment of the present invention, there is provided a semiconductor package structure including:
the rewiring structure is provided with a flip-chip terminal mounting surface, and a plurality of metal pads are formed on the flip-chip terminal mounting surface; and
the electromagnetic interference shielding structure comprises a side wall frame part and a top layer, wherein the side wall frame part is directly formed on the metal pad of the flip chip terminal mounting surface of the rewiring structure;
a plurality of chips flip-chip bonded to the flip-chip terminal mounting surface; and
a plastic package body formed on the flip chip terminal mounting surface to seal the side wall frame portion and the chip of the electromagnetic interference shielding structure;
the top layer is attached to the plastic package body and connected with the side wall frame portion, the top layer and the side wall frame portion form at least one shielding cavity, and at least one chip is arranged inside the shielding cavity.
In some embodiments, the top layer is directly connected to the top end of the sidewall frame portion exposed outside the plastic package body.
In some embodiments, the rewiring structure further has an external terminal mounting surface, and the semiconductor package structure further includes a plurality of external terminals disposed on the external terminal mounting surface.
In some embodiments, a plurality of passive devices are further disposed in the shielding cavities, and are disposed on the flip-chip terminal mounting surface through solder, and the passive devices are located in one of the shielding cavities.
In some embodiments, a thickness of the molding compound between a back side of the chip and the top layer of the emi shielding structure is greater than or equal to 5 μm.
A method for manufacturing a semiconductor package structure includes:
providing a first carrier, and forming a rewiring structure on the surface of the first carrier, wherein the rewiring structure is provided with a flip-chip terminal mounting surface, and a metal pad is formed on the flip-chip terminal mounting surface;
forming a first portion of an electromagnetic interference shielding structure on the rewiring structure, wherein the first portion comprises a sidewall frame portion of the electromagnetic interference shielding structure and is directly formed on the metal pad of the flip-chip terminal mounting surface of the rewiring structure;
flip-chip bonding a plurality of chips on the flip-chip terminal mounting surface;
forming a plastic package body on the flip chip terminal mounting surface to seal the side wall frame part and the chip of the electromagnetic interference shielding structure in a mold manner; and
the second part forming the electromagnetic interference shielding structure is arranged on the plastic package body, the second part comprises a top layer of the electromagnetic interference shielding structure, the top layer is attached to the plastic package body and connected with the side wall frame portion, the top layer and the side wall frame portion form at least one shielding cavity, and at least one chip is arranged inside each shielding cavity.
In some embodiments, the step of forming the second portion of the emi shielding structure further comprises:
thinning the plastic package body to expose the top end of the side wall frame part; and
depositing metal on the thinned surface to form the top layer of the EMI shielding structure;
the manufacturing method of the semiconductor packaging structure further comprises the following steps:
providing a second carrier, attaching to the top layer, while removing the first carrier;
forming a plurality of external terminals on the external terminal mounting surface exposed by the rewiring structure after the first carrier is removed; and
and performing singulation cutting to form a plurality of semiconductor packaging structures.
In some embodiments, in the step of thinning the plastic package body, the thickness of the plastic package body remaining on the back side of the chip is thinned to be greater than or equal to 5 μm.
In some embodiments, the sidewall frame portion is formed by a method of electroplating.
In some embodiments, the top layer is formed by sputtering.
In some embodiments, the emi shielding structure is made of metal, and the melting point of the metal is higher than the highest temperature of a reflow soldering process used for flip chip bonding the chip to the flip chip terminal mounting surface.
In some embodiments, the flip chip bonding step of the plurality of chips further comprises: and arranging a plurality of passive devices on the flip-chip terminal mounting surface, wherein the passive devices are positioned in one of the shielding cavities.
By adopting the technical scheme, the embodiment of the invention avoids the short circuit of the rewiring circuit caused by the climbing of the solder, the holes in the solder and the penetration of the solder into the rewiring structure.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the invention.
Fig. 3 is a manufacturing process of a semiconductor package structure according to an embodiment of the invention.
Reference numerals
100: embodiment 1 of the present invention;
110: a rewiring structure; 111: a flip-chip terminal mounting surface; 112: an external terminal mounting surface; 113: re-routing the circuit; 114: a first metal pad;
120: an electromagnetic interference shielding structure; 121: a sidewall frame portion of the electromagnetic interference shielding structure; 122: a top layer of an electromagnetic interference shielding structure; 123: a shielding cavity;
130: a chip; 131: carrying out wafer back; 132: a metal pad on the surface of the chip; 133: a flip chip terminal;
140: a passive device;
150: welding flux;
160: molding the body;
170: a second metal pad;
180: and an external terminal.
200: embodiment 2 of the present invention.
300: a manufacturing process of the semiconductor package structure according to embodiment 1 of the present invention;
301: a first dielectric layer; 302: a second dielectric layer; 303: gluing a film;
313A: a first layer of redistribution traces; 313B: a second layer of redistribution traces;
391: a first carrier; 392: a second carrier; 393: rubberized fabric.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the invention. As shown in fig. 1, the semiconductor package structure 100 includes: the rewiring structure 110, the emi shielding structure 120, the plurality of chips 130, the plurality of passive devices 140, the solder 150, the molding body 160, the plurality of second metal pads 170, and the plurality of external terminals 180.
The rewiring structure 110 includes: the flip-chip terminal mounting surface 111, the external terminal mounting surface 112, and the multilayer rewiring circuit 113 provided inside the rewiring structure 110 are formed such that a plurality of first metal pads 114 are formed on the flip-chip terminal mounting surface 111, a plurality of second metal pads 170 are formed on the external terminal mounting surface 112, and external terminals 180 are provided on the second metal pads 170.
The emi shielding structure 120 includes a sidewall portion 121 and a top layer 122, where the top layer 122 and the sidewall portion 121 form at least one shielding cavity 123, and at least one chip 130 is disposed inside each shielding cavity 123.
In one embodiment, a plurality of passive devices 140 are also disposed within the shielded cavities 123, the plurality of passive devices 140 being located in one of the shielded cavities 123.
The sidewall frame portion 121 is directly formed on the first metal pad 114 of the flip-chip terminal mounting surface 111, where "directly forming" refers to not connecting the sidewall frame portion 121 to the first metal pad 114 of the flip-chip terminal mounting surface 111 through solder or other substances, but directly forming the sidewall frame portion 121 on the first metal pad 114, for example, directly forming through a metal deposition method. The chip 130 is flip-chip bonded to the flip-chip terminal mounting surface 111, the passive device 140 is connected to the first metal pad 114 on the flip-chip terminal mounting surface 111 through the solder 150, the chip 130 and the passive device 140 are electrically connected to the second metal pad 170 on the external terminal mounting surface 112 and the external terminal 180 through the redistribution circuit 113, the second metal pad 170 may be Under Bump Metallurgy (UBM), and the external terminal 180 may be a solder ball. It should be noted that the first metal pads 114 under the sidewall frame portions 121 are not electrically connected to the redistribution traces 113. Note that the redistribution line 113 shown in fig. 1 is a schematic representation for the purpose of explanation only, and is not a specific connection method, and it is not understood that the connection method is limited to this connection method.
The plastic package body 160 is formed on the flip-chip terminal mounting surface 111, fills each shielding cavity 123, and seals the sidewall frame portion 121, each chip 130, and each passive device 140. The top layer 122 of the emi shielding structure 120 is attached to the molding compound 160 and connected to the sidewall frame portion 121, and in some embodiments, the top layer 122 is directly connected to the top end of the sidewall frame portion 121 exposed outside the molding compound 160 to form the emi shielding structure 120. Both the sidewall frame portion 121 and the top layer 122 of the emi shielding structure 120 are made of metal, and in order to avoid short circuit of the redistribution traces 113 caused by the metal of the sidewall frame portion 121 melting due to high temperature and overflowing into the redistribution traces 110 along with micro cracks of the redistribution traces, in a preferred embodiment, a metal with a high melting point and not melting at the high temperature of the reflow soldering, such as Cu, Al, etc., is selected.
In some embodiments, the thickness of the molding compound 160 between the back side 131 of the chip 130 and the top layer 122 of the emi shielding structure 120 is greater than or equal to 5 μm.
In other embodiments, the semiconductor package structure shown in fig. 1 may not include the passive device 140, but only include a plurality of chips 130, and the structure thereof is shown in fig. 2. The description of the same components in fig. 2 as those shown in fig. 1 can be referred to the description of fig. 1, and will not be repeated herein.
In addition, it should be noted that the emi shielding structure 120 may be in any shape, preferably in a frame-shaped structure, and a user may set the sidewall frame portion 121 at different positions on the flip-chip terminal mounting surface 111 according to the need to divide the shielding cavities 123 into different numbers, sizes and structures, so as to set the chips 130 in different numbers and sizes.
The invention also provides a method for manufacturing the semiconductor packaging structure. Fig. 3 is a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. As shown in fig. 3, in step S101, a first carrier 391 is provided, a first dielectric layer 301 is deposited on the surface of the first carrier 391, and a first redistribution layer 313A is formed on the surface of the first dielectric layer 301. In step S102, a second dielectric layer 302 is deposited on the surface of the first dielectric layer 301 and covers the first redistribution layer 313A, and a second redistribution layer 313B is deposited on the surface of the second dielectric layer 302. In step S103, according to the method in step S102, a plurality of layers of redistribution traces 113 are sequentially deposited, and finally the redistribution structure 110 is formed, and a plurality of first metal pads 114 are formed on the flip-chip terminal mounting surface 111 of the redistribution structure 110.
In step S104, a photoresist is coated on the flip-chip terminal mounting surface 111, and photoresist holes are formed on the selected first metal pads 114. In step S105, after depositing metal in the photoresist holes, the photoresist is removed to form the sidewall portions 121 of the emi shielding structure 120, and in some embodiments, the metal may be deposited by electroplating to directly form the sidewall portions 121 of the emi shielding structure 120 on the first metal pads 114 of the flip-chip terminal mounting surface 111 of the redistribution structure 110.
In step S106, the plurality of chips 130 dipped with solder paste are aligned and disposed on the selected first metal pads 114, and a reflow process is performed to flip-chip bond the chips 130 to the flip-chip terminal mounting surface 111, in some embodiments, the method further includes aligning and disposing a plurality of passive devices 140 dipped with solder paste on the selected first metal pads 114, and performing a reflow process simultaneously with the chips 130 to simultaneously connect the chips 130 and the passive devices 140 to the flip-chip terminal mounting surface 111.
In step S107, a molding process is performed to form a molding body 160 on the flip-chip terminal mounting surface 111 to mold and seal the sidewall frame portion 121 of the emi shielding structure 120, the chip 130 and the passive device 140.
In step S108, the top layer 122 forming the electromagnetic interference shielding structure 120 is disposed on the plastic package body 160, the top layer 122 is attached to the plastic package body 160 and connected to the sidewall frame portion 121, the top layer 122 and the sidewall frame portion 121 form at least one shielding cavity 123, and at least one chip 130 is disposed inside each shielding cavity 123, which includes the following specific steps: the molding compound 160 is thinned to expose the top end of the sidewall frame portion 121, and a certain thickness of the molding compound 160 remains above the die back 131 of the chip 130, in some embodiments, the thickness of the molding compound 160 is greater than or equal to 5 μm. Metal is deposited on the surface of the thinned plastic package body 160 to form the top layer 122 of the emi shielding structure, and in some embodiments, the metal may be deposited by sputtering. The top layer 122 is formed as an integral structure with the sidewall frame portion 121.
In step S109, a second carrier 392 is provided, an adhesive film 303 is attached to the surface of the second carrier 392, and the top layer 122 of the emi shielding structure 120 is attached to the adhesive film 302.
In step S110, the first carrier 391 is removed to expose the external terminal mounting surface 112 of the redistribution structure 110, a hole is opened in the external terminal mounting surface 112 to expose the first layer of redistribution traces 313A, the second metal pad 170 is formed on the first layer of redistribution traces 313A, and the external terminal 180 is disposed on the second metal pad 170. In some embodiments, the second metal pad 170 may be an Under Bump Metallurgy (UBM), and the external terminal 180 may be a solder ball.
In step S111, the second support 392 and the adhesive film 303 are removed; an adhesive 393 is provided and the top layer 122 of the emi shielding structure 120 is attached to the adhesive 393.
In step S112, singulation is performed to form a plurality of semiconductor packages.
In some embodiments, the first support 391 and the second support 392 may be circular discs made of metal, silicon, silica, organic material, or glass, and the adhesive film 303 may be an adhesive film that loses its adhesiveness by heating.
In some embodiments, the emi shielding structure 120 is made of a metal having a melting point higher than the highest temperature of the reflow process used to flip-chip bond the chip 130 to the flip-chip terminal mounting surface 111.
The embodiments of the present invention have been described above with reference to specific embodiments. However, the present invention is not limited to these specific embodiments. That is, those skilled in the art can appropriately design and modify the embodiments so long as the features of the present invention are included in the scope of the present invention. For example, the elements, the arrangement, the materials, the conditions, the shapes, the sizes, and the like of the elements included in the above embodiments are not limited to those illustrated in the drawings, and may be appropriately modified. The elements of the above-described embodiments may be combined as technically allowable, and the combination of these elements is also intended to be included in the scope of the present invention as long as the features of the present invention are included.
Claims (12)
1. A semiconductor package structure, comprising:
the rewiring structure is provided with a flip-chip terminal mounting surface, and a plurality of metal pads are formed on the flip-chip terminal mounting surface; and
the electromagnetic interference shielding structure comprises a side wall frame part and a top layer, wherein the side wall frame part is directly formed on the metal pad of the flip chip terminal mounting surface of the rewiring structure so as to connect the whole bottom surface of the side wall frame part with the metal pad; the metal pad positioned below the side wall frame part is not electrically connected with the rewiring structure;
a plurality of chips flip-chip bonded to the flip-chip terminal mounting surface; and
a plastic package body formed on the flip chip terminal mounting surface to seal the side wall frame portion and the chip of the electromagnetic interference shielding structure;
the top layer is attached to the plastic package body and connected with the side wall frame portion, the top layer and the side wall frame portion form at least one shielding cavity, at least one chip is arranged in the shielding cavity, and the melting point of the side wall frame portion is higher than the highest temperature of a reflow soldering process adopted when the chip is in flip chip bonding with the flip chip terminal mounting surface.
2. The semiconductor package structure of claim 1, wherein the top layer is directly connected to a top end of the sidewall frame portion exposed outside the mold package.
3. The semiconductor package of claim 1, wherein the rewiring structure further has an external terminal mounting surface, the semiconductor package further comprising a plurality of external terminals disposed on the external terminal mounting surface.
4. The semiconductor package structure of claim 1, wherein a plurality of passive devices are further disposed in the shielding cavity, and disposed on the flip-chip terminal mounting surface via solder, the passive devices being located in one of the shielding cavities.
5. The semiconductor package structure of any one of claims 1 to 4, wherein a thickness of the molding compound between a back side of the chip and the top layer of the EMI shielding structure is greater than or equal to 5 μm.
6. A method for manufacturing a semiconductor package structure, comprising:
providing a first carrier, and forming a rewiring structure on the surface of the first carrier, wherein the rewiring structure is provided with a flip-chip terminal mounting surface, and a metal pad is formed on the flip-chip terminal mounting surface;
forming a first portion of an electromagnetic interference shielding structure on the rewiring structure, wherein the first portion comprises a sidewall frame portion of the electromagnetic interference shielding structure and is directly formed on the metal pad of the flip-chip terminal mounting surface of the rewiring structure, so that the whole bottom surface of the sidewall frame portion is connected with the metal pad; the metal pad positioned below the side wall frame part is not electrically connected with the rewiring structure;
flip-chip bonding a plurality of chips on the flip-chip terminal mounting surface;
forming a plastic package body on the flip chip terminal mounting surface to seal the side wall frame part and the chip of the electromagnetic interference shielding structure in a mold manner; and
forming a second part of the electromagnetic interference shielding structure on the plastic package body, wherein the second part comprises a top layer of the electromagnetic interference shielding structure, the top layer is attached to the plastic package body and connected with the side wall frame portion, the top layer and the side wall frame portion form at least one shielding cavity, and at least one chip is arranged inside each shielding cavity; the melting point of the side wall frame part is higher than the highest temperature of a reflow soldering process adopted when the chip is in flip chip joint with the flip chip terminal mounting surface.
7. The method of manufacturing a semiconductor package structure of claim 6, wherein the step of forming the second portion of the EMI shielding structure further comprises:
thinning the plastic package body to expose the top end of the side wall frame part; and
depositing metal on the thinned surface to form the top layer of the EMI shielding structure;
the manufacturing method of the semiconductor packaging structure further comprises the following steps:
providing a second carrier, attaching to the top layer, while removing the first carrier;
forming a plurality of external terminals on the external terminal mounting surface exposed by the rewiring structure after the first carrier is removed; and
and performing singulation cutting to form a plurality of semiconductor packaging structures.
8. The method for manufacturing a semiconductor package structure according to claim 7, wherein in the step of thinning the molding compound, the thickness of the molding compound remaining on the back side of the chip is thinned to 5 μm or more.
9. The method of manufacturing a semiconductor package structure according to claim 6, wherein the sidewall frame portion is formed by an electroplating method.
10. The method of manufacturing a semiconductor package according to claim 6, wherein the top layer is formed by a sputtering method.
11. The method according to claim 6, wherein the EMI shielding structure is made of a metal having a melting point higher than a maximum temperature of a reflow process used for flip chip bonding the chip to the flip chip terminal mounting surface.
12. The method for manufacturing a semiconductor package according to any one of claims 6 to 11, wherein the flip chip bonding step of the plurality of chips further comprises: and arranging a plurality of passive devices on the flip-chip terminal mounting surface, wherein the passive devices are positioned in one of the shielding cavities.
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| CN201711041958.5A CN109727928B (en) | 2017-10-30 | 2017-10-30 | Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof |
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| CN201711041958.5A CN109727928B (en) | 2017-10-30 | 2017-10-30 | Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof |
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| CN111816640A (en) * | 2020-06-02 | 2020-10-23 | 江苏长电科技股份有限公司 | BGA electromagnetic shielding packaging structure and manufacturing method thereof |
| CN113823622A (en) * | 2020-06-18 | 2021-12-21 | 华为技术有限公司 | Chip packaging device and electronic equipment |
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| CN105990317A (en) * | 2015-02-25 | 2016-10-05 | 晟碟信息科技（上海）有限公司 | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof |
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| US7161252B2 (en) * | 2002-07-19 | 2007-01-09 | Matsushita Electric Industrial Co., Ltd. | Module component |
| US7327015B2 (en) * | 2004-09-20 | 2008-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
| WO2007072616A1 (en) * | 2005-12-22 | 2007-06-28 | Murata Manufacturing Co., Ltd. | Module having built-in component and method for fabricating such module |
| CN105489593B (en) * | 2015-12-24 | 2018-08-03 | 合肥矽迈微电子科技有限公司 | It is electromagnetically shielded package assembling and its manufacturing method |
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| CN105990317A (en) * | 2015-02-25 | 2016-10-05 | 晟碟信息科技（上海）有限公司 | Device with electromagnetic interference shield layer and semiconductor and manufacture method thereof |
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