US20140251657A1

US20140251657A1 - Printed circuit board and method of manufacturing the same

Info

Publication number: US20140251657A1
Application number: US14/281,333
Authority: US
Inventors: Hyung Jin Jeon; Young Do Kweon; Seung Wook Park; Seon Hee Moon
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2010-07-14
Filing date: 2014-05-19
Publication date: 2014-09-11
Also published as: US8756804B2; US20120073870A1

Abstract

Embodiments of the invention provide a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of and priority to U.S. patent application Ser. No. 13/213,984, entitled, “PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME,” filed Aug. 19, 2011, which is a continuation in part of and claims the benefit of U.S. patent application Ser. No. 12/894,002, entitled “PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME,” filed on Sep. 29, 2010, which claims the benefit of Korean Patent Application No. 10-2010-0068162, filed Jul. 14, 2010, entitled “PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF”, which are all hereby incorporated by reference in their entirety into this application

BACKGROUND

1. Field of the Invention
The present invention relates to a printed circuit hoard and a method of manufacturing the same.
2. Description of the Related Art
Printed circuit boards (PCBs), which are responsible for signal transmission, power supply, etc., using electrical connections between electronic components, have been developed towards the fineness of active devices and semiconductor components and the fabrication of electronic products which are lightweight, slim, short and small, rather than being developed independently.
Conventional PCBs are provided in the form of multilayered PCBs by repetitively stacking insulating and circuit layers on a core layer having a circuit layer. In the typical formation of multilayered PCBs, locating an insulating layer at an accurate position and forming a circuit layer adapted for the requirements made thereof are regarded as important when determining the reliability of the PCB. To this end, an align key is formed on the PCB and is used together with a device for recognizing the align key to perform a build-up process.
Also, alongside recent trends in the electronics industry are the demands for rapidly and inexpensively manufactured d products which are lightweight and small and have multi-functionality and high reliability. One of the important methods enabling this is the packaging technique. The packaging technique uses an interposer board in order to achieve a three-dimensional structure and a small size.
A conventional interposer board includes a semiconductor wafer (Si wafer) serving as a core layer. The interposer board is formed by performing grinding to control the thickness of the supplied Si wafer, forming a through hole, performing an oxidizing process to form an oxide insulating layer on the outer surface of the wafer and on the inner wall of the through hole, and performing a plating process to form a via and a redistribution layer. As such, the redistribution layer may be formed to have a multilayer structure using a typical build-up process.
However, the Si interposer board thus manufactured is disadvantageous because expensive materials are used and the semiconductor process is employed, undesirably complicating the manufacturing process, resulting in lowered productivity.

SUMMARY

Accordingly, embodiments of the invention have been made keeping in mind the problems encountered in the conventional art and therefore embodiments of the present invention are intended to provide a PCB, which includes a base member made of a ceramic material or an organic material, and an insulating layer formed on a surface of the base member so that the surface of the base member is flattened to thus facilitate the recognition of an align key formed on the base member.
Also, embodiments of the present invention are intended to provide a method manufacturing the PCB.
An embodiment of the present invention provides a PCB, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member.
According to an embodiment, the base member includes a ceramic material or an organic material.
According to an embodiment, the PCB further includes a protection layer formed on the circuit layer.
According to an embodiment, the circuit layer includes a pad exposed to the outside and a pad protection layer formed on the pad.
According to an embodiment, the circuit layer has a multilayer structure.
According to an embodiment, the protection layer has an opening for exposing the pad of the circuit layer or the via.
According to an embodiment, the opening is subjected to rounding treatment to be imparted with a shape, which has a diameter that increases as the opening becomes more distant from the base member.
According to an embodiment, the protection layer is formed by means of a photoresist using a liquid photodefinable material, and the opening of the protection layer is formed using photo-exposure and development.
According to an embodiment, a thickness from one surface of the circuit layer in contact with the protection layer to an exposed surface of the protection layer is 15 μm or less.
Another embodiment of the present invention provides a method of manufacturing a PCB, including providing a base member, forming an insulating layer on each of both surfaces of the base member, forming a through hole in the base member, forming a via in the through hole, and forming a circuit layer on each of both surfaces of the base member so that the circuit layer formed on one surface of the base member and the circuit layer formed on the other surface of the base member are connected with each other using the via.
According to an embodiment, the base member includes a ceramic material or an organic material.
According to an embodiment, the method further includes forming a protection, layer for covering the circuit layer, after forming the circuit layer.
According to an embodiment, the protection has an opening for exposing the pad of the circuit layer or the via.
According to an embodiment, the opening is subjected to rounding treatment so as to be imparted with a shape which has a diameter that increases as the opening becomes more distant from the base member.
According to an embodiment, the protection layer is formed by means of a photoresist using a liquid photodefinable material, and the opening of the protection layer is formed using photo-exposure and development.
According to an embodiment, the protection layer is formed so that a pad of the circuit layer is exposed, and the method further includes forming a pad protection layer on the pad.
According to an embodiment, forming the via and forming the circuit layer is simultaneously performed using plating.
Various objects, advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

These and other features, aspects, and advantages of the invention are better understood with regard to the following Detailed Description, appended Claims, and accompanying Figures. It is to be noted, however, that the Figures illustrate only various embodiments of the invention and are therefore not to be considered limiting of the invention's scope as it may include other effective embodiments as well.

FIG. 1 is a cross-sectional view schematically showing a PCB according to an embodiment of the present invention.

FIGS. 2 and 3 are cross-sectional views schematically showing modifications of the PCB of FIG. 1 according to embodiments of the present invention.

FIGS. 4 to 13 are cross-sectional views schematically showing a process of manufacturing the PCB of FIGS. 1 to 3 according to embodiments of the present invention.

DETAILED DESCRIPTION

Advantages and features of the present invention and methods of accomplishing the same will be apparent by referring to embodiments described below in detail in connection with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. The embodiments are provided only for completing the disclosure of the present invention and for fully representing the scope of the present invention to those skilled in the art.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. Like reference numerals refer to like elements throughout the specification.
FIG. 1 is a cross-sectional view schematically showing a PCB according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views schematically showing modifications of the PCB of FIG. 1 according to embodiments of the present invention. With reference to these drawings, the PCB according to an embodiment of the present invention is described below.
As shown in FIG. 1, the PCB 100 includes a base member 110 made of an organic or ceramic material. Whereas a conventional interposer board includes a Si wafer, the PCB 100 according to an embodiment of the present invention uses the above material and thus may further reduce the material cost when used as an interposer board.
According to an embodiment, the base member 110 of organic material includes a plastic resin, such as a phenol resin, an epoxy resin, or an imide resin, and reduces changes in dimension depending on strength and temperature using a reinforcing material such as glass fiber or paper. In addition, the base member 110 of ceramic material includes a non-metal solid or an inorganic material such as alumina (Al₂O₃), and has very low electrical conductivity and is more resistant to high temperature compared to when the organic material is used.
As shown in FIG. 1, the base member 110 typically has a planar rectangular shape, but the shape thereof is not limited thereto and may vary.
Also, according to an embodiment, insulating layers 120 are respectively formed on both surfaces of the base member 110, so that the surfaces of the base member 110 are flattened. A typical base member 110 having surface roughness is problematic, because it decreases reliability upon formation of a circuit layer and makes it difficult to recognize an align key. More specifically, when a circuit layer is formed using an etching process, in the case of the base member 110 having suffice roughness, excessive etching is performed in order to prevent adjacent circuit patterns from shorting out, undesirably increasing defects (non-uniform circuit patterns) of the circuit layer. Also, when the align key is recognized using IR light and then photo-exposure and development or stacking is performed, the surface roughness hinders the recognition of the align key.
According to an embodiment, the insulating layers 120 function to flatten the surfaces of the base member 110 to thus offset the surface roughness, thereby solving the above problems. As such, the insulating layers 120 are provided in the form of a thin film and are made of an organic material.
Also, according to an embodiment, circuit layers 130 are respectively formed on the insulating layers 120. Because the insulating layers 120 are formed on both surfaces of the base member 110, the circuit layers 130 are also formed on both surfaces of the base member 110. Accordingly, the PCB 100 electrically connects a main circuit board on which the corresponding PCB is mounted, with an electronic device mounted on the corresponding PCB. As such, the circuit layers 130 are formed using a typical plating process, and are made of a conductive material such as copper.
In particular, in the case where the PCB 100 according to an embodiment of the invention is used as an interposer board, the circuit layers 130 function as a redistribution layer.
Also, according to an embodiment, vias 140 function to connect the circuit layers 130 formed on both surfaces of the base member 110. The via 140 are typically formed by forming through holes 115 in the base member 110 and then performing plating, and the structure and shape of the vias 140 are easily modified.
In addition, a PCB 100-1, as shown in FIG. 2, further includes protection layers 150 formed on the circuit layers 130. The protection layers 150 function to prevent the oxidation of the circuit lavers 130. The protection layers 150 include a photoresist (PR) using a liquid photodefinable material. According to an embodiment, the liquid photodefinable material includes a resin such as hydroxystyrene, epoxy, acryl, etc., a photosensitive crosslinker, and a solvent, but embodiments of the invention are not necessarily limited thereto, and any photosensitive material known in the art may be used. When the protective layers 150 are formed by means of PR using the liquid photodefinable material in this way, the thickness T from one surface of the circuit layer 130 in contact with the protection layer 150 to the exposed surface of the protection layer 150 are formed to 15 μm or less, which is much thinner compared to conventional techniques.
As such, openings 155 are formed in the protection layers 150, so that pads 132 for mounting an electronic device are exposed to the outside. Furthermore, the openings 155 of the protection layers 150 are formed to expose the vias 140 to the outside, in addition to the pads 132 (an enlarged view of FIG. 2). As such, the openings 155 of the protection layers 150 are formed using photo-exposure and development, and the specific formation process thereof is described later.
Also, according to an embodiment, the openings 155 of the protection layers 150 are subjected to rounding treatment 157 to be imparted with a shape, which has a diameter that increases as an opening becomes snore distant from the base member 110 (an enlarged view of FIG. 2). When the openings 155 of the protection layers 150 are subjected to rounding treatment 157 in this way, upon forming a seed layer using a sputter, the seed layer is deposited on portions subjected to rounding treatment 157, even if a material having linearity is emitted perpendicular to the protection layers 150 from the sputter.
As further shown in FIG. 2, the pads 132 function as connectors on which bumps are located, when the electronic device is mounted on the PCB 100-1 or when the PCB 100-1 is mounted on another circuit board.
Also, according to an embodiment, pad protection layers 134 are further formed on the pads 132. The pad protection layers 134 function to protect the pads 132 exposed to the outside from being oxidized, and to improve the solderability of components and conductivity. According to an embodiment, the pad protection layers 134 are made of a metal having low corrosivity and high conductivity, such as tin, silver or gold.
In addition, the circuit layer 130 of a PCB 100-2, as shown in FIG. 3, has a multilayer structure formed by repetitively stacking insulating layers 50 and circuit layers. In particular, in the case where the PCB 100 according to an embodiment of the invention is used as an interposer board, the circuit layer 130 functions as a redistribution layer, and thus enables a wiring structure to vary depending on the needs thanks to the formation of the multilayer structure. On the other hand, according to another embodiment, the insulating layers 50 are formed by means of PR using a liquid photodefinable material, like the protection layers 150. Furthermore, via holes that perforate the insulating layers 50 are subjected to rounding treatment to be imparted with a shape which has a diameter that increases as it becomes more distant from the base member 110, as in the openings 155 of the protection layers 150.
With reference to FIGS. 4 to 13, a method of manufacturing the PCB according to another embodiment of the invention is described below.
As shown in FIG. 4, a base member 110 is provided. The base member 110 constitutes a core layer of the PCB 100, and is made of an organic or ceramic material.
Next, as shown in FIG. 5, insulating layers 120 are respectively formed on both surfaces of the base member 110. The insulating layers 120 are formed using an organic material (e.g., a plastic resin) or a ceramic material. As such, roller coating, curtain coating, or spray coating is applied. The insulating layers 120 thus formed offset the surface roughness caused by irregularities, thus forming flattened surfaces.
Next, as shown in FIG. 6, through holes 115 are formed in the base member 110. As such, mechanical drilling using a drill bit or laser machining using a YAG laser or a CO₂laser may be utilized.
Next, vias 140 are formed in the through holes 115. As shown in FIG. 7, the through holes 115 are filled with a conductive material, thus forming the vias 140, or alternatively, plated vias 140 are formed on the inner walls of the through holes 115 using electroless copper plating and copper electroplating.
Next, as shown in FIG. 8, circuit layers 130 are respectively formed on both surfaces of the base member 110, so that they are connected using the vias 140. Specifically, plating layers (which are formed on the insulating layers) are formed on both surfaces of the base member 110, master films are laminated thereon, photo-exposure and development are performed, and then etching is performed, thus forming the circuit layers 130.
In addition, as shown in FIG. 9, protection layers 150 are formed to cover the circuit layers 130, and openings 155 for exposing the pads 132 or the vias 140 are formed in the protection layers 150.
Specifically in the formation of the protection layers 150, PR using a liquid photodefinable material is applied on the insulating layers 120, and prebaked at 60˜150° C. for 1˜10 minutes, after which photo-exposure for radiating light onto portions (positive type PR) where openings 155 will be formed or the other portions (negative type PR) depending on the kind of PR is carried out. Subsequently, development is performed so that the portions where the openings 155 will be formed are dissolved and removed. Finally, curing is performed at 180˜250° C. for a period of time ranging from 30 minutes to 2 hours thus completing the protection layers 150. However, this process of forming the protection layers 150 is merely illustrative, and the scope of various embodiments of the invention is not limited thereto.
According to an embodiment, the openings 155 of the protection layers 150 are formed into various shapes depending on the process conditions (e.g., temperature, time, photo-exposure amount, etc.) including prebaking, photo-exposure, and development. In particular, the openings 155 are subjected to rounding treatment 157 to be imparted with a shape, which has a diameter that increases as an opening becomes more distant from the base member 110, while shrinking the resin of the liquid photodefinable material in the curing process (an enlarged view of FIG. 9).
According to an embodiment, the formation of pad protection layers 134 for protecting the pads exposed to the outside is further performed, and is carried out using an outer-surface treatment process such as hot air solder leveling (HASL), pre-flux coating, or electroless gold plating. Alternatively, under bump metallization (UBM) may be adopted as the pad protection layers 134. As such, UBM includes a wetting layer bound to bumps on which electronic devices are mounted, a barrier layer for preventing the diffusion of bumps to the pads 132, and an adhesion layer for enhancing adhesion between the bumps and the pads 132.
In addition, a method of manufacturing a PCB according to another embodiment of the invention enables vias 140 and circuit layers 130 connected using the vias 140 to be simultaneously formed using plating. With reference to FIGS. 10 to 13, the method of manufacturing the PUB according to the present embodiment is described below.
As shown in FIG. 10, a seed layer 136 is formed on a base member 110 having through holes 115 formed therein. The seed layer 136 is funned on the inner walls of the through holes 115 and on the insulating layers 120 using electroless copper plating. The electroless copper plating is performed using a precipitation reaction in the presence of a catalyst composed of a palladium-tin compound in order to plate the surface of a non-conductor, such as the organic material or the ceramic material.
Next, as shown in FIG. 11, a plating layer 138 is formed, and then the seed layer 136 and the plating layer 138 are patterned. The plating layer 138 is identically formed on the seed layer 136 using copper electroplating. Furthermore, patterning is performed using a master film (e.g., an etching resist film) and an etchant.
As such, in order to protect the seed layer 136 and the plating layer 138 formed on the inner walls of the through holes 115, a hole filling process for filling through holes with ink or a tenting process using a master film may be applied (e.g., a panel plating process).
Next, as shown in FIGS. 12 and 13, protection layers 150 are formed, and pad protection layers 134 are further formed on the pads 132.
As mentioned above with reference to various embodiment of the invention, as illustrated in FIGS. 10 to 13, the vias and the circuit layers are simultaneously formed, and thus the manufacturing process becomes simplified, resulting in increased productivity. Also, in order to simultaneously form the vias and the circuit layers, a patterning plating process, which includes performing electroless plating, forming a plating resist and then selectively forming plating layer may be is the present embodiment, in addition to the panel plating process using the hole filling process or the tenting process.
In addition, a PCB 100-2, as shown in FIG. 3, is configured, such that a circuit layer 130 formed on one surface of a base member 110 has a multilayer structure. Such a PCB 100-2 is manufactured by forming a single circuit layer on the base member 110 as mentioned above with reference to FIG. 8, and then repeating (a build-up process) the formation of an insulating layer and the formation of a circuit layer.
As described hereinbefore, embodiments of the invention provide a PCB and a method of manufacturing the same. In the PCB according to various embodiments of the invention, a base member made of a ceramic material or an organic material is used, thus reducing the PCB production cost, and in particular, it substitutes for a Si wafer when forming an interposer board, and thereby the production cost can be further reduced.
Also, according to various embodiments of the invention, the PCB is configured, such that an insulating layer is formed on the base member thus flattening the surface of the base member, and thereby an align key formed on the base member can be accurately recognized. Therefore, a build-up process can be efficiently carried out, and the reliability of a circuit layer is increased. In the case of the interposer board, the formation of a redistribution layer is easy.
Also, according to the present invention, because the PCB includes the base member made of a ceramic material or an organic material, a typical build-up process can be utilized in lieu of a conventional semiconductor process, thereby shortening the manufacturing time and increasing the productivity.
Terms used herein are provided to explain embodiments, not limiting the present invention. Throughout this specification, the singular form includes the plural form unless the context clearly indicates otherwise. When terms “comprises” and/or “comprising” used herein do not preclude existence and addition of another component, step, operation and/or device, in addition to the above-mentioned component, step, operation and/or device.
Embodiments of the present invention may suitably comprise, consist or consist essentially of the elements disclosed and may be practiced in the absence of an element not disclosed. For example, it can be recognized by those skilled in the art that certain steps can be combined into a single step.
The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to describe the best method he or she knows for carrying out the invention.
The terms “first,” “second,” “third,” “fourth,” and the like, in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method.
The singular forms “a,” “an,” and “the” include plural referents, unless the context clearly dictates otherwise.
As used herein and in the appended claims, the words “comprise,” “has,” and “include” and all grammatical variations thereof are each intended to have an open, non-limiting meaning that does not exclude additional elements or steps.
As used herein, the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative, positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Objects described herein as being “adjacent to” each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
Ranges may be expressed herein as from about one particular value, and/or to about another particular value. When such a range is expressed, it is to be understood that another embodiment is from the one particular value and/or to the other particular value, along with all combinations within said range.
Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereupon without departing from the principle and scope of the invention. Accordingly, the scope of the present invention should be determined by the following claims and their appropriate legal equivalents.

Claims

What is claimed is:

1. A printed circuit board, comprising:

a base member;

an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened;

a circuit layer formed on the insulating layer; and

a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member.

2. The printed circuit board as set forth in claim 1, wherein the base member comprises a ceramic material or an organic material.

3. The printed circuit board as set forth in claim 1, further comprising a protection layer formed on the circuit layer.

4. The printed circuit board as set forth in claim 1, wherein the circuit layer comprises a pad exposed to outside and a pad protection layer formed on the pad.

5. The printed circuit hoard as set forth in claim 1, wherein the circuit layer has a multilayer structure.

6. The printed circuit board as set forth in claim 3, wherein the protection layer has an opening for exposing the pad of the circuit layer or the via.

7. The printed circuit board as set forth in claim 6, wherein the opening is subjected to rounding treatment so as to be imparted with a shape which has a diameter that increases as the opening becomes more distant from the base member.

8. The printed circuit board as set forth in claim 6, wherein the protection layer is formed by means of a photoresist using a liquid photodefinable material, and the opening of the protection layer is formed using photo-exposure and development.

9. The printed circuit board as set forth in claim 3, wherein a thickness from one surface of the circuit layer in contact with the protection layer to an exposed surface of the protection layer is 15 μm or less.