JP2005056924A - Process for producing multilayer substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for producing a multilayer substrate with high accuracy and reliability. <P>SOLUTION: A through hole 22 is made through a substrate 21 by laser beam machining, Cu 23 is deposited on the substrate 21 by electroless plating, a via hole 24 is formed by filling the through hole 22 with deposition by plating, an electric circuit pattern 29 being connected with the via hole 24 is formed on the Cu 23 by photoetching, and a plurality of wafers 20 on which the electric circuit is formed are laid in layers and thermo-compression bonded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer substrate, for example, a method for manufacturing a multilayer substrate used as a high-frequency substrate for electronic components for high-speed communication such as radio and light.
[0002]
[Prior art]
A multilayer substrate is frequently used as a high-frequency substrate for electronic components for high-speed communication, and a method for manufacturing such a multilayer substrate is disclosed in, for example, Japanese Patent Laid-Open No. 3-148195. FIG. 3 is a diagram for explaining the manufacturing method.
[0003]
In FIG. 3A, an insulating sheet 6 coated with a carrier film 4 is laminated and adhered on a stainless steel substrate 2 as a temporary substrate, and then only the carrier film 4 is peeled off. The insulator sheet 6 is a clay-like substance in which ceramic powder (aluminum powder, AlN powder, etc.), an auxiliary agent, and a binder material are mixed. By firing, the binder material disappears, and the ceramic powders become solid. It is a mix.
[0004]
Next, using a carbon dioxide laser, holes 8 having a diameter of 180 μm are formed in the insulating sheet 6 as shown in FIG. Then, the hole 8 is filled using a via hole filling silver conductor or W (tungsten) through a metal mask to form the via hole 10 as shown in FIG. Thereafter, the electric circuit 12 is printed by screen printing on the insulator sheet 6 having the via hole 10 filled with the conductive material as shown in FIG.
[0005]
After repeating FIG. 3 (a)-(d) and forming the laminated body of 7 layers, for example, after laminating | stacking the insulator sheet 6 and obtaining the laminated body which has a total of 8 layers of insulator sheets, The temporary substrate 2 is removed and placed on an alumina support and fired. As a result, a sintered body of a multilayer substrate having eight insulating sheets and seven internal electric circuit layers and vias on the front and back sides is obtained.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 3-148195
[Problems to be solved by the invention]
In the manufacturing method shown in FIG. 3, after the holes 8 are formed, the position of the via holes 10 is shifted by about 10 to 50 μm due to shrinkage or the like during firing of the insulator sheet 6 or the via hole filling conductor. When a thin film circuit such as a microwave filter is to be formed on a multilayer substrate, a pattern (circuit) is formed using photolithography. At this time, if misalignment occurs due to baking, it is necessary to make a mask pattern in accordance with the reduced state of the substrate.
[0008]
However, if the position of displacement is not stable or the amount of deviation is different each time, a mask pattern is required for each substrate, which causes a large increase in cost and extremely deteriorates productivity. For example, when creating a microwave thin film circuit of 2.0 GHz or more, a pattern accuracy of 50 μm or less is required. For this reason, at present, it is necessary to create a mask pattern for each firing lot, which increases the cost.
[0009]
Further, the via hole 10 is filled by using the via hole filling conductor to form the via hole 10, and then the via hole filling conductor and the insulator sheet 6 are fired, so the hole 8 is not completely filled and a cavity is generated. There is a problem of end.
[0010]
If a cavity is generated in the hole 8 in this way, the parasitic inductor component as a high-frequency characteristic increases, so that it deviates from the designed characteristic impedance. In order to reduce this parasitic inductance, an inductance component may be connected in parallel, but it is necessary to form a via hole more than necessary. In the photolithography described above, patterning is performed using a resist. However, if there is a hole, the thickness of the resist around the hole becomes thin, and patterning cannot be performed.
[0011]
Therefore, a main object of the present invention is to provide a method for manufacturing a multilayer substrate that can improve accuracy and reliability.
[0012]
[Means for Solving the Problems]
The present invention relates to a method of manufacturing a multilayer substrate in which a plurality of substrates on which electric circuits are formed are stacked, a step of forming a hole on the substrate by laser processing, and plating to fill the hole to form a via hole And a step of forming an electric circuit connected to the via hole on the substrate, and a step of laminating a plurality of substrates on which the electric circuit is formed and thermocompression bonding.
[0013]
In this invention, since the via hole is formed by plating after the via hole is drilled by laser processing, the position of the via hole is not shifted, and a substrate that can completely fill the hole can be created, A highly accurate substrate that can withstand the current semiconductor process can be produced.
[0014]
Preferably, the plating is also performed on the entire upper surface of the substrate, and the step of forming the electric circuit is characterized in that a circuit pattern is formed by photo-etching a plated portion on the upper surface of the substrate.
[0015]
Preferably, the substrate on which the electric circuit is formed is formed with a work-affected layer that becomes a starting point for division after lamination.
[0016]
Preferably, electrode pads for power feeding are formed on the plurality of substrates, and the step of thermocompression bonding is characterized in that the electrode pads of the plurality of substrates or electrode pads and via holes are electrically connected.
[0017]
Preferably, the thermocompression bonding step is characterized by electrically connecting via holes of a plurality of substrates.
[0018]
Preferably, the thermocompression bonding step is performed by stacking a plurality of substrates and applying a predetermined pressure at a predetermined temperature for a predetermined time.
[0019]
Preferably, the plating for forming the via hole uses a plating solution having an impurity concentration of 3% or less.
[0020]
Preferably, the plating for forming the via hole is selected from Ni, Cu, CuW and Au.
[0021]
Preferably, the substrate is a fired ceramic substrate having a round shape or a square shape having a size of about 1500 m ² or more.
[0022]
Preferably, the multilayer substrate laminated and thermocompression bonded is cut for each die based on the starting point of the work-affected layer.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram for explaining a method of manufacturing a multilayer substrate according to the present invention. As shown in FIG. 1A, a ceramic substrate 21 constituting the wafer 20 is prepared. In the present invention, a substrate that does not require a firing step in a subsequent step, such as a ceramic substrate, is used. In the case of FIG. 1A, the ceramic substrate 21 is made by polishing the fired AlN and having a surface irregularity of 0.2 μm or less and a thickness of 200 μm. The size of the ceramic substrate 21 is preferably about 1500 mm ² or more, and the shape is preferably formed in a round shape or a square shape.
[0024]
Next, as shown in FIG. 1B, through holes 22 are formed in the ceramic substrate 21 by a YAG laser. As the YAG laser, a typical Nd (neodymium): YAG laser is used, and if the power is 1 W and the beam diameter is 30 μm, the through hole 22 can be formed in about 10 seconds. Note that the through hole 22 may be formed in the ceramic substrate 21 by a short wavelength pulse laser or a femtosecond laser instead of the YAG laser.
[0025]
Next, as shown in FIG. 1C, Cu 23 is formed on the ceramic substrate 21 by electroless plating, and the through hole 22 is filled. Electroless plating is performed by immersing the ceramic substrate 21 in a plating solution containing 1.5% of 37% HCl for a volume ratio of 100 of the solution Cu (NH ₄ ) ₂ C 1 _4. Can be grown on the entire surface of the ceramic substrate 21 with a thickness of 30 μm, and the inside of the through hole 22 can be completely filled with Cu 23. Thereby, the via hole 24 is formed.
[0026]
When the through hole 22 is formed in the ceramic substrate 21 by laser processing, the inner wall of the through hole 22 is deteriorated due to the heat of laser processing, and the metal component of the ceramic is deposited and becomes metalized to be electrically conductive. In this state, when electroless plating is performed, selective plating is performed from the electrically conductive portion, so that the inside of the through hole 22 can be completely filled with Cu23. If the inner wall of the through hole 22 is not selectively plated, the portion other than the through hole 22 and the upper surface of the ceramic substrate 21 may be covered with an organic protective film such as a resist.
[0027]
The purity of the plating solution is preferably 3% or less, and the plating solution is selected from Ni, Cu, CuW and Au.
[0028]
Next, an electric circuit pattern is formed on the plated Cu 23 of the ceramic substrate 21 shown in FIG. That is, as shown in FIG. 1D, a photoresist 25 is applied on the plated Cu 23, and a photomask 27 on which a thin film circuit 26 constituting a microwave filter, a power line, and the like is drawn is used. The photoresist 25 is exposed by irradiation or the like, and thereafter development is performed.
[0029]
As a result of development, a resist pattern 28 is formed as shown in FIG. 1E. When acid-based etching is performed, Cu 23 other than the electric circuit pattern 29 is dissolved as shown in FIG. Only 28 and the electric circuit pattern 29 are left. Finally, when the resist is removed, the wafer 20 having the electric circuit pattern 29 formed on the ceramic substrate 21 is produced as shown in FIG.
[0030]
FIG. 2 is a diagram for explaining a method of laminating ceramic substrates. A plurality of wafers 20a, 20b,... 20n are formed by the method of FIG. 1, and these wafers 20a, 20b,. Each wafer 20a, 20b,... 20n is formed with electrode pads (not shown) connected to a power supply line or a ground line for power supply. When the wafers 20a, 20b,... 20n are bonded together, the substrates need to be electrically connected to each other, but the electrode pads of each wafer 20a, 20b,. . In the case where power is supplied through the via hole 24, the connection may be made between the via holes 24 without connecting the electrode pads to each other or between the electrode pad and the via hole 24.
[0031]
In thermocompression bonding, the wafers 20a, 20b,... 20n are aligned in advance with high accuracy and stacked, and heated at a temperature of 500 to 600 ° C. while applying a pressure of 1 MPa or more. In this state, thermocompression bonding is performed by holding for 1 hour or more.
[0032]
As described above, in the present invention, since the via hole 24 is formed by plating after laser drilling using a substrate that does not require a firing step in a subsequent process such as a ceramic substrate, the position of the via hole 24 is determined. Since no deviation occurs, a high-precision multilayer substrate can be formed at low cost by stacking the multilayer substrates and performing thermocompression bonding all at once.
[0033]
The laminated multilayer substrate is divided by dicing, but the thickness increases by becoming a multilayer substrate. Further, due to the cutting resistance, it is easily peeled off from the thermocompression bonded portion during dicing. Therefore, a crack is made along a groove processed at a predetermined position of the wafer, a work-affected layer is provided, and a layer serving as a starting point for division is provided. The work-affected layer may be, for example, a groove formed by laser processing or a groove formed with chemicals. A braking device is used to divide the individual dies. Thereby, each wafer can be processed using a photolithographic technique, and can be easily divided for each die after thermocompression bonding.
[0034]
Although one embodiment of the present invention has been described with reference to the drawings, the present invention is not limited to the illustrated embodiment. Various modifications can be made to the illustrated embodiment within the same scope or equivalent scope as the present invention.
[0035]
【The invention's effect】
As described above, according to the present invention, in a subsequent process, a hole is formed by laser processing on a substrate that does not require a baking process, plating is performed to fill the hole, a via hole is formed, and the via hole is connected. As a result, the circuit board with the electrical circuit formed is stacked and thermocompression bonded to create a highly accurate substrate with completely filled via holes. It is possible to efficiently produce a substrate that can withstand.
[0036]
Further, since the via hole can be formed with high accuracy, a multilayer substrate can be easily formed, and the cost can be reduced by stacking the substrates in layers without overlapping each other individually.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a method for producing a multilayer substrate according to the present invention.
FIG. 2 is a diagram for explaining a method of multilayering a substrate.
FIG. 3 is a diagram for explaining a conventional method of manufacturing a multilayer substrate.
[Explanation of symbols]
2 Substrate 4 Carrier film 6 Insulator sheet 8 Hole 10 Via hole 12 Electric circuit 20, 20a, 20b, 20n Wafer 21 Ceramic substrate 22 Through hole 23 Cu
24 via hole 25 photoresist 26 thin film circuit 27 photomask 28 resist pattern 29 electric circuit pattern

Claims (10)

A method of manufacturing a multilayer substrate in which a plurality of substrates on which an electric circuit is formed is laminated,
Forming a hole on the substrate by laser processing;
Forming via holes by plating to fill the holes;
Forming an electrical circuit connected to the via hole on the substrate;
And a step of laminating and thermocompression-bonding a plurality of substrates on which the electric circuit is formed. The plating is also performed on the entire top surface of the substrate,
2. The method of manufacturing a multilayer substrate according to claim 1, wherein the step of forming the electric circuit forms a circuit pattern by photo-etching a plated portion on the upper surface of the substrate. 3. The method for manufacturing a multilayer substrate according to claim 1, wherein a work-affected layer that is a starting point for division after lamination is formed on the substrate on which the electrical circuit is formed. 4. An electrode pad for power feeding is formed on the plurality of substrates,
4. The multilayer substrate according to claim 1, wherein in the step of thermocompression bonding, electrode pads of the plurality of substrates or electrode pads and the via holes are electrically connected. 5. Production method. The method for manufacturing a multilayer substrate according to any one of claims 1 to 3, wherein the thermocompression bonding step electrically connects via holes of the plurality of substrates. 6. The multilayer according to claim 1, wherein the thermocompression bonding step is performed by laminating the plurality of substrates and applying a predetermined pressure at a predetermined temperature for a predetermined time. A method for manufacturing a substrate. The method for manufacturing a multilayer substrate according to claim 1 or 2, wherein plating for forming the via hole uses a plating solution having an impurity concentration of 3% or less. The method for manufacturing a multilayer substrate according to claim 1, 2 or 7, wherein the plating for forming the via hole is selected from Ni, Cu, CuW and Au. The multilayer substrate according to any one of claims 1 to 6, wherein a fired ceramic substrate having a round shape or a square shape having a size of about 1500 m ² or more is used as the substrate. Production method. 10. The method for manufacturing a multilayer substrate according to claim 1, wherein the multilayer substrate that has been laminated and thermocompression bonded is cut for each die based on a starting point of the work-affected layer. .

Images