US20120280727A1 - Power-on reset circuit - Google Patents

Power-on reset circuit Download PDF

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Publication number
US20120280727A1
US20120280727A1 US13/464,380 US201213464380A US2012280727A1 US 20120280727 A1 US20120280727 A1 US 20120280727A1 US 201213464380 A US201213464380 A US 201213464380A US 2012280727 A1 US2012280727 A1 US 2012280727A1
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US
United States
Prior art keywords
node
component
pull
power
reset circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US13/464,380
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English (en)
Inventor
Li Ping Lin
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Raydium Semiconductor Corp
Original Assignee
Raydium Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raydium Semiconductor Corp filed Critical Raydium Semiconductor Corp
Assigned to RAYDIUM SEMICONDUCTOR CORPORATION reassignment RAYDIUM SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, LI PIN
Publication of US20120280727A1 publication Critical patent/US20120280727A1/en
Assigned to RAYDIUM SEMICONDUCTOR CORPORATION reassignment RAYDIUM SEMICONDUCTOR CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTION TO THE SPELLING OF CONVEYING PARTY NAME. THE CORRECT SPELLING OF NAME IS: LI PING LIN PREVIOUSLY RECORDED ON REEL 028159 FRAME 0516. ASSIGNOR(S) HEREBY CONFIRMS THE CONVEYING PARTY NAME, LI PIN LIN, SHOULD HAVE THE CORRECT SPELLING: LI PING LIN. Assignors: LIN, LI PING
Priority to US14/067,383 priority Critical patent/US8841947B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
    • H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

Definitions

  • the present invention relates to a power-on reset circuit and, in particular, to a power-on reset circuit capable of changing a logic level of a reset signal at multiple threshold voltages.
  • Most electronic devices have a power-on reset circuit, which is used for outputting a reset signal to logic components of the electronic device.
  • the logic components include, for example, registers, counters and flip-flops, which are sensitive to starting status during boot-up. During periods with power supply inconsistencies, the power-on reset circuit outputs a reset signal to restart the electronic device.
  • FIG. 1 is a schematic view of a conventional power-on reset circuit 10 .
  • the power-on reset circuit 10 includes a pull-up component 12 and a pull-down circuit 14 .
  • the pull-up component 12 is a P-MOSFET MP 1 and the pull-down component 14 is an N-MOSFET MN 1 .
  • the conductive capability of the P-MOSFET is stronger than the capability of the N-MOSFET, so the first logic component X 1 may make a transition for changing an outputted logic level.
  • a logic level at the output node N 2 of the power-on reset circuit 10 is 1 and the power-on reset circuit 10 may output a reset signal, Reset, having a high logic level to other circuits, not shown, for resetting the circuits in logic level.
  • the present invention provides a power-on reset circuit which is capable of changing logic level of reset signal with respect to multiple threshold voltages.
  • a power-on reset circuit comprises a first pull-up component, a second pull-up component, a first pull-down component, and a first logic component.
  • the first pull-up component is coupled between a power supply and a first node.
  • the second pull-up component is coupled between the power supply and a second node.
  • the first pull-down component is coupled to the first node and a common node, and the first logic component is coupled between the first node and the second node.
  • the second pull-up component is actuated based on a voltage at the second node.
  • a power-on reset circuit comprises a first pull-up component, a first pull-down component, a second pull-down component, a first logic component, and a second logic component.
  • the first pull-up component is coupled between a power supply and a first node.
  • the first pull-down component is coupled between the first node and the common node.
  • the second pull-down component is coupled between the common node and a third node.
  • the first logic component is coupled between the first node and the second node, and a second logic component is coupled between the second node and the third node.
  • the second pull-down component is actuated based on a voltage at the third node.
  • FIG. 1 is a schematic view of a conventional power-on reset circuit
  • FIG. 2 is a schematic view of a waveform chart of a reset signal and a threshold voltage of a conventional power-on reset circuit
  • FIG. 3 is a schematic view of one embodiment of the present invention showing a power-on reset circuit
  • FIG. 4 is a schematic view of one embodiment of the present invention showing a waveform chart of a logic level of reset signal and a voltage level of the power supply of the power-on reset circuit;
  • FIG. 5 is a schematic view of one embodiment of the present invention indicating a power-on reset circuit
  • FIG. 6 is a schematic view of one embodiment of the present invention indicating a waveform chart of a voltage level of the reset signal and a voltage level of the power supply of a power-on reset circuit.
  • the present invention discloses a power-on reset circuit which is capable of changing logic level of a reset signal at multiple threshold voltages.
  • FIG. 3 is a schematic view of one embodiment of the present invention showing a power-on reset circuit 30 .
  • the power-on reset circuit 30 includes a first pull-up component 32 , a second pull-up component 34 and a first pull-down component 36 .
  • the first pull-up component 32 is coupled between a power supply V DD and a first node N 1 .
  • the second pull-up component 34 is coupled between the power supply V DD and a second node N 2 .
  • the first pull-down component 36 is coupled between the first node N 1 and a common node, which is grounded.
  • a first logic component X 1 is coupled between the first node N 1 and the second node N 2 .
  • the second pull-up component 34 is actuated based on a voltage, Reset_fb, at the second node N 2 .
  • the power-on reset circuit 30 further includes a capacitor C 1 , which is coupled between the first node N 1 and the common node.
  • the first pull-up component 32 is a P-MOSFET MP 1 , which has a source connected to the power supply V DD , a drain connected to the first node N 1 , and a gate connected to the common node.
  • the first pull down component 36 is an N-MOSFET MN D , which has a source connected to the common node, a drain connected to the first node N 1 , and a gate connected to the power supply V DD .
  • the second pull-up component 34 includes a voltage control component or a P-MOSFET MP 2 .
  • the P-MOSFET MP 2 has a source connected to the power supply V DD , a drain connected to the first node N 1 , and a gate connected to the second node N 2 .
  • FIG. 4 is a schematic view of one embodiment of the present invention showing a waveform chart of a logic level of reset signal and a voltage level of the power supply V DD of the power-on reset circuit 30 .
  • the voltage level of the power supply V DD is 0V
  • the first pull-up component 32 has not been connected, and a voltage at the first node N 1 is 0V.
  • a logic level at the second node N 2 , Reset_fb is 0.
  • the first pull-up component 32 and the second pull-up component 34 are conducted. Therefore, when the voltage level of the power supply V DD decreases and reaches a threshold voltage V RES2 , the first logic component X 1 makes a transition for outputting a logic level 1 so that the power-on reset circuit 30 may output a reset signal having a low logic level to other circuits, not shown, for resetting the circuits in logic level.
  • FIG. 5 is a schematic view of one embodiment of the present invention indicating a power-on reset circuit 50 .
  • the power-on reset circuit includes a first pull-up component 52 , a first pull-down component 54 , and a second pull-down component 56 .
  • the first pull-up circuit 52 is coupled between a power supply V DD and a first node N 1 .
  • the first pull-down component 54 is coupled between the first node N 1 and a common node, which is grounded.
  • a second pull-down component 56 is coupled between the common node and a third node N 3 .
  • a first logic component X 1 is coupled between the first node N 1 and the second node N 2
  • a second logic component X 2 is coupled between the second node N 2 and the third node N 3 .
  • the second pull-down component 56 is actuated based on a voltage at the third node N 3 .
  • the power-on reset circuit further includes a capacitor C 1 , which is coupled between the first node N 1 and the common node.
  • the first pull-up component 52 includes a P-MOSFET MP 1 which has a source coupled to the power supply, a drain coupled to the first node, and a gate coupled to the common node.
  • the first pull-down component includes an N-MOSFET MN D , which has a source coupled to the common node, a drain coupled to the first node, and a gate coupled to the power supply.
  • the second pull-down component 56 includes a voltage control component or an N-MOSFET MN 2 .
  • the N-MOSFET MN 2 has a source coupled to the common node, a drain coupled to the first node N 1 , and a gate coupled to the third node N 3 .
  • FIG. 6 is a schematic view of one embodiment of the present invention indicating a waveform chart of a voltage level of the reset signal and a voltage level of the power supply V DD of a power-on reset circuit 50 .
  • a logic level, Reset_fb, at the second node N 2 is 1
  • a voltage logic level, Reset at an output node of the power-on reset circuit 50 is 0.
  • the power-on reset circuit 50 When the logic level of the first logic component X 1 is 0, the logic level, Reset, at the output node is 1 and the voltage logic level, Reset_fb, at the second node N 2 is 0, the power-on reset circuit 50 outputs a reset signal, Reset, having a high logic level to other circuits, not shown, for resetting the circuits in logic level.
  • the first pull-down component 54 and the second pull-down component 56 are conducted. Therefore, when the voltage level of the power supply V DD decreases and reaches a threshold voltage V 4 , the first logic component X 1 and the second logic component X 2 make a transition, and, meanwhile, the threshold voltage V RES4 is greater than or equal to the threshold voltage V RES3 .
  • the power-on reset circuit 50 outputs a reset signal, Reset, having a low logic level to other circuits, not shown, for resetting the circuits in logic level.
US13/464,380 2011-05-06 2012-05-04 Power-on reset circuit Abandoned US20120280727A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/067,383 US8841947B2 (en) 2011-05-06 2013-10-30 Power-on reset circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100115890 2011-05-06
TW100115890A TW201246788A (en) 2011-05-06 2011-05-06 A power on reset circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/067,383 Division US8841947B2 (en) 2011-05-06 2013-10-30 Power-on reset circuit

Publications (1)

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US20120280727A1 true US20120280727A1 (en) 2012-11-08

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US13/464,380 Abandoned US20120280727A1 (en) 2011-05-06 2012-05-04 Power-on reset circuit
US14/067,383 Active US8841947B2 (en) 2011-05-06 2013-10-30 Power-on reset circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/067,383 Active US8841947B2 (en) 2011-05-06 2013-10-30 Power-on reset circuit

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US (2) US20120280727A1 (zh)
CN (1) CN102769450A (zh)
TW (1) TW201246788A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566969B2 (en) 2017-08-28 2020-02-18 Rolls-Royce Corporation Analog power-up reset circuit for logic level reset
CA3089121A1 (en) * 2018-01-26 2019-08-01 LineVision, Inc. System and method for power transmission line monitoring
CN110134174B (zh) * 2018-02-08 2021-03-19 华邦电子股份有限公司 具有磁滞功能的电源启动重置电路
CN109257035B (zh) * 2018-08-30 2022-04-05 龙迅半导体（合肥）股份有限公司 一种上电复位电路
KR20200140972A (ko) * 2019-06-07 2020-12-17 삼성전자주식회사 전압 감시 장치 및 그것을 포함하는 전자 장치
TWI692200B (zh) * 2019-08-27 2020-04-21 大陸商常州欣盛半導體技術股份有限公司 載帶芯片用開機關機重置電路及其工作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691887A (en) * 1995-06-06 1997-11-25 Micron Technology, Inc. Self-timing power-up circuit
US7019417B2 (en) * 2002-07-22 2006-03-28 Hynix Semiconductor Inc. Power-on reset circuit with current detection
US20100253399A1 (en) * 2009-04-01 2010-10-07 Austriamicrosystems Ag Circuit Arrangement for Operating Voltage Detection

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359297A (en) * 1993-10-28 1994-10-25 Motorola, Inc. VCO power-up circuit for PLL and method thereof
JP4462743B2 (ja) * 2000-03-29 2010-05-12 株式会社ルネサステクノロジ パワーオンリセット回路
KR100614645B1 (ko) * 2004-06-03 2006-08-22 삼성전자주식회사 파워-온 리셋회로

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691887A (en) * 1995-06-06 1997-11-25 Micron Technology, Inc. Self-timing power-up circuit
US7019417B2 (en) * 2002-07-22 2006-03-28 Hynix Semiconductor Inc. Power-on reset circuit with current detection
US20100253399A1 (en) * 2009-04-01 2010-10-07 Austriamicrosystems Ag Circuit Arrangement for Operating Voltage Detection

Also Published As

Publication number Publication date
US8841947B2 (en) 2014-09-23
US20140049300A1 (en) 2014-02-20
TW201246788A (en) 2012-11-16
CN102769450A (zh) 2012-11-07

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AS Assignment

Owner name: RAYDIUM SEMICONDUCTOR CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, LI PIN;REEL/FRAME:028159/0516

Effective date: 20120503

AS Assignment

Owner name: RAYDIUM SEMICONDUCTOR CORPORATION, TAIWAN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTION TO THE SPELLING OF CONVEYING PARTY NAME. THE CORRECT SPELLING OF NAME IS: LI PING LIN PREVIOUSLY RECORDED ON REEL 028159 FRAME 0516. ASSIGNOR(S) HEREBY CONFIRMS THE CONVEYING PARTY NAME, LI PIN LIN, SHOULD HAVE THE CORRECT SPELLING: LI PING LIN;ASSIGNOR:LIN, LI PING;REEL/FRAME:031506/0443

Effective date: 20120503

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION