US20120134125A1 - Method of manufacturing electronic component embedded circuit board - Google Patents

Method of manufacturing electronic component embedded circuit board Download PDF

Info

Publication number
US20120134125A1
US20120134125A1 US13/364,104 US201213364104A US2012134125A1 US 20120134125 A1 US20120134125 A1 US 20120134125A1 US 201213364104 A US201213364104 A US 201213364104A US 2012134125 A1 US2012134125 A1 US 2012134125A1
Authority
US
United States
Prior art keywords
electronic component
carrier
insulator
circuit pattern
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/364,104
Inventor
Byoung-Chan Kim
Young-Hwan Shin
Jong-Jin Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Priority to US13/364,104 priority Critical patent/US20120134125A1/en
Publication of US20120134125A1 publication Critical patent/US20120134125A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0376Etching temporary metallic carrier substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469Circuit made after mounting or encapsulation of the components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49133Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a method of manufacturing an electronic component embedded printed circuit board.
  • step with the trends towards smaller size and higher density in a current electronic component there has been an evolution of technology for advance in a package that connects the electronic component with a printed circuit board, and for providing a pattern having ultra-fine pitch, which are being produced in smaller and smaller sizes.
  • wire bonding which is a traditional method of connecting
  • an active research is now being devoted to apply the method on a bonding pad that is between 40 ⁇ m and 50 ⁇ m in pitch.
  • step with the trends towards a smaller size in pitch for an electronic component embedded board when forming a via using a laser drill, there are demands for establishing registration between layers and for narrowing a insulation distance in order to minimize the size of a via for interconnection, to reduce the thickness of an insulation layer.
  • FIG. 1 is a cross-sectional view of an electronic component embedded printed circuit board according to the related art. Illustrated in FIG. 1 are a core 1 , an electronic component 2 , an electrode 3 , a via 4 , 5 , insulators 6 a and 6 b , and a circuit pattern 7 .
  • an electronic component embedded printed circuit board includes a core 1 , which embeds an electronic component 2 therein, and the electronic component 2 is connected with a circuit pattern 7 through a via 4 , which is placed on the electronic component 2 and the core 1 .
  • a method of manufacturing an electronic component embedded printed circuit board in accordance with the related art will be described with reference to FIGS. 2 to 7 .
  • FIGS. 2 to 7 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board according to the related art.
  • FIGS. 2 to 7 Illustrated in FIGS. 2 to 7 are a core 1 , a cavity 1 a , an electronic component 2 , an electrode 3 , a via 4 , 5 , insulators 6 a and 6 b , a circuit pattern 7 , a solder ball 8 and an adhesive tape 9 .
  • an adhesive tape 9 is attached at the bottom of the core 1 for fixing the electronic component 2 in accordance with the related art.
  • the electronic component 2 may be landed in the cavity 1 a , which is illustrated in FIG. 3 , and then an insulator 6 a may be stacked on the top side of the core 1 , which is shown in FIG. 4 .
  • the adhesive tape 9 may be removed, and then an insulator 6 b may be stacked at the bottom of the core 1 , which is illustrated in FIG. 6 .
  • a via 4 may formed, and then several circuit patterns 7 can be formed as illustrated in FIG. 7 .
  • an electrode 3 of the electronic component 2 may be damaged by a layer drill during the process.
  • the adhesive tape 9 may not be completely removed, and thus the product reliability and yield ratio may be declined.
  • An aspect of the invention provides a method of manufacturing a printed circuit board, in which an electronic component may be embedded for improving the degree of conformation and improving the yield by simplifying the production process
  • Another aspect of the invention provides an electronic component embedded printed circuit board, which includes: an insulator; a first circuit pattern buried in one side of the insulator; an electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern; and a second circuit pattern buried in an other side of the insulator.
  • the electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • another aspect of the invention provides a method of manufacturing an electronic component embedded printed circuit board.
  • the method includes: providing a first carrier having a first circuit pattern formed on one surface thereof; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding an electronic component to the first circuit pattern; stacking one side of an insulator on one side of the first carrier to cover the electronic component; compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and removing the first carrier and the second carrier.
  • the electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern formed on one surface thereof can be performed simultaneously through: providing the first carrier and the second carrier coupled together with an adhesive layer; forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and separating the first carrier and the second carrier.
  • a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • an electronic component embedded printed circuit board which includes: an insulator; a first circuit pattern buried in one side of the insulator; a first electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern; a second circuit pattern buried in an other side of the insulator; and a second electronic component embedded in the insulator and connected with the second circuit pattern.
  • the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • an adhesive part interposed between the first electronic component and the second electronic component can be made of a different material from that of the insulator.
  • another aspect of the invention further provides a method of manufacturing an electronic component embedded printed circuit board.
  • the method can include: providing a first carrier having a first circuit pattern formed on one surface thereof; flip-chip bonding a first electronic component to the first circuit pattern; stacking a first insulator on one side of the first carrier to cover the first electronic component; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding a second electronic component to the second circuit pattern; stacking a second insulator on one side of the second carrier to cover the second electronic component; compressing the first insulator and the second insulator such that the first electronic component and the second electronic component face each other; and removing the first carrier and the second carrier.
  • the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern formed on one surface thereof can be performed simultaneously through: providing the first carrier and the second carrier coupled together with an adhesive layer; forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and separating the first carrier and the second carrier.
  • a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • another aspect of the invention further provides a method of manufacturing an electronic component embedded printed circuit board.
  • the method can include: providing a first carrier having a first circuit pattern formed on one surface thereof; flip-chip bonding a first electronic component to the first circuit pattern; adhering a second electronic component to the first electronic component by using an adhesive part; stacking one side of an insulator on the first carrier to cover the first electronic component and the second electronic component; forming a via and a second circuit pattern on another side of the insulator, the via configured to be connected with the second electronic component and the second circuit pattern configured to be electrically connected with the via; and removing the first carrier.
  • the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • FIG. 1 is a cross sectional view illustrating an electronic component embedded printed circuit board according to the related art.
  • FIGS. 2 to 7 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board according to the related art.
  • FIGS. 8 to 11 are cross-sectional views illustrating embodiments of an electronic component embedded printed circuit board according to an aspect of the present invention.
  • FIG. 12 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIGS. 8 to 11 .
  • FIGS. 13 to 25 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 12 .
  • FIG. 26 is a cross sectional view illustrating a first disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIG. 27 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 26 .
  • FIGS. 28 to 34 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 27 .
  • FIG. 35 is a cross sectional view illustrating a second embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIG. 36 is a flowchart illustrating a second disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIGS. 37 to 39 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board illustrated in FIG. 36 .
  • first and second may be used to describe various components, such components must not be limited to the above terms.
  • the above terms are used only to distinguish one component from another.
  • a first component may be referred to as a second component without departing from the scope of rights of the present invention, and likewise a second component may be referred to as a first component.
  • the term “and/or” encompasses both combinations of the plurality of related items disclosed and any item from among the plurality of related items disclosed.
  • FIGS. 8 to 11 are cross-sectional views illustrating embodiments of an electronic component embedded printed circuit board according to an aspect of the present invention. Illustrated in FIGS. 8 to 11 are circuit patterns 15 a , 15 b and 15 c , a via 16 , an electronic component 20 , a solder bump 21 , a stud bump 22 , insulators 30 and 36 , an underfill part 32 and a solder resist 34 .
  • an electronic component embedded printed circuit board in accordance with the present embodiment includes an insulator 30 , which embeds a first circuit pattern 15 a , a second circuit pattern 15 b and an electronic component 20 , and the electronic component 20 can be flip-chip bonded with the first circuit pattern 15 a .
  • an electronic component embedded printed circuit board according to the present embodiment presents that the electronic component 20 can be simply flip-chip bonded with the circuit pattern 15 a embedded in the insulator 30 , without processing a via 4 ( FIG. 7 ) for connecting to the electronic component 20 .
  • a via 4 FIG. 7
  • FIGS. 8 and 9 a structure using a solder bump 21 is presented.
  • FIGS. 10 and 11 a structure using a gold stud bump 22 is presented. It is appreciated that the flip-chip bonding structure can be also implemented through various materials and structures.
  • a via 16 which penetrates through the insulator 30 , can be formed for electrically connecting the first circuit pattern 15 a to the second circuit pattern 15 b .
  • a hole (not illustrated) can be formed in the insulation layer 30 by using a layer drill or a mechanical drill, and then a conductive material can be filled inside the penetrated hole by way of plating.
  • an additional insulator 36 can be respectively stacked on each side of the insulator 30 , and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36 .
  • a solder resist 34 can be formed at an outermost layer for protecting the circuit patterns 15 c and 15 d , and an aperture can be formed in some portions for connecting to an outside device.
  • an underfill part 32 can be formed at the bottom of the electronic component 20 .
  • the underfill part 32 can be made of a material that is different from the insulator 30 covering the electronic component 20 .
  • the underfill part 32 can be made of a material that is the same as the insulator 30 .
  • FIG. 12 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIGS. 8 to 11 .
  • FIGS. 13 to 25 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 12 . Illustrated in FIGS.
  • 13 to 25 are a adhesive film 11 , a first carrier 12 a , a second carrier 12 b , a first seed layer 13 a , a second seed layer 13 b , plating resists 14 a and 14 b , circuit patterns 15 a , 15 b , 15 c and 15 d , a via 16 , an electronic component 20 , a solder bump 21 , a stud bump 22 , insulators 30 and 36 , an underfill part 32 and a solder resist 34 .
  • a first carrier 12 a having a first circuit pattern 15 a formed on a surface thereof and a second carrier 12 b having a second circuit pattern 15 b formed on a surface thereof are prepared (S 110 , S 120 ).
  • the first carrier 12 a and the second carrier 12 b in which the first circuit pattern 15 a is formed on a surface of the first carrier 12 a and the second circuit pattern 15 b is formed on a surface of the second carrier 12 b , can be prepared individually or collectively.
  • the first carrier 12 a and the second carrier 12 b which are coupled together with an adhesive layer 11 , are prepared (S 101 ).
  • the first circuit pattern 15 a can be formed on the first carrier 12 a
  • the second circuit pattern 15 b can be formed on the second carrier 12 b by way of electroplating (S 102 ), and then the first carrier 12 a and the second carrier 12 b can be separated from each other (S 103 ).
  • a carrier being made of a material containing copper will be used in this embodiment.
  • a chemical etching method can be used as a method of removing the carrier later.
  • seed layers 13 a and 13 b which are made of a different material from that of the carriers 12 a and 12 b , can be formed on each surface of the carriers 12 a and 12 b .
  • the circuit patterns 15 a and 15 b can be formed on each surface of the seed layers 13 a and 13 b by using etching resists 14 a and 14 b .
  • the seed layers 13 a and 13 b of nickel materials can be formed. The results of using such a structure will be described later.
  • a material which has a flexible adhesive strength being changed by the temperature, can be used as the adhesive layer 11 interposed between the first carrier 12 a and the second carrier 12 b . This is because it is good to have a low adhesive strength when separating the first carrier 12 a and the second carrier 12 b even though a high adhesive strength is necessary when forming a circuit pattern.
  • Such an adhesive layer 11 can be a thermoplastic adhesive layer and an effervescent adhesive layer.
  • the first carrier 12 a having the first circuit pattern 15 a formed thereon is prepared. And then, as illustrated in FIG. 16 , the electronic component 20 can be flip-chip bonded with the first circuit pattern 15 a (S 130 ).
  • the electronic component 20 can be flip-chip bonded by using the solder bump 21 , which is illustrated in FIG. 16 , or by using the gold stud bump 22 , which is illustrated in FIG. 17 .
  • an insulator 30 can be stacked on a surface of the first carrier 12 a such that the electronic component 20 is completely covered (S 140 ). If necessary, before stacking the insulator 30 , an additional underfill part 32 can be formed at the bottom of the electronic component, which is illustrated in FIG. 19 .
  • the second carrier 12 b having the second circuit pattern 15 b formed on one surface thereof can be compressed on another side of the insulator 30 (S 150 ).
  • the second carrier 12 b having the second circuit pattern 15 b formed on one surface thereof can be manufactured individually with the first carrier 12 a having the first circuit pattern 15 a formed on one surface thereof, they can be manufactured simultaneously in the same process, which has been already described above.
  • the first carrier 12 a and the second carrier 12 b can be removed (S 160 ).
  • the first circuit pattern 15 a and the second circuit pattern 15 b can be buried in the insulator 30 . That is, the first circuit pattern 15 a and the second circuit pattern 15 b are not only embedded in the insulator 30 , but also the electronic component 20 can be embedded inside the insulator 30 .
  • the method of chemical etching can be used.
  • the carriers 12 a and 12 b can be chemically removed.
  • the seed layers 13 a and 13 b when forming the seed layers 13 a and 13 b , which are made of a material containing nickel, on each surface of the carriers 12 a and 12 b , which are made of a material containing copper, the seed layers 13 a and 13 b can performed as a barrier layer so as to prevent the circuit patterns 15 a and 15 b embedded in the insulator 30 from being damaged while removing the carriers 12 a and 12 b by providing the etching liquid.
  • the seed layers 13 a and 13 b can be also etched by using etched liquid, which only reacts with nickel.
  • the circuit patterns 15 a and 15 b formed on the insulator 30 cannot react with the etching liquid, which is for removing the seed layers 13 a and 13 b , and thus the seed layers 13 a and 13 b can be completely removed without damaging the circuit patterns 15 a and 15 b.
  • the first circuit pattern 15 a and the second circuit pattern 15 b can be electrically connected with the via 16 , which penetrates through the insulator 30 .
  • the circuit patterns 15 a and 15 b can be protected by forming a solder resist 34 at an outermost layer.
  • an additional insulator 36 can be respectively stacked on each side of the insulator 30 , and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36 .
  • FIG. 26 is a cross sectional view illustrating a first disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention. Illustrated in FIG. 26 are circuit patterns 15 a , 15 b , 15 c and 15 d , a via 16 , electronic components 20 a and 20 b , solder bumps 21 a and 21 b , insulators 30 and 36 , and a solder resist 34 .
  • An electronic component embedded printed circuit board according to the present embodiment can have two electronic components 20 a and 20 b embedded in one insulator 30 , in which the electronic components 20 a and 20 b can be respectively flip-chip bonded with circuit patterns 15 a and 15 b that are buried in the insulator 30 . Through such a structure, an electronic component embedded circuit board having higher density can be implemented.
  • the present embodiment has the structure of an electronic component embedded circuit board described above, so that redundant explanations are omitted.
  • FIG. 27 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 26 .
  • FIGS. 28 to 34 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 27 . Illustrated in FIGS. 28 to 34 are a first carrier 12 a , a second carrier 12 b , a first seed layer 13 a , a second seed layer 13 b , circuit patterns 15 a , 15 b , 15 c and 15 d , a via 16 , a first electronic component 20 a , a second electronic component 20 b , solder bumps 21 a and 21 b , insulators 30 and 36 , an underfill part 32 and a solder resist 34 .
  • a first carrier 12 a having a first circuit pattern 15 a formed on one surface thereof is prepared (S 210 ).
  • a first electronic component 20 a can be flip-chip bonded to the first circuit pattern 15 a (S 220 ), and a first insulator 30 a can be stacked on one side of the first carrier 12 a to cover the first electronic component 20 a (S 230 ).
  • an underfill part can be formed before stacking the first insulator 30 a . Illustrated in FIG. 31 is the underfill part 32 a formed at the bottom of the first electronic component.
  • a second carrier 12 b having a second circuit pattern 15 b formed on one surface thereof is prepared (S 240 ).
  • a second electronic component 20 b can be flip-chip bonded to the second circuit pattern 15 b (S 250 ), and a second insulator 30 b can be stacked on one side of the second carrier 12 b to cover the second electronic component 20 b (S 260 ).
  • an underfill part 32 b can be formed before stacking the second insulator 30 b , which can be done in the same process as the first insulator 30 a.
  • a method of preparing the first carrier having the first circuit pattern formed on one surface thereof and the second carrier having the second circuit pattern formed on one surface thereof can be the same as the one described above.
  • the method includes: providing the first carrier 12 a and the second carrier 12 b coupled together with an adhesive layer, which is illustrated in FIG. 13 (S 201 ); forming the first circuit pattern 15 a on the first carrier 12 a and the second circuit pattern 15 b on the second carrier 12 b through electroplating, which is illustrated in FIG. 14 (S 202 ); and separating the first carrier 12 a and the second carrier 12 b (S 203 ).
  • the first insulator 30 a and the second insulator 30 b can be compressed against each other such that the first electronic component 20 a and the second electronic component 20 b face each other (S 270 ).
  • the first insulator 30 a and the second insulator 30 b can become one insulator 30 ( FIG. 32 ), and thus the first electronic component 20 a and the second electronic component 20 b can be embedded in the insulator 30 .
  • first electronic component 20 a can be flip-chip bonded with the first circuit pattern 15 a
  • second electronic component 20 b can be flip-chip bonded with the second circuit pattern 15 b.
  • the first carrier 12 a and the second carrier 12 b can be removed (S 280 ).
  • an insulation layer 36 can be stacked on both sides of the insulator 30 , and a circuit pattern can be formed on each insulation layer 36 , so that an electronic component embedded circuit board having a 4 layered structure can be manufactured.
  • a solder resist can be formed on a surface of the insulator 30 having the first circuit pattern 15 a and the second circuit pattern 15 b embedded therein, without stacking the insulation layer 36 .
  • the method of chemical etching can be used.
  • the seed layers 13 a and 13 b which are made of a different material from that of the carriers 12 a and 12 b , are formed on surfaces of the carriers 12 a and 12 b , the circuit patterns 15 a and 15 b can be protected by dividing the etching process.
  • FIG. 35 is a cross sectional view illustrating a second embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention. Illustrated in FIG. 35 are circuit patterns 15 a , 15 b , 15 c and 15 d , a via 16 and 17 , electronic components 20 a and 20 b , a solder bump 21 , insulators 30 and 36 and a solder resist 34 .
  • an electronic component embedded printed circuit board can have two electronic components 20 a and 20 b embedded in one insulator 30 , in which one of the electronic components can be flip-chip bonded with a circuit pattern 15 a and the other one can be connected through a via 17 .
  • the electronic components 20 a and 20 b can be adhered by using an adhesive part 38 .
  • the present embodiment presents that only one 20 a of the two electronic components 20 a and 20 b is flip-chip bonded and the other one 20 b is connected with the circuit pattern through the via 17 .
  • the present embodiment has the structure of an electronic component embedded circuit board described above, so that redundant explanations are omitted.
  • FIG. 36 is a flowchart illustrating a second disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIGS. 37 to 39 are flowcharts illustrating a method of manufacturing an electronic component embedded printed circuit board illustrated in FIG. 36 . Illustrated in FIGS. 37 to 39 are circuit patterns 15 a , 15 b , 15 c and 15 d , a via 16 and 17 , electronic components 20 a and 20 b , a solder bump 21 , insulators 30 and 36 , and a solder resist 34 .
  • a first carrier 12 a having a first circuit pattern 15 a formed on one surface thereof is prepared (S 310 ), and a first electronic component 20 a can be flip-chip bonded to the first circuit pattern 15 a (S 320 ).
  • a second electronic component 20 b can be adhered to the first electronic component 20 a by using an adhesive part 38 (S 330 ).
  • an adhesive part 38 (S 330 ).
  • an epoxy type adhesive or a film type adhesive can be used as the adhesive part 38 .
  • one side of an insulator 30 can be stacked on the first carrier 12 a to cover the first electronic component 20 a and the second electronic component 20 b (S 340 ). As illustrated in FIG. 37 , the first electronic component 20 a and the second electronic component 20 b are covered in the insulator 30 through such a process.
  • a via 17 and a second circuit pattern 15 b can be formed on another side of the insulator 30 , in which the via is connected with the second electronic component and the second circuit pattern is electrically connected with the via (S 350 ).
  • a via hole can be formed in the insulator by using a layer drill, and then a conductive material can be filled inside the via hole by way of electroless plating and electroplating.
  • the second circuit pattern 15 b can be simultaneously formed on the insulator through the via forming process by using electroless plating or electroplating.
  • the first carrier 12 a can be removed (S 360 ), and thus an electronic component embedded printed circuit board can be manufactured by forming a solder resist at an outermost layer.
  • an additional insulator 36 can be respectively stacked on each side of the insulator 30 , and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36 .
  • the degree of conformation for an electrical component can be improved by embedding the electrical component using a flip-chip bonding method, and the yield can improved by simplifying the production process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

An electronic component embedded printed circuit board and a method for manufacturing the same are disclosed. The method includes: providing a first carrier having a first circuit pattern formed on one surface thereof; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding an electronic component to the first circuit pattern; stacking one side of an insulator on one side of the first carrier to cover the electronic component; compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and removing the first carrier and the second carrier. The method can improve the degree of conformation for an electrical component by embedding the electrical component using a flip-chip bonding method and can improve the yield by simplifying the production process.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional of U.S. application Ser. No. 12/359,416, filed on Jan. 26, 2009, which claims the benefit of Korean Patent Application No. 10-2008-0070662 filed with the Korean Intellectual Property Office on Jul. 21, 2008, the entire contents of each of which are incorporated herein by reference.
  • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a method of manufacturing an electronic component embedded printed circuit board.
  • 2. Description of the Related Art
  • In step with the trends towards smaller size and higher density in a current electronic component, there has been an evolution of technology for advance in a package that connects the electronic component with a printed circuit board, and for providing a pattern having ultra-fine pitch, which are being produced in smaller and smaller sizes. In particular, in a case of wire bonding, which is a traditional method of connecting, an active research is now being devoted to apply the method on a bonding pad that is between 40 μm and 50 μm in pitch.
  • In step with the trends towards a smaller size in pitch for an electronic component embedded board, when forming a via using a laser drill, there are demands for establishing registration between layers and for narrowing a insulation distance in order to minimize the size of a via for interconnection, to reduce the thickness of an insulation layer.
  • FIG. 1 is a cross-sectional view of an electronic component embedded printed circuit board according to the related art. Illustrated in FIG. 1 are a core 1, an electronic component 2, an electrode 3, a via 4, 5, insulators 6 a and 6 b, and a circuit pattern 7.
  • As illustrated in FIG. 1, an electronic component embedded printed circuit board according to the related art includes a core 1, which embeds an electronic component 2 therein, and the electronic component 2 is connected with a circuit pattern 7 through a via 4, which is placed on the electronic component 2 and the core 1. Below, a method of manufacturing an electronic component embedded printed circuit board in accordance with the related art will be described with reference to FIGS. 2 to 7.
  • FIGS. 2 to 7 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board according to the related art.
  • Illustrated in FIGS. 2 to 7 are a core 1, a cavity 1 a, an electronic component 2, an electrode 3, a via 4, 5, insulators 6 a and 6 b, a circuit pattern 7, a solder ball 8 and an adhesive tape 9.
  • As illustrated in FIG. 2, after forming a cavity 1 a, which is for embedding an electronic component 2, by processing a core 1 having a via 5 formed thereon, an adhesive tape 9 is attached at the bottom of the core 1 for fixing the electronic component 2 in accordance with the related art.
  • After that, the electronic component 2 may be landed in the cavity 1 a, which is illustrated in FIG. 3, and then an insulator 6 a may be stacked on the top side of the core 1, which is shown in FIG. 4.
  • Then, as illustrated in FIG. 5, the adhesive tape 9 may be removed, and then an insulator 6 b may be stacked at the bottom of the core 1, which is illustrated in FIG. 6.
  • After that, a via 4 may formed, and then several circuit patterns 7 can be formed as illustrated in FIG. 7.
  • According to the related art, however, there may be a problem of defective interconnection when forming the via 4 for connecting the electronic component 2 with the circuit patterns 7. In addition, an electrode 3 of the electronic component 2 may be damaged by a layer drill during the process.
  • Furthermore, the adhesive tape 9 may not be completely removed, and thus the product reliability and yield ratio may be declined.
  • SUMMARY
  • An aspect of the invention provides a method of manufacturing a printed circuit board, in which an electronic component may be embedded for improving the degree of conformation and improving the yield by simplifying the production process
  • Another aspect of the invention provides an electronic component embedded printed circuit board, which includes: an insulator; a first circuit pattern buried in one side of the insulator; an electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern; and a second circuit pattern buried in an other side of the insulator.
  • Here, the electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • Yet, another aspect of the invention provides a method of manufacturing an electronic component embedded printed circuit board. The method includes: providing a first carrier having a first circuit pattern formed on one surface thereof; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding an electronic component to the first circuit pattern; stacking one side of an insulator on one side of the first carrier to cover the electronic component; compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and removing the first carrier and the second carrier.
  • Here, the electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • In addition, the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern formed on one surface thereof can be performed simultaneously through: providing the first carrier and the second carrier coupled together with an adhesive layer; forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and separating the first carrier and the second carrier.
  • Additionally, a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • Still, another aspect of the invention provides an electronic component embedded printed circuit board, which includes: an insulator; a first circuit pattern buried in one side of the insulator; a first electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern; a second circuit pattern buried in an other side of the insulator; and a second electronic component embedded in the insulator and connected with the second circuit pattern.
  • Here, the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • In addition, an adhesive part interposed between the first electronic component and the second electronic component can be made of a different material from that of the insulator.
  • Still, another aspect of the invention further provides a method of manufacturing an electronic component embedded printed circuit board. The method can include: providing a first carrier having a first circuit pattern formed on one surface thereof; flip-chip bonding a first electronic component to the first circuit pattern; stacking a first insulator on one side of the first carrier to cover the first electronic component; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding a second electronic component to the second circuit pattern; stacking a second insulator on one side of the second carrier to cover the second electronic component; compressing the first insulator and the second insulator such that the first electronic component and the second electronic component face each other; and removing the first carrier and the second carrier.
  • Here, the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • In addition, the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern formed on one surface thereof can be performed simultaneously through: providing the first carrier and the second carrier coupled together with an adhesive layer; forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and separating the first carrier and the second carrier.
  • Additionally, a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • Still, another aspect of the invention further provides a method of manufacturing an electronic component embedded printed circuit board. The method can include: providing a first carrier having a first circuit pattern formed on one surface thereof; flip-chip bonding a first electronic component to the first circuit pattern; adhering a second electronic component to the first electronic component by using an adhesive part; stacking one side of an insulator on the first carrier to cover the first electronic component and the second electronic component; forming a via and a second circuit pattern on another side of the insulator, the via configured to be connected with the second electronic component and the second circuit pattern configured to be electrically connected with the via; and removing the first carrier.
  • Here, the first electronic component can be flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
  • Additionally, a first seed layer can be formed on one side of the first carrier, in which the first seed layer is made of a different material from that of the first carrier, and the removing of the first carrier can include removing the first seed layer.
  • Additional aspects and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross sectional view illustrating an electronic component embedded printed circuit board according to the related art.
  • FIGS. 2 to 7 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board according to the related art.
  • FIGS. 8 to 11 are cross-sectional views illustrating embodiments of an electronic component embedded printed circuit board according to an aspect of the present invention.
  • FIG. 12 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIGS. 8 to 11.
  • FIGS. 13 to 25 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 12.
  • FIG. 26 is a cross sectional view illustrating a first disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIG. 27 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 26.
  • FIGS. 28 to 34 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 27.
  • FIG. 35 is a cross sectional view illustrating a second embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIG. 36 is a flowchart illustrating a second disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention.
  • FIGS. 37 to 39 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board illustrated in FIG. 36.
  • DETAILED DESCRIPTION
  • As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to particular modes of practice, and it is to be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the present invention are encompassed in the present invention. In the description of the present invention, certain detailed explanations of related art are omitted when it is deemed that they may unnecessarily obscure the essence of the invention.
  • While such terms as “first” and “second,” etc., may be used to describe various components, such components must not be limited to the above terms. The above terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of rights of the present invention, and likewise a second component may be referred to as a first component. The term “and/or” encompasses both combinations of the plurality of related items disclosed and any item from among the plurality of related items disclosed.
  • The terms used in the present specification are merely used to describe particular embodiments, and are not intended to limit the present invention. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In the present specification, it is to be understood that the terms such as “including” or “having,” etc., are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.
  • The method of manufacturing an electronic component embedded printed circuit board according to embodiments of the invention will be described below in more detail with reference to the accompanying drawings. Those components that are the same or are in correspondence are rendered the same reference numeral regardless of the figure number, and redundant explanations are omitted.
  • FIGS. 8 to 11 are cross-sectional views illustrating embodiments of an electronic component embedded printed circuit board according to an aspect of the present invention. Illustrated in FIGS. 8 to 11 are circuit patterns 15 a, 15 b and 15 c, a via 16, an electronic component 20, a solder bump 21, a stud bump 22, insulators 30 and 36, an underfill part 32 and a solder resist 34.
  • As illustrated in FIG. 8, an electronic component embedded printed circuit board in accordance with the present embodiment includes an insulator 30, which embeds a first circuit pattern 15 a, a second circuit pattern 15 b and an electronic component 20, and the electronic component 20 can be flip-chip bonded with the first circuit pattern 15 a. In other words, an electronic component embedded printed circuit board according to the present embodiment presents that the electronic component 20 can be simply flip-chip bonded with the circuit pattern 15 a embedded in the insulator 30, without processing a via 4 (FIG. 7) for connecting to the electronic component 20. Through such a method, the problem of defective interconnection due to degraded adhesion when processing a via can be solved.
  • As such, several methods of implementing the flip-chip bonding structure are disclosed below. In FIGS. 8 and 9, a structure using a solder bump 21 is presented. In FIGS. 10 and 11, a structure using a gold stud bump 22 is presented. It is appreciated that the flip-chip bonding structure can be also implemented through various materials and structures.
  • Meanwhile, a via 16, which penetrates through the insulator 30, can be formed for electrically connecting the first circuit pattern 15 a to the second circuit pattern 15 b. For forming the via 16, a hole (not illustrated) can be formed in the insulation layer 30 by using a layer drill or a mechanical drill, and then a conductive material can be filled inside the penetrated hole by way of plating.
  • In addition, as illustrated in FIG. 8, when implementing a multi-layered structure, an additional insulator 36 can be respectively stacked on each side of the insulator 30, and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36.
  • A solder resist 34 can be formed at an outermost layer for protecting the circuit patterns 15 c and 15 d, and an aperture can be formed in some portions for connecting to an outside device.
  • Meanwhile, an underfill part 32 can be formed at the bottom of the electronic component 20. As illustrated in FIGS. 8 and 10, the underfill part 32 can be made of a material that is different from the insulator 30 covering the electronic component 20. As illustrated in FIGS. 9 and 11, the underfill part 32 can be made of a material that is the same as the insulator 30.
  • Until now, the structure of an electronic component embedded printed circuit board according to an aspect of the present invention has been described. Below, a method of manufacturing an electronic component embedded printed circuit board having the same structure will be described.
  • FIG. 12 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIGS. 8 to 11. FIGS. 13 to 25 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 12. Illustrated in FIGS. 13 to 25 are a adhesive film 11, a first carrier 12 a, a second carrier 12 b, a first seed layer 13 a, a second seed layer 13 b, plating resists 14 a and 14 b, circuit patterns 15 a, 15 b, 15 c and 15 d, a via 16, an electronic component 20, a solder bump 21, a stud bump 22, insulators 30 and 36, an underfill part 32 and a solder resist 34. First of all, a first carrier 12 a having a first circuit pattern 15 a formed on a surface thereof and a second carrier 12 b having a second circuit pattern 15 b formed on a surface thereof are prepared (S110, S120). The first carrier 12 a and the second carrier 12 b, in which the first circuit pattern 15 a is formed on a surface of the first carrier 12 a and the second circuit pattern 15 b is formed on a surface of the second carrier 12 b, can be prepared individually or collectively.
  • In other words, as illustrated in FIG. 13, the first carrier 12 a and the second carrier 12 b, which are coupled together with an adhesive layer 11, are prepared (S101). As illustrated in FIG. 14, the first circuit pattern 15 a can be formed on the first carrier 12 a, and the second circuit pattern 15 b can be formed on the second carrier 12 b by way of electroplating (S102), and then the first carrier 12 a and the second carrier 12 b can be separated from each other (S103).
  • Although an adhesive film can be used as the carriers 12 a and 12 b, a carrier being made of a material containing copper will be used in this embodiment. When using such a carrier, which is made of a metallic material, a chemical etching method can be used as a method of removing the carrier later.
  • As illustrated in FIGS. 13 to 15, when using the carriers 12 a and 12 b, which are made of a material containing copper, seed layers 13 a and 13 b, which are made of a different material from that of the carriers 12 a and 12 b, can be formed on each surface of the carriers 12 a and 12 b. Then, the circuit patterns 15 a and 15 b can be formed on each surface of the seed layers 13 a and 13 b by using etching resists 14 a and 14 b. For example, the seed layers 13 a and 13 b of nickel materials can be formed. The results of using such a structure will be described later.
  • A material, which has a flexible adhesive strength being changed by the temperature, can be used as the adhesive layer 11 interposed between the first carrier 12 a and the second carrier 12 b. This is because it is good to have a low adhesive strength when separating the first carrier 12 a and the second carrier 12 b even though a high adhesive strength is necessary when forming a circuit pattern. Such an adhesive layer 11, for example, can be a thermoplastic adhesive layer and an effervescent adhesive layer.
  • Through the method described above, the first carrier 12 a having the first circuit pattern 15 a formed thereon is prepared. And then, as illustrated in FIG. 16, the electronic component 20 can be flip-chip bonded with the first circuit pattern 15 a (S130). Here, the electronic component 20 can be flip-chip bonded by using the solder bump 21, which is illustrated in FIG. 16, or by using the gold stud bump 22, which is illustrated in FIG. 17.
  • After that, as illustrated in FIG. 18, an insulator 30 can be stacked on a surface of the first carrier 12 a such that the electronic component 20 is completely covered (S140). If necessary, before stacking the insulator 30, an additional underfill part 32 can be formed at the bottom of the electronic component, which is illustrated in FIG. 19.
  • As illustrated in FIGS. 20 and 21, the second carrier 12 b having the second circuit pattern 15 b formed on one surface thereof can be compressed on another side of the insulator 30 (S150). Although the second carrier 12 b having the second circuit pattern 15 b formed on one surface thereof can be manufactured individually with the first carrier 12 a having the first circuit pattern 15 a formed on one surface thereof, they can be manufactured simultaneously in the same process, which has been already described above.
  • After compressing the second carrier 12 b on the insulator 30 by using heat and pressure, as illustrated in FIG. 22, the first carrier 12 a and the second carrier 12 b can be removed (S160). Thus, the first circuit pattern 15 a and the second circuit pattern 15 b can be buried in the insulator 30. That is, the first circuit pattern 15 a and the second circuit pattern 15 b are not only embedded in the insulator 30, but also the electronic component 20 can be embedded inside the insulator 30.
  • Meanwhile, in order to remove the carriers 12 a and 12 b, the method of chemical etching can be used. In other words, by using etching liquid, the carriers 12 a and 12 b can be chemically removed.
  • As described above, when forming the seed layers 13 a and 13 b, which are made of a material containing nickel, on each surface of the carriers 12 a and 12 b, which are made of a material containing copper, the seed layers 13 a and 13 b can performed as a barrier layer so as to prevent the circuit patterns 15 a and 15 b embedded in the insulator 30 from being damaged while removing the carriers 12 a and 12 b by providing the etching liquid.
  • After etching the carriers 12 a and 12 b made of a material containing copper, the seed layers 13 a and 13 b can be also etched by using etched liquid, which only reacts with nickel. In this case, the circuit patterns 15 a and 15 b formed on the insulator 30 cannot react with the etching liquid, which is for removing the seed layers 13 a and 13 b, and thus the seed layers 13 a and 13 b can be completely removed without damaging the circuit patterns 15 a and 15 b.
  • Next, as illustrated in FIG. 23, the first circuit pattern 15 a and the second circuit pattern 15 b can be electrically connected with the via 16, which penetrates through the insulator 30. As illustrated in FIG. 24, the circuit patterns 15 a and 15 b can be protected by forming a solder resist 34 at an outermost layer.
  • In addition, as illustrated in FIG. 25, when implementing a multi-layered structure, an additional insulator 36 can be respectively stacked on each side of the insulator 30, and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36.
  • Below, a first disclosed embodiment of an electronic component embedded printed circuit board will be described in accordance with another aspect of the present invention.
  • FIG. 26 is a cross sectional view illustrating a first disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention. Illustrated in FIG. 26 are circuit patterns 15 a, 15 b, 15 c and 15 d, a via 16, electronic components 20 a and 20 b, solder bumps 21 a and 21 b, insulators 30 and 36, and a solder resist 34. An electronic component embedded printed circuit board according to the present embodiment can have two electronic components 20 a and 20 b embedded in one insulator 30, in which the electronic components 20 a and 20 b can be respectively flip-chip bonded with circuit patterns 15 a and 15 b that are buried in the insulator 30. Through such a structure, an electronic component embedded circuit board having higher density can be implemented.
  • Except that the two electronic components 20 a and 20 b are embedded in one insulator 30 and they are flip-chip bonded respectively, the present embodiment has the structure of an electronic component embedded circuit board described above, so that redundant explanations are omitted.
  • Below, a method of manufacturing an electronic component embedded circuit board having the same structure above will be described.
  • FIG. 27 is a flowchart illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 26. FIGS. 28 to 34 are flow diagrams illustrating a method of manufacturing an electronic component embedded printed circuit board shown in FIG. 27. Illustrated in FIGS. 28 to 34 are a first carrier 12 a, a second carrier 12 b, a first seed layer 13 a, a second seed layer 13 b, circuit patterns 15 a, 15 b, 15 c and 15 d, a via 16, a first electronic component 20 a, a second electronic component 20 b, solder bumps 21 a and 21 b, insulators 30 and 36, an underfill part 32 and a solder resist 34. First of all, a first carrier 12 a having a first circuit pattern 15 a formed on one surface thereof is prepared (S210). A first electronic component 20 a can be flip-chip bonded to the first circuit pattern 15 a (S220), and a first insulator 30 a can be stacked on one side of the first carrier 12 a to cover the first electronic component 20 a (S230). It is appreciated that an underfill part can be formed before stacking the first insulator 30 a. Illustrated in FIG. 31 is the underfill part 32 a formed at the bottom of the first electronic component.
  • Likewise, a second carrier 12 b having a second circuit pattern 15 b formed on one surface thereof is prepared (S240). A second electronic component 20 b can be flip-chip bonded to the second circuit pattern 15 b (S250), and a second insulator 30 b can be stacked on one side of the second carrier 12 b to cover the second electronic component 20 b (S260). It is apparent that an underfill part 32 b can be formed before stacking the second insulator 30 b, which can be done in the same process as the first insulator 30 a.
  • A method of preparing the first carrier having the first circuit pattern formed on one surface thereof and the second carrier having the second circuit pattern formed on one surface thereof can be the same as the one described above. The method includes: providing the first carrier 12 a and the second carrier 12 b coupled together with an adhesive layer, which is illustrated in FIG. 13 (S201); forming the first circuit pattern 15 a on the first carrier 12 a and the second circuit pattern 15 b on the second carrier 12 b through electroplating, which is illustrated in FIG. 14 (S202); and separating the first carrier 12 a and the second carrier 12 b (S203).
  • After that, as illustrated in FIGS. 31 and 32, the first insulator 30 a and the second insulator 30 b can be compressed against each other such that the first electronic component 20 a and the second electronic component 20 b face each other (S270). When compressing the first insulator 30 a and the second insulator 30 b by using heat and pressure, the first insulator 30 a and the second insulator 30 b can become one insulator 30 (FIG. 32), and thus the first electronic component 20 a and the second electronic component 20 b can be embedded in the insulator 30.
  • Furthermore, the first electronic component 20 a can be flip-chip bonded with the first circuit pattern 15 a, and the second electronic component 20 b can be flip-chip bonded with the second circuit pattern 15 b.
  • As illustrated in FIG. 33, the first carrier 12 a and the second carrier 12 b can be removed (S280). As illustrated in FIG. 34, an insulation layer 36 can be stacked on both sides of the insulator 30, and a circuit pattern can be formed on each insulation layer 36, so that an electronic component embedded circuit board having a 4 layered structure can be manufactured.
  • On the other hand, when manufacturing a two layered electronic component embedded circuit board, a solder resist can be formed on a surface of the insulator 30 having the first circuit pattern 15 a and the second circuit pattern 15 b embedded therein, without stacking the insulation layer 36.
  • In order to remove the carriers 12 a and 12 b, the method of chemical etching can be used. As described above, when the seed layers 13 a and 13 b, which are made of a different material from that of the carriers 12 a and 12 b, are formed on surfaces of the carriers 12 a and 12 b, the circuit patterns 15 a and 15 b can be protected by dividing the etching process.
  • Below, a second disclosed embodiment of an electronic component embedded printed circuit board will be described in accordance with another aspect of the present invention.
  • FIG. 35 is a cross sectional view illustrating a second embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention. Illustrated in FIG. 35 are circuit patterns 15 a, 15 b, 15 c and 15 d, a via 16 and 17, electronic components 20 a and 20 b, a solder bump 21, insulators 30 and 36 and a solder resist 34.
  • In this embodiment, an electronic component embedded printed circuit board can have two electronic components 20 a and 20 b embedded in one insulator 30, in which one of the electronic components can be flip-chip bonded with a circuit pattern 15 a and the other one can be connected through a via 17. In addition, the electronic components 20 a and 20 b can be adhered by using an adhesive part 38.
  • In comparison with the previously described embodiment, in which the two electronic components 20 a and 20 b embedded in the insulator 30 are all flip-chip bonded with the circuit patterns 15 a and 15 b, the present embodiment presents that only one 20 a of the two electronic components 20 a and 20 b is flip-chip bonded and the other one 20 b is connected with the circuit pattern through the via 17.
  • Through such a structure, an electronic component embedded printed circuit board having higher density than that of the related art can be implemented.
  • Except the difference described above, the present embodiment has the structure of an electronic component embedded circuit board described above, so that redundant explanations are omitted.
  • Below, a method of manufacturing an electronic component embedded printed circuit board having the structure will be described.
  • FIG. 36 is a flowchart illustrating a second disclosed embodiment of an electronic component embedded printed circuit board in accordance with another aspect of the present invention. FIGS. 37 to 39 are flowcharts illustrating a method of manufacturing an electronic component embedded printed circuit board illustrated in FIG. 36. Illustrated in FIGS. 37 to 39 are circuit patterns 15 a, 15 b, 15 c and 15 d, a via 16 and 17, electronic components 20 a and 20 b, a solder bump 21, insulators 30 and 36, and a solder resist 34. First of all, a first carrier 12 a having a first circuit pattern 15 a formed on one surface thereof is prepared (S310), and a first electronic component 20 a can be flip-chip bonded to the first circuit pattern 15 a (S320).
  • Likewise, a second electronic component 20 b can be adhered to the first electronic component 20 a by using an adhesive part 38 (S330). Here, an epoxy type adhesive or a film type adhesive can be used as the adhesive part 38.
  • After adhering the second electronic component 20 b to the first electronic component 20 a, one side of an insulator 30 can be stacked on the first carrier 12 a to cover the first electronic component 20 a and the second electronic component 20 b (S340). As illustrated in FIG. 37, the first electronic component 20 a and the second electronic component 20 b are covered in the insulator 30 through such a process.
  • Then, a via 17 and a second circuit pattern 15 b can be formed on another side of the insulator 30, in which the via is connected with the second electronic component and the second circuit pattern is electrically connected with the via (S350). For forming the via 17, as illustrated in FIG. 38, a via hole can be formed in the insulator by using a layer drill, and then a conductive material can be filled inside the via hole by way of electroless plating and electroplating. As such, the second circuit pattern 15 b can be simultaneously formed on the insulator through the via forming process by using electroless plating or electroplating.
  • Then, the first carrier 12 a can be removed (S360), and thus an electronic component embedded printed circuit board can be manufactured by forming a solder resist at an outermost layer.
  • As illustrated in FIG. 35, when implementing a multi-layered structure, an additional insulator 36 can be respectively stacked on each side of the insulator 30, and then each of circuit patterns 15 c and 15 d can be formed on each insulator 36.
  • According to certain embodiments of the invention as set forth above, the degree of conformation for an electrical component can be improved by embedding the electrical component using a flip-chip bonding method, and the yield can improved by simplifying the production process.
  • While the spirit of the invention has been described in detail with reference to particular embodiments, the embodiments are for illustrative purposes only and do not limit the invention. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the invention. As such, many embodiments other than those set forth above can be found in the appended claims.

Claims (8)

1. An electronic component embedded printed circuit board comprising:
an insulator;
a first circuit pattern buried in one side of the insulator;
an electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern; and
a second circuit pattern buried in an other side of the insulator.
2. The electronic component embedded printed circuit board of claim 1, wherein the electronic component is flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
3-6. (canceled)
7. An electronic component embedded printed circuit board comprising:
an insulator;
a first circuit pattern buried in one side of the insulator;
a first electronic component embedded in the insulator and flip-chip bonded with the first circuit pattern;
a second circuit pattern buried in an other side of the insulator; and
a second electronic component embedded in the insulator and connected with the second circuit pattern.
8. The electronic component embedded printed circuit board of claim 7, wherein the first electronic component is flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.
9. The electronic component embedded printed circuit board of claim 7, wherein the second electronic component is flip-chip bonded with the second circuit pattern.
10. The electronic component embedded printed circuit board of claim 7, further comprising an adhesive part interposed between the first electronic component and the second electronic component, the adhesive part being made of a different material from that of the insulator.
11-17. (canceled)
US13/364,104 2008-07-21 2012-02-01 Method of manufacturing electronic component embedded circuit board Abandoned US20120134125A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/364,104 US20120134125A1 (en) 2008-07-21 2012-02-01 Method of manufacturing electronic component embedded circuit board

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020080070662A KR100997199B1 (en) 2008-07-21 2008-07-21 Manufacturing method of printed circuit board having electro component
KR10-2008-0070662 2008-07-21
US12/359,416 US8201324B2 (en) 2008-07-21 2009-01-26 Method of manufacturing electronic component embedded circuit board
US13/364,104 US20120134125A1 (en) 2008-07-21 2012-02-01 Method of manufacturing electronic component embedded circuit board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/359,416 Division US8201324B2 (en) 2008-07-21 2009-01-26 Method of manufacturing electronic component embedded circuit board

Publications (1)

Publication Number Publication Date
US20120134125A1 true US20120134125A1 (en) 2012-05-31

Family

ID=41529281

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/359,416 Expired - Fee Related US8201324B2 (en) 2008-07-21 2009-01-26 Method of manufacturing electronic component embedded circuit board
US13/364,104 Abandoned US20120134125A1 (en) 2008-07-21 2012-02-01 Method of manufacturing electronic component embedded circuit board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/359,416 Expired - Fee Related US8201324B2 (en) 2008-07-21 2009-01-26 Method of manufacturing electronic component embedded circuit board

Country Status (3)

Country Link
US (2) US8201324B2 (en)
KR (1) KR100997199B1 (en)
TW (1) TWI401001B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160066428A1 (en) * 2013-05-14 2016-03-03 Murata Manufacturing Co., Ltd. Component-embedded substrate and communication module

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110037332A (en) * 2009-10-06 2011-04-13 삼성전기주식회사 A printed circuit board and a method of manufacturing the same
KR101102789B1 (en) * 2010-10-07 2012-01-05 대덕전자 주식회사 Method of electroplating the hole for the semi-additive process with a heterogeneous metal seed layer
KR101167802B1 (en) * 2010-12-27 2012-07-25 삼성전기주식회사 circuit board and method for manufacturing the same
EP2506330A1 (en) 2011-04-01 2012-10-03 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Apparatus and method for providing an embedded structure and for providing an electro-optical device including the same
CN102800598B (en) * 2011-05-24 2015-08-19 成都锐华光电技术有限责任公司 The substrate of embedding active element and embedding method
KR101874992B1 (en) * 2011-12-30 2018-07-06 삼성전기주식회사 A printed circuit board comprising embeded electronic component within and a method for manufacturing the same
KR101302380B1 (en) * 2012-01-30 2013-09-06 주식회사 심텍 Thin PCB substrate and method of manufacturing the same
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (en) 2012-08-03 2019-04-18 삼성전자주식회사 Methods of manufacturing semiconductor packages
CN102905478B (en) * 2012-11-14 2016-12-28 江苏普诺威电子股份有限公司 Components and parts technique is buried in multilayer board
TWI552290B (en) * 2014-04-22 2016-10-01 矽品精密工業股份有限公司 Package substrate and manufacturing method thereof
JP2016076656A (en) * 2014-10-08 2016-05-12 イビデン株式会社 Electronic component built-in wiring board and method of manufacturing the same
CN105810659A (en) * 2014-12-30 2016-07-27 恒劲科技股份有限公司 Packaging device and manufacturing method thereof
KR102356810B1 (en) * 2015-01-22 2022-01-28 삼성전기주식회사 Printed circuit board having embedded electronic devices and method of manufacturing the same
KR101696894B1 (en) * 2015-02-03 2017-01-17 주식회사 심텍 embedded PCB and method of manufacturing the same
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
JP2020038943A (en) * 2018-09-05 2020-03-12 株式会社東芝 Semiconductor device and manufacturing method of the same
US10462937B1 (en) 2019-04-11 2019-10-29 Borgwarner, Inc. PCB design for electrically-actuated turbochargers
CN111867248A (en) * 2019-04-24 2020-10-30 宏启胜精密电子(秦皇岛)有限公司 Circuit board and manufacturing method thereof
CN112312656B (en) * 2019-07-30 2022-09-20 宏启胜精密电子(秦皇岛)有限公司 Embedded circuit board and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091593B2 (en) * 2003-07-09 2006-08-15 Matsushita Electric Industrial Co., Ltd. Circuit board with built-in electronic component and method for manufacturing the same
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
US7888174B2 (en) * 2006-06-20 2011-02-15 Unimicron Technology Corp. Embedded chip package process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081423A (en) * 2001-10-26 2007-03-29 Matsushita Electric Works Ltd Wiring board sheet and manufacturing method thereof, multilayer board and manufacturing method thereof
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
JP5022552B2 (en) * 2002-09-26 2012-09-12 セイコーエプソン株式会社 Electro-optical device manufacturing method and electro-optical device
TWI282160B (en) 2004-07-09 2007-06-01 Phoenix Prec Technology Corp Circuit board structure integrated with chip and method for fabricating the same
US7351608B1 (en) * 2004-08-19 2008-04-01 The United States Of America As Represented By The Director Of The National Security Agency Method of precisely aligning components in flexible integrated circuit module
KR100733251B1 (en) * 2005-09-29 2007-06-27 삼성전기주식회사 Double electronic components embedded PCB and manufacturing method thereof
KR100704911B1 (en) * 2005-12-26 2007-04-09 삼성전기주식회사 Electronic chip embedded pcb and method of the same
KR100782407B1 (en) 2006-10-30 2007-12-05 삼성전기주식회사 Method for manufacturing circuit board
KR100816324B1 (en) * 2007-05-23 2008-03-24 전자부품연구원 Chip embedded print circuit board and fabricating method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091593B2 (en) * 2003-07-09 2006-08-15 Matsushita Electric Industrial Co., Ltd. Circuit board with built-in electronic component and method for manufacturing the same
US7888174B2 (en) * 2006-06-20 2011-02-15 Unimicron Technology Corp. Embedded chip package process
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160066428A1 (en) * 2013-05-14 2016-03-03 Murata Manufacturing Co., Ltd. Component-embedded substrate and communication module
US9629249B2 (en) * 2013-05-14 2017-04-18 Murata Manufacturing Co., Ltd. Component-embedded substrate and communication module

Also Published As

Publication number Publication date
US20100012364A1 (en) 2010-01-21
TW201008410A (en) 2010-02-16
TWI401001B (en) 2013-07-01
KR100997199B1 (en) 2010-11-29
KR20100009849A (en) 2010-01-29
US8201324B2 (en) 2012-06-19

Similar Documents

Publication Publication Date Title
US8201324B2 (en) Method of manufacturing electronic component embedded circuit board
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US7939935B2 (en) Electronic device substrate, electronic device and methods for fabricating the same
KR100537972B1 (en) Chip scale ball grid array for integrated circuit package
US7514770B2 (en) Stack structure of carrier board embedded with semiconductor components and method for fabricating the same
US9947625B2 (en) Wiring board with embedded component and integrated stiffener and method of making the same
US7768119B2 (en) Carrier structure embedded with semiconductor chip
KR100851072B1 (en) Electronic package and manufacturing method thereof
US9536781B2 (en) Method of making integrated circuit
US20050247665A1 (en) Method of manufacturing an electronic parts packaging structure
US8169072B2 (en) Semiconductor device, manufacturing method thereof, and electronic device
US9209146B2 (en) Electronic device packages having bumps and methods of manufacturing the same
JP5942823B2 (en) Electronic component device manufacturing method, electronic component device, and electronic device
US7678681B2 (en) Electronic component built-in substrate and method of manufacturing the same
JP5357239B2 (en) WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
US20080099903A1 (en) Stacked chip package, embedded chip package and fabricating method thereof
US9875930B2 (en) Method of packaging a circuit
JP5128180B2 (en) Chip built-in substrate
KR101043328B1 (en) Electro device embedded printed circuit board and manufacturing method thereof
KR101167429B1 (en) Method for manufacturing the semiconductor package
US20100065959A1 (en) Semiconductor package and method of manufacturing the same, and semiconductor device
US20110186997A1 (en) Board on chip package substrate and manufacturing method thereof
CN108305864B (en) Terminal with a terminal body
US8556159B2 (en) Embedded electronic component
KR100997790B1 (en) Substrate for semiconductor package and method for fabricating the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION