TWI552290B - Package substrate and manufacturing method thereof - Google Patents

Description

Package substrate and its preparation method

The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate having electronic components and a method of fabricating the same.

As shown in FIG. 1 , a conventional packaged substrate of a molded interconnect system (MIS) connects a plurality of first conductive portions 11 to a plurality of metal pillars 12, and connects the plurality of metal pillars 12 to a plurality of The second conductive portion 13 is further covered with the first conductive portion 11 and the metal pillar 12 by the package 14; however, when the aspect ratio of the metal pillar 12 is too large, the effect of plating the metal pillar 12 is not good, but nowadays The specification of the height of the capacitor is usually 110 μm or more. Therefore, if a capacitor is to be embedded in the package substrate, the height of the metal pillar 12 must be increased.

In order to increase the height of the metal post 12, the industry has improved. As shown in Fig. 2, the metal post 12 is divided into two sections of a first sub-metal post 121 and a second sub-metal post 122 and separately plated. However, the more the manufacturing steps, the more the manufacturing tolerances are accumulated. In order to maintain the original area of the second conductive portion 13, the range of the first sub-metal pillar 121 must be larger than the range of the second sub-metal pillar 122. The first sub-metal pillar 121 provides the second sub-gold The column 122 has a sufficient alignment margin; similarly, in order for the first conductive portion 11 to provide a sufficient alignment margin of the first sub-metal pillar 121, the range of the first conductive portion 11 must also be greater than the first The range of the sub-metal pillars 121 greatly increases the area of the first conductive portion 11, thereby limiting the available wiring space.

Since today's electronic products are pursuing a trend toward lighter, thinner and shorter, manufacturers are continually seeking ways to achieve high-density electronic components and high wiring density. Therefore, how to avoid various problems in the above-mentioned prior art is an urgent problem to be solved in the industry.

The present invention provides a package substrate, comprising: a package having opposite top and bottom surfaces; a plurality of conductive structures embedded in the package, and each of the conductive structures includes a first conductive portion embedded in the package and exposing the bottom surface; and a metal pillar, an alignment layer and a conductive blind hole sequentially formed on the first conductive portion, and one end of the conductive blind hole Exposing the top surface such that the vertical projection area of each of the alignment layers is larger than the vertical projection area of each of the metal pillars, and the vertical projection area of each of the alignment layers is greater than the vertical projection area of each of the conductive blind holes; The conductive portion is formed on the conductive blind via and the top surface; and the electronic component is embedded in the package.

The present invention provides a method for manufacturing a package substrate, comprising: forming a plurality of first conductive portions on a carrier plate; providing electronic components on the plurality of first conductive portions, and forming metal posts on each of the first conductive portions; Forming an alignment layer on the end faces of the metal pillars so that the vertical projection area of each of the alignment layers a vertical projection area larger than each of the metal pillars; forming a package on the carrier plate to cover the first conductive portion, the metal pillar, the electronic component and the alignment layer, the package having a bottom surface connecting the carrier board and a conductive top hole is formed in the package body on each of the alignment layers to form a plurality of conductive structures by the first conductive portion, the metal pillar, the alignment layer and the conductive blind via, wherein Forming a second conductive portion on the top surface of the package and each of the conductive blind holes, and a vertical projected area of each of the alignment layers is larger than a vertical projected area of each of the conductive blind holes; and removing the carrier plate to expose the first a conductive portion.

As can be seen from the above, the present invention is characterized in that an alignment layer is disposed between the metal pillar and the conductive blind hole, and the vertical projection area of the alignment layer to each of the first conductive portions is larger than the vertical projection area of the metal pillar to each of the first conductive portions. And the vertical projection area of the alignment layer to each of the first conductive portions is greater than the vertical projection area of the conductive vias to each of the first conductive portions, so the alignment layer can provide sufficient alignment of the conductive blind holes A margin is required, and the range of the metal post and the first conductive portion can be reduced or the original range of the metal post and the first conductive portion can be maintained, thereby increasing the wiring density and the mounting density of the electronic component; The placement of the amine layer facilitates the formation of blind holes and increases the adhesion to the second conductive portion to improve overall yield.

11, 32‧‧‧ First Conductive Department

12, 34‧‧‧ metal column

121‧‧‧First child metal column

122‧‧‧Second sub-metal column

13, 40b, 47‧‧‧Second Conductive Department

14, 37‧‧‧ package

30‧‧‧Loading board

31‧‧‧First barrier layer

310‧‧‧First opening

32a‧‧‧ first surface

32b‧‧‧ second surface

33‧‧‧second barrier layer

330‧‧‧Second opening

35‧‧‧ alignment layer

36‧‧‧Electronic components

37a‧‧‧ third surface

37b‧‧‧Fourth surface

370, 450‧‧ ‧ blind holes

38‧‧‧ Conductive layer

39‧‧‧ third resistive layer

390‧‧‧ third opening

40a, 46‧‧‧ conductive blind holes

41‧‧‧Insulating protective layer

410‧‧‧Insulating protective layer opening

42‧‧‧ fourth resistive layer

43‧‧‧ fifth resistive layer

430‧‧‧ openings

44‧‧‧Surface treatment layer

45‧‧‧ dielectric materials

1 is a cross-sectional view of a package substrate of a conventional molded internal connection type system; and FIG. 2 is a cross-sectional view of another conventional packaged internal connection type system; FIG. 3A to 3N The present invention is the method for manufacturing the package substrate of the present invention. A cross-sectional view of an embodiment; and a cross-sectional view of a second embodiment of the method of fabricating the package substrate of the present invention, as shown in FIGS. 4A to 4D.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terminology used in the present specification is only for the purpose of illustration, and is not intended to limit the scope of the invention. The change or adjustment of the relative relationship is also considered as The scope of the invention can be implemented.

First embodiment

3A to 3N are cross-sectional views showing a first embodiment of the method of fabricating the package substrate of the present invention.

As shown in FIG. 3A, a first resist layer 31 having a first opening 310 is formed on a top surface of a carrier plate 30, and an opposite first surface 32a and a second surface are formed in the first opening 310. The first conductive portion 32 of the surface 32b connects the first conductive portion 32 to the carrier plate 30 with its first surface 32a. The carrier plate 30 can be a steel plate.

As shown in FIG. 3B, a second resist layer 33 having a second opening 330 is formed on the first resist layer 31 and the first conductive portion 32, and the first conductive portion is in the second opening 330. A metal post 34 is formed on the second surface 32b of the 32.

As shown in FIG. 3C, an alignment layer 35 of an arbitrary pattern is formed on the end surface of the metal pillar 34 and the second resist layer 33, and the vertical projection area of the alignment layer 35 for each of the first conductive portions 32 is formed. It is larger than the vertical projected area of the metal pillars 34 to the first conductive portions 32.

As shown in FIG. 3D, the first resistive layer 31 and the second resistive layer 33 are removed, and the electronic component 36 is disposed on the second surface 32b of the first conductive portion 32. The electronic component 36 is a laminated ceramic capacitor. (Multi-layer Ceramic Capacitor, MLCC for short).

As shown in FIG. 3E, a package body 37 is formed on the top surface of the carrier plate 30 to cover the first conductive portion 32, the metal pillars 34, the electronic component 36 and the alignment layer 35, and the package body 37 has a connection. The third surface 37a of the carrier plate 30 (i.e., the bottom surface of the package body 37) and the fourth surface 37b opposite thereto (i.e., the top surface of the package body 37).

As shown in FIG. 3F, a portion of the package body 37 is removed to form a blind via 370 that exposes the alignment layer 35. The blind via 370 is formed by laser cauterization or mechanical drilling.

As shown in FIG. 3G, a conductive layer 38 is formed on the package 37 and the alignment layer 35.

As shown in FIG. 3H, a third opening is formed on the conductive layer 38. The third resistive layer 39 of 390.

As shown in FIG. 3I, the conductive layer 38 performs a plating step of, for example, copper plating for the current path, and further forms a conductive via hole 40a in the blind via 370 on the alignment layer 35 to be formed by each of the first conductive portions. 32, the metal pillar 34, the alignment layer 35 and the conductive blind hole 40a constitute a plurality of conductive structures (not labeled with the component symbol), and the second conductive portion 40b is formed on the fourth surface 37b and the conductive blind via 40a, so that the first The two conductive portions 40b are electrically connected to the first conductive portion 32, such that the vertical projected area of the alignment layer 35 to each of the first conductive portions 32 is larger than the vertical projected area of the conductive blind vias 40a to the first conductive portions 32. The aligning layer 35 is located between the metal post 34 and the conductive blind hole 40a. The conductive blind hole 40a and the second conductive portion 40b are integrally formed, but not limited thereto.

As shown in FIG. 3J, the third resist layer 39 and the conductive layer 38 it covers are removed.

As shown in FIG. 3K, an insulating protective layer 41 is formed on the second conductive portion 40b and the fourth surface 37b, and the insulating protective layer 41 has a plurality of insulating protective layer openings 410 of the exposed portion of the second conductive portion 40b.

As shown in FIG. 3L, a fourth resist layer 42 is formed on the insulating protective layer 41, the second conductive portion 40b and the fourth surface 37b, and an opening 430 having the bottom surface is formed on the bottom surface of the carrier plate 30. The fifth resist layer 43.

As shown in FIG. 3M, the carrier plate 30 in the opening 430 is removed, and the first conductive portion 32 of a portion of the thickness is removed as needed, and the fourth resist layer 42 and the fifth resist layer 43 are removed. It should be particularly noted that the present invention can also completely remove the carrier plate 30 as needed (this is not shown).

As shown in FIG. 3N, a surface treatment layer 44 is formed on the exposed surface of the first conductive portion 32 and the second conductive portion 40b, and the surface treatment layer 44 is made of nickel/gold (Ni/Au) and nickel. /Palladium/Gold (Ni/Pd/Au) or Organic Soldering Agent (OSP).

The package substrate comprises: a package body 37 having opposite top and bottom surfaces; a plurality of conductive structures embedded in the package body 37, and each of the conductive structures includes: a first conductive portion 32, Embedded in the package body 37 and exposing the bottom surface; and the metal pillar 34, the alignment layer 35 and the conductive blind hole 40a sequentially formed on the first conductive portion 32, one end of the conductive blind hole 40a The top surface is exposed, so that the vertical projection area of each of the alignment layers 35 for each of the first conductive portions 32 is larger than the vertical projection area of each of the metal pillars 34 for each of the first conductive portions 32, and each of the alignments is made. The vertical projection area of each of the first conductive portions 32 of the layer 35 is larger than the vertical projection area of each of the conductive blind holes 40a to the first conductive portions 32; and the second conductive portion 40b is formed on the conductive blind vias 40a and The top surface is exposed on the top surface; and the electronic component 36 is embedded in the package body 37.

In the package substrate, the insulating protective layer 41 is formed on the second conductive portion 40b and the fourth surface 37b, and has a plurality of insulating protective layer openings 410 of the exposed portion of the second conductive portion 40b.

In the package substrate of the embodiment, a surface treatment layer 44 is formed on the exposed surface of the first conductive portion 32 and the second conductive portion 40b, and the electronic component 36 is a multilayer ceramic capacitor (Multi-layer). Ceramic Capacitor, referred to as MLCC).

Second embodiment

4A to 4D are cross-sectional views showing a second embodiment of the method of fabricating the package substrate of the present invention.

This embodiment is substantially similar to the previous embodiment, and the main differences are described below.

As shown in FIG. 4A, which continues from FIG. 3E, the package 37 is ground to embed and align the alignment layer 35 to the fourth surface 37b.

As shown in FIG. 4B, a dielectric material 45 is formed on the fourth surface 37b and the alignment layer 35. The material of the dielectric material 45 may be a polyimide or a molding compound.

As shown in FIG. 4C, a portion of the dielectric material 45 is removed to form a blind via 450 of the exposed portion of the alignment layer 35.

As shown in FIG. 4D, a conductive via hole 46 is formed in the blind via 450 on the alignment layer 35, and a second conductive portion 47 is formed on the dielectric material 45 and the conductive via hole 46 to make the second The conductive portion 47 is electrically connected to the first conductive portion 32 such that the vertical projected area of the alignment layer 35 to each of the first conductive portions 32 is greater than the vertical projected area of the conductive blind vias 46 for each of the first conductive portions 32. The alignment layer 35 is located between the metal pillars 34 and the conductive blind vias 46. The carrier layer 30 is removed and the insulating protective layer 41 and the surface treatment layer 44 are formed as in the previous embodiment.

Another package substrate is similar to the package substrate of the previous embodiment, but the package includes an encapsulation layer (package 37) and a dielectric material formed on the encapsulation layer and the alignment layer 35. 45. The material of the dielectric material 45 may be a polyimide or a molding compound, wherein the encapsulation layer (the package 37) covers the first conductive portion 32 and the metal. The pillar 34, the electronic component 36 and the alignment layer 35 are covered by the dielectric material 45.

In summary, compared with the prior art, the present invention is characterized in that an alignment layer is disposed between the metal pillar and the conductive blind hole, and the vertical projection area of the alignment layer to each of the first conductive portions is greater than that of the metal pillar pair. a vertical projected area of the first conductive portion, and a vertical projected area of the alignment layer to each of the first conductive portions is greater than a vertical projected area of the conductive vias for each of the first conductive portions, so the alignment layer can provide The conductive blind hole has a sufficient margin for alignment, and can narrow the range of the metal pillar and the first conductive portion or maintain the original range of the metal pillar and the first conductive portion, thereby improving the wiring density and the electronic component. The density of the set; in addition, the arrangement of the polyimide layer contributes to the formation of blind holes and increases the adhesion to the second conductive portion to improve the overall yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

30‧‧‧Loading board

32‧‧‧First Conductive Department

34‧‧‧Metal column

35‧‧‧ alignment layer

36‧‧‧Electronic components

37‧‧‧Package

38‧‧‧ Conductive layer

40a‧‧‧conductive blind hole

40b‧‧‧Second Conductive Department

41‧‧‧Insulating protective layer

Claims (14)

A package substrate includes: a package having opposite top and bottom surfaces; a plurality of conductive structures embedded in the package, and each of the conductive structures includes: a first conductive portion embedded in the package And exposing the bottom surface; and the metal pillar, the alignment layer and the conductive blind hole formed on the first conductive portion, the one end of the conductive blind hole is exposed outside the top surface, and the alignment layer is arranged The vertical projection area is larger than the vertical projection area of each of the metal pillars, and the vertical projection area of each of the alignment layers is larger than the vertical projection area of each of the conductive blind holes; the second conductive portion is formed on the conductive blind hole and the top And the electronic component is embedded in the package. The package substrate according to claim 1, further comprising an insulating protective layer formed on the top surface of the second conductive portion and the package, and having a plurality of exposed portions of the insulating portion of the second conductive portion Open the hole. The package substrate according to claim 1, further comprising a surface treatment layer formed on the exposed surface of the first conductive portion and the second conductive portion. The package substrate according to claim 1, wherein the electronic component is a laminated ceramic capacitor. The package substrate of claim 1, wherein the package comprises an encapsulation layer and a dielectric material formed on the encapsulation layer and the alignment layer, wherein the encapsulation layer encapsulates the first conductive portion And a metal pillar, an electronic component and an alignment layer, the dielectric material covering the conductive blind hole. The package substrate according to claim 1, wherein the conductive blind hole and the second conductive portion are integrally formed. A method for manufacturing a package substrate, comprising: forming a plurality of first conductive portions on a carrier plate; providing electronic components on the plurality of first conductive portions, and forming metal pillars on each of the first conductive portions; Forming an alignment layer on the end surface of the column, so that a vertical projection area of each of the alignment layers is larger than a vertical projection area of each of the metal pillars; a package body is formed on the carrier plate to cover the first conductive portion, the metal pillar, An electronic component and an alignment layer, the package has a bottom surface connected to the carrier and a top surface opposite thereto; and a conductive blind hole is formed in the package on each of the alignment layers to be formed by each of the first conductive portions and the metal The pillar, the alignment layer and the conductive blind via form a plurality of conductive structures, wherein a second conductive portion is formed on the top surface of the package and each of the conductive blind vias, and a vertical projected area of each of the alignment layers is greater than each a vertical projection area of the conductive blind hole; and removing the carrier plate to expose the first conductive portion. The method of manufacturing a package substrate according to claim 7, wherein the conductive blind hole and the second conductive portion are integrally formed. The method for manufacturing a package substrate according to claim 7 of the patent application, wherein A plurality of blind holes are formed in the package by laser cauterization or mechanical drilling to form the conductive blind holes in each of the blind holes. The method for manufacturing a package substrate according to claim 7 , after forming the second conductive portion, forming an insulating protective layer on the second conductive portion and the top surface, and the insulating protective layer has a plurality of exposed portions The insulating protective layer of the second conductive portion is opened. The method for manufacturing a package substrate according to claim 7, wherein after forming the second conductive portion, a surface treatment layer is formed on the exposed surfaces of the first conductive portion and the second conductive portion. The method of manufacturing a package substrate according to claim 7, wherein the electronic component is a laminated ceramic capacitor. The method of manufacturing a package substrate according to claim 7, wherein the package comprises an encapsulation layer formed on the carrier board and a dielectric material formed on the encapsulation layer and the alignment layer, wherein The encapsulation layer encapsulates the first conductive portion, the metal pillar, the electronic component and the alignment layer, and the dielectric material covers the conductive via hole. The method for manufacturing a package substrate according to claim 13 , wherein the step of forming the package comprises forming the package layer; grinding the package layer to embed and align the alignment layer with the package layer; And forming the dielectric material on the encapsulation layer and the alignment layer.