CN102800598B - The substrate of embedding active element and embedding method - Google Patents
The substrate of embedding active element and embedding method Download PDFInfo
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- CN102800598B CN102800598B CN201110135359.6A CN201110135359A CN102800598B CN 102800598 B CN102800598 B CN 102800598B CN 201110135359 A CN201110135359 A CN 201110135359A CN 102800598 B CN102800598 B CN 102800598B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of method of embedding active element in a substrate.The method comprises: on the conductive layer of the first loading plate, form the first internal layer circuit figure; Active element is connected to the first internal layer circuit figure on the first loading plate; The correspondence position processing hole of active element on dielectric-slab, the length in hole and width are equal to or are greater than length and the width of active element; By the second loading plate, with cuniculate dielectric-slab and the first loading plate aligned stack successively with active element, form active element and imbed module, the active element on the first loading plate is positioned at the inside that active element imbeds module, inserts the hole on dielectric-slab; Active element is imbedded module and carry out hot pressing, form the substrate of embedding active element, the temperature of hot pressing is more than or equal to the glass transition temperature of dielectric-slab.The present invention has that processing step is simple, productivity ratio is high, cost is low and can carry out the advantage such as reprocessing.
Description
Technical field
The present invention relates to microelectronic industry encapsulation technology field, particularly relate to a kind of substrate and embedding method of embedding active element.
Background technology
With increase rapidly that is compact, high-performance portable electronic equipment, electronic devices and components are imbedded so-called rear surface attachment (post-SMT) the technology first meeting clue of substrate inside.At present, although be based on passive components such as embedding resistance, inductance, electric capacity, in recent years, by active elements such as chips, the ultimate three-dimensional packaging technology of substrate inside is all embedded in also among rapid progression together with passive component.With Intel Company deliver without salient point lamination multilayer (Bumpless Build-Up Layer, BBUL) for the multilayer printed wiring board imbedding active element of representative comes out, the beginning that active element realizes system integration encapsulation can be imbedded at last in a substrate.
Because the inside composition of active element comes more complex with structure compared with passive component, therefore embedding active element is much more difficult compared with embedding passive component.By the sequencing of embedding active element, " elder generation " embedding active element can be divided into, " centre " embedding active element and " finally " embedding active element.
Intel Company deliver without salient point lamination multilayer technique be " elder generation " embedding active element one typical case, the patent that current most active element is imbedded all concentrates on this part, this is similar to the theory of wafer-level packaging " fan-out " (Fan-Out), substantially be all the connection first realizing active element in a supporting bracket, then insulating barrier is added, after " lamination ", the holding wire of active element is connected to outside above again, what realize active element imbeds process.United States Patent (USP) NO.2010/0012364A1 relates to a kind of electronic component and is embedded to method in substrate, and as shown in Figure 1, base main body mainly comprises supporting layer 36, insulating barrier 30 and electronic component 20.Here electronic component 20 adopts face-down bonding technique to be connected on the circuitous pattern 15a of the first supporting layer 36, then adds a layer insulating 20, finally presses one deck again with the supporting layer 36 of circuitous pattern 15b above, achieves electronic component 20 in a substrate embedding.
" centre " embedding active element after referring to, on the substrate of part " lamination ", active element being installed again " lamination " connect realize active element imbed process, the patent of this respect also has a lot, but the method adopted is substantially consistent with the method for " elder generation " embedding active element.
" elder generation " embedding active element and these two kinds of methods of " centre " embedding active element all also exist some shortcomings.First, a series of embedding technique due to active element is connected processing with relevant " lamination " to waste time and energy very much, must cause low production efficiency and high cost; Secondly, due to the laminating technology adopting repeatedly " lamination " of high pressure to connect embedding active element, breaking of embedding active element is easily caused; Again, in common embedding encapsulating structure, out of order active element is difficult to reprocess, and therefore necessarily requires the more high performance good chip of higher level; Finally, in the technical process of the pressurized, heated between the embedding active element connected and baseplate material interface, owing to there is heat coupling, easily there is the connection fault of junction in namely different thermal coefficient of expansions and the thermal stress issues brought.The problem adopting the method for " finally " embedding active element can solve above-described " elder generation " embedding active element to bring with " centre " embedding active element, traditional " finally " embedding active element completes " lamination " at substrate and connects later just embedding active element, but this method technique is too complicated, more consuming time.
Realizing in process of the present invention, applicant recognizes that the method for prior art embedding active element in a substrate exists following technological deficiency: owing to needing a series of embedding technique and relevant lamination Connection Step, its production efficiency is low, and cost is high.
Summary of the invention
(1) technical problem that will solve
For addressing the aforementioned drawbacks, the invention provides a kind of substrate and embedding method of embedding active element, to enhance productivity, reducing costs.
(2) technical scheme
According to an aspect of the present invention, a kind of method of embedding active element is in a substrate provided.The method comprises: on the conductive layer of the first loading plate, form the first internal layer circuit figure; Active element is connected to the first internal layer circuit figure on the first loading plate; The correspondence position processing hole of active element on dielectric-slab, the length in hole and width are equal to or are greater than length and the width of active element; By the second loading plate, with cuniculate dielectric-slab and the first loading plate aligned stack successively with active element, form active element and imbed module, the active element on the first loading plate is positioned at the inside that active element imbeds module, inserts the hole on dielectric-slab; Active element is imbedded module and carry out hot pressing, form the substrate of embedding active element, the temperature of hot pressing is more than or equal to the glass transition temperature of dielectric-slab.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, dielectric-slab is one or more layers, and the gross thickness of one or more layers dielectric-slab is greater than the thickness of active element.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, dielectric-slab adopts the one in following material to prepare: polyimides, polypropylene, liquid crystal polymer, span come vinegar imines-cyanate resin, epoxy resin, polytetrafluoroethylene or phenylpropyl alcohol cyclobutane.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, on dielectric-slab, the correspondence position of active element is processed in the step in hole, and the mode of processing is the one in following methods: photoetching process, plasma etching method or laser processing method.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, for the active element with salient point, step active element being connected to the first internal layer circuit figure of the first loading plate comprises: use Flip chip machine to be held in the passive face of active element; According to the bonding parameter preset, by the first internal layer circuit figure of active surface back bonding to the first loading plate of active element.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, also comprise after the step of the first internal layer circuit figure of active surface back bonding to the first loading plate of active element: fill underfill in the joint portion of active element and the first loading plate, carry out reflow soldering; Or also comprise before the step of the first internal layer circuit figure of active surface back bonding to the first loading plate of active element: on the first loading plate, cover connecting material, this connecting material is anisotropic conducting film or anisotropy conductiving glue, does not at this moment need underfill.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, also comprise after the active surface of active element being connected to the step of the first internal layer circuit figure of the first loading plate: Adhesion Interface heat sink material or add metal fin on passive of active element; Or active element is imbedded module carry out hot pressing, also comprise after forming the step of the substrate of embedding active element: on substrate, arrange louvre, this louvre is used for the heat radiation of embedding active element in it.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, interface heat sink material is adopt electrostatic spinning technique polyurethane to be prepared into the nanofiber substrate of interface heat sink material, and adds high hot nano particle on this basis and be prepared from.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, by the second loading plate, also comprise with before cuniculate dielectric-slab and the step that stacks gradually with the first loading plate of active element: on the conductive layer of the second loading plate, form the second internal layer circuit figure; By the second loading plate, with in cuniculate dielectric-slab and the step that stacks gradually with the first loading plate of active element: the second internal layer circuit figure on the second loading plate is imbedded inside module towards active element.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, also comprise after the first loading plate stacked gradually, dielectric-slab are carried out the step of hot pressing with the second loading plate: the opposite side conductive layer that the first internal layer circuit figure place conductive layer is relative on the first loading plate forms the first outer circuit figure; And/or the opposite side conductive layer that the second internal layer circuit figure place conductive layer is relative on the second loading plate forms the second outer circuit figure.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, by the second loading plate, also comprise with before cuniculate dielectric-slab and the step with the first loading plate aligned stack successively of active element: passive component is connected to the first internal layer circuit figure or the second internal layer circuit figure; The correspondence position processing hole of passive component on dielectric-slab, the length in hole and width are equal to or are greater than length and the width of passive component.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, also comprise after the first loading plate stacked gradually, dielectric-slab and the second loading plate are carried out the step of hot pressing: in the predeterminated position processing of multilager base plate perpendicular to the through hole of multilager base plate; Metallize to the through hole on multilager base plate, this through hole is used for the connection of active element and outer first circuitous pattern and outer second circuit figure.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, by the second loading plate, with cuniculate dielectric-slab and the first loading plate aligned stack successively with active element, formed after active element imbeds the step of module and comprise: stacking multiple active element imbeds module, each active element is imbedded module and is all imbedded default active element, every two active elements are imbedded between module has intermodule dielectric-slab, the material of this intermodule dielectric-slab can be identical with the material of dielectric-slab, also can adopt different materials; Active element is imbedded module and carry out hot pressing, the step forming the multilager base plate of embedding active element comprises: stacking multiple active elements are imbedded module and carries out hot pressing, forms the multilager base plate of embedding multiple active element.
Preferably, in the technical scheme of the present invention's embedding active element method in a substrate, stacking multiple active element is imbedded in the step of module: the active element that adjacent active element is imbedded in module can be arranged or back-to-back setting in opposite directions.
According to another aspect of the present invention, a kind of substrate of embedding active element is additionally provided.This substrate is comprised and being combined successively by hot pressing: the first loading plate, dielectric-slab and the second loading plate; On dielectric-slab, the correspondence position of active element arranges hole, and the length in hole and width are equal to or are greater than length and the width of active element; Active element is connected to the first internal layer circuit figure on the first loading plate, and inserts in the hole of dielectric-slab.
(3) beneficial effect
The present invention has following beneficial effect:
(1) method of the present invention's embedding active element in a substrate adopts new " finally " embedding active element form, namely disposable lamination " interlayer " imbeds the method for active element, has that processing step is simple, productivity ratio is high and can carry out the advantage such as reprocessing;
(2) in the present invention, active element or passive have adhered to floor height thermally-conductive interface heat sink material and/or a metal fin, or substrate arranges louvre, and therefore active element can efficiently radiates heat;
(3) the embedding substrate module of active element in the present invention, can also carry out " lamination " again and connect, and the three-dimensional realizing active element in encapsulation is carried, thus realizes the system in package of carrying whole passive component and active element in same encapsulation;
(4) method that adopts of whole technique can with planar semiconductor process compatible, finally realize integration and make.
Accompanying drawing explanation
Fig. 1 is the structural representation that prior art electronic component is embedded to substrate;
Fig. 2 is the flow chart of the embodiment of the present invention embedding active element method in a substrate;
Fig. 3 a is the schematic diagram of the embodiment of the present invention first bearing substrate;
Fig. 3 b is the schematic diagram after the embodiment of the present invention forms internal layer circuit on the first bearing substrate;
Fig. 3 c is the schematic diagram after the embodiment of the present invention connects active element on internal layer circuit;
Fig. 3 d is the schematic diagram of the embodiment of the present invention on active element after Adhesion Interface heat sink material;
Fig. 4 is the schematic diagram after the embodiment of the present invention forms internal layer circuit on the second bearing substrate;
Fig. 5 is the schematic diagram after the embodiment of the present invention processes hole on dielectric-slab;
Fig. 6 is the schematic diagram that the first loading plate, dielectric-slab, the second loading plate are aimed at by the embodiment of the present invention;
Fig. 7 is the schematic diagram of the multilager base plate after embodiment of the present invention hot pressing.
Fig. 8 through hole prepared by embodiment of the present invention multilager base plate after hot-pressing to go forward side by side the schematic diagram of row metal;
Fig. 9 is the schematic diagram that first loading plate of the embodiment of the present invention on multilager base plate and the second loading plate prepare outer circuit figure;
Figure 10 is the schematic diagram of the multilager base plate of the stacking many laminations of embodiment of the present invention sequential system;
Figure 11 is the schematic diagram of the multilager base plate of the stacking many laminations of the back-to-back mode of the embodiment of the present invention;
Figure 12 is the schematic diagram that the embodiment of the present invention is embedded with the multilager base plate of many laminations of active element and passive component.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.For ease of understanding, first element involved in the present invention is numbered:
[main element symbol description]
100-first loading plate; 102,112-layers of copper;
104-active element; 106-anisotropic conducting film;
200-second loading plate; 202,212-layers of copper;
300,302,304-dielectric-slab; 400-through hole;
502,504-passive component.
The present invention combines the form of " elder generation " embedding active element and " finally " embedding active element, disposable hot pressing " interlayer " is adopted to imbed the method for active element, active element is embedded in multilager base plate, achieve system in package plate, not only increase the reliability of systemic-function, make system more densification and microminaturization simultaneously, improve the performance of Signal transmissions, reduce production cost.
In a basic embodiment of the present invention, disclose a kind of method of embedding active element in a substrate.Fig. 2 is the flow chart of the embodiment of the present invention embedding active element method in a substrate.As shown in Figure 2, the method comprises:
Step S202, the conductive layer of the first loading plate is formed the first internal layer circuit figure;
Step S204, is connected to the first internal layer circuit figure on the first loading plate by active element;
Step S206, the correspondence position processing hole of active element on dielectric-slab, the length in hole and width are equal to or are greater than length and the width of active element;
Step S208, by the second loading plate, with cuniculate dielectric-slab and the first loading plate aligned stack successively with active element, form active element and imbed module, the active element on the first loading plate is positioned at the inside that active element imbeds module, inserts the hole on dielectric-slab;
Step S210, imbeds module and carries out hot pressing, form the substrate of embedding active element by active element, the temperature of this hot pressing is greater than the fusion temperature of dielectric-slab.
In the present embodiment, utilize the hole on dielectric-slab to hold active element, thus active element is encapsulated in the middle of substrate.The processing step of the method is simple, productivity ratio is high, just can carry out trouble shoot/reparation to active element before imbedding.Those of ordinary skill in the art should be appreciated that the ordinal relation of above-mentioned steps S206 and step S202/204 is adjustable.That is, can first on dielectric-slab active element correspondence position processing hole, then on the conductive layer of the first loading plate, form the first internal layer circuit figure, and active element be connected to the first internal layer circuit figure.
In order to further reduce costs and simplify production stage, above-mentioned dielectric-slab can be one or more layers, and the gross thickness of one or more layers dielectric-slab is greater than the thickness of active element.Polyimides, polypropylene, liquid crystal polymer, span are come vinegar imines-cyanate resin, epoxy resin, polytetrafluoroethylene or phenylpropyl alcohol cyclobutane etc. and are had stable chemical property, can working ability strong, its fusing point is between 150 DEG C to 200 DEG C.Therefore, dielectric-slab preferably adopts above-mentioned material.As long as and above-mentioned hot pressing temperature to equal or higher than 200 DEG C.
On dielectric-slab, the mode in the correspondence position processing hole of active element can be: photoetching process, plasma etching method or laser processing method." hole " of the embedding active element of employing laser processing is the method for the cave wall quality that can obtain best " hole " shape in current various processing " hole " and not have " lateral erosion ".In addition, the course of processing in " hole " of the embedding active element of laser processing is adopted to be quite simply accurate, both the deviation that the film negative film making not in photic method and " contraposition " thereof cause, the error etc. that metal mask makes and " contraposition " brings again not in plasma.The more important thing is that dielectric material that laser processing adopts has more selectivity widely, if any cover Copper Foil base material, do not cover Copper Foil base material, have the dielectric-slab of reinforcing material, the dielectric board material etc. that do not have the dielectric-slab of reinforcing material and " dry film " or " wet film " to be formed can carry out laser processing.
In order to ensure the quality of connection of active element and the first internal layer circuit figure, adopt the active element with salient point.Step active element being connected to the first internal layer circuit figure of the first loading plate can comprise: step S204a, uses Flip chip machine to be held in the passive face of active element; Step S204b, according to the bonding parameter preset, by the first internal layer circuit figure of active surface back bonding to the first loading plate of active element.In order to ensure the validity that active element is connected with loading plate, following two kinds of methods can be adopted:
First method, can also comprise after above-mentioned steps S204: fill underfill in the joint portion of active element and the first loading plate, carry out reflow soldering.Herein, underfill can make active element carry out autoregistration in reflow process, the impact that bulk temperature expansion characteristics does not mate or external force causes between active element with loading plate can also be effectively reduced, the glue material that the glue of filling adopts this area conventional;
Second method: adopt anisotropic conducting film or anisotropy conductiving glue as connecting material, bonding pressure at this moment and temperature are different.
For being encapsulated into inner active element, the heat radiation of its inside is very important problem.Traditional chip package all adopts fin or cooling device to dispel the heat, but fin and cooling device volume are all a little large, are unfavorable for realizing compact package.
In the present embodiment, also comprise after the active surface of active element being connected to the step of the first internal layer circuit figure of the first loading plate: Adhesion Interface heat sink material or interpolation metal fin on passive of active element, this interface scattering material is silicone oil, heat-conducting glue, heat-conducting silica gel sheet or novel interfacial heat sink material etc.Preferably, passive of active element adheres to novel interfacial heat sink material.This novel interfacial heat sink material refers to and adopts electrostatic spinning (Electrospinning) technology by polyurethane (Polyurethane, PU) the nanofiber substrate of interface heat sink material is prepared into, and add high hot nano particle on this basis, make it have high thermal conductivity (see this area relate art literature).This interface heat sink material can be produced on the back side of active element, forms high heat dissipation interface, improves the capacity of heat transmission of adhesive interface, to improve the heat-sinking capability of element.This novel interfacial heat sink material can also make different thickness as required.For lower powered active element, adhere to one deck novel interfacial heat sink material and help its heat radiation, in addition, for high-power active element, also need to dose metal fin, or on substrate, open the measures such as some louvres, effectively can carry out the heat radiation of active element.
According to another aspect of the present invention, a kind of substrate of embedding active element is additionally provided.This substrate comprises by hot binding: the first loading plate, dielectric-slab and the second loading plate.Wherein, on dielectric-slab, the correspondence position of active element arranges hole, and the length in hole and width are equal to or are greater than length and the width of active element; Active element is connected to the first internal layer circuit figure on the first loading plate, and inserts in the hole of dielectric-slab.Preferably, in this substrate, dielectric-slab is one or more layers, and the gross thickness of one or more layers dielectric-slab is greater than the thickness of active element.Dielectric-slab adopts the one in following material to prepare: polyimides, polypropylene, liquid crystal polymer, span come vinegar imines-cyanate resin, epoxy resin, polytetrafluoroethylene or phenylpropyl alcohol cyclobutane.
Below by the basis of above-described embodiment, provide optimum embodiment of the present invention: the embodiment of embedding active element method in a substrate.Needs illustrate, the embodiment of this optimum, only for understanding the present invention, is not limited to protection scope of the present invention.Further, the feature in optimum embodiment, when nothing indicates especially, be applicable to method and related substrate, the technical characteristic occurred in identical or different embodiment can combinationally use in not conflicting situation all simultaneously.
The present embodiment is divided into nine steps, is described respectively below with reference to accompanying drawing.
Step one, first loading plate 100 and the second loading plate 200 all adopts the epoxy resin of double-sided copper-clad, span carrys out vinegar imines-organic resin film such as cyanate resin or liquid crystal polymer, be approximately 200 to 250 microns thick, conductive layer adopts layers of copper, be approximately 10 to 20 microns thick, as shown in Figure 3 a.
Step 2, by double-sided copper-clad first loading plate 100 and the second loading plate 200 by traditional PCB technology step, comprises the steps such as press mold, exposure, etching and striping and forms internal layer circuit figure.In more detail, the wiring diagram film with predetermined inner layer circuit pattern in layers of copper 102 and 202, then sticks on photo-conductive film by use hot-rolling by photo-conductive film hot pressing tightly.Subsequently, by figuratum wiring diagram film to ultraviolet photoetching, photo-conductive film is cured.Use developer solution such as sodium carbonate and potash to process, dissolve part uncured in photo-conductive film, expose the layers of copper 102 on the first loading plate 100 and the layers of copper 202 on the second loading plate 200.Using the photosensitive pattern after remaining solidification as mask, the layers of copper 102 and 202 exposed is etched, forms predetermined inner layer circuit pattern.Here the internal layer circuit figure that making two kinds is different is needed, a kind of be the first loading plate 100 layers of copper 102 on formed and connect the internal layer circuit figure of active element, as shown in Figure 3 b, another kind be the second loading plate 200 layers of copper 202 on form internal layer circuit figure, as shown in Figure 4.
Step 3, on the first loading plate 100 (Fig. 3 b) utilizing face-down bonding technique to be connected to by active element 104 active surface with salient point with internal layer circuit figure.For the active element with salient point, use Flip chip machine, after carrying out bonding connection under certain temperature and pressure, Reflow Soldering is carried out after underfill, underfill can carry out autoregistration in reflow process, effectively can also reduce the impact that bulk temperature expansion characteristics does not mate or external force causes between active element with loading plate.Certainly anisotropy conductiving glue or anisotropic conducting film can also be adopted as connecting material, at this moment bonding pressure and temperature are different, for anisotropic conducting film 106, first the suction nozzle of Flip chip machine is used to be held in passive for active element 104 face, because coverlay is all posted in anisotropic conducting film two sides, therefore anisotropic conducting film 106 coverlay is removed, stick in the layers of copper 102 with the first loading plate 100 of circuitous pattern, then bonding parameter is set, finally carry out the Flip chip of active element at the first loading plate.In bonding process, bonding pressure is 30N, and bonding temperature is 180 DEG C, and bonding time is 180s, as shown in Figure 3 c.
Step 4, passive at active element 104 adheres to one deck novel interfacial heat sink material 108, as shown in Figure 3 d.The present embodiment mainly adopts a kind of novel interfacial heat sink material 108 based on nanometer technology, use macromolecular material as substrate, employing electrospinning processes is prepared, the back side of active element can be produced on, form high heat dissipation interface, improve the capacity of heat transmission of adhesive interface, to improve the heat-sinking capability of element.This novel interfacial heat sink material can also make different thickness as required.And for high-power active element, also need to dose metal fin, or on substrate, open the measures such as some louvres, effectively can carry out the heat radiation of active element.
Step 5, as shown in Figure 5, adopts the method for laser processing dielectric-slab 300 to be carried out to the making of " hole " shape." hole " of the embedding active element of employing laser processing is the method for the cave wall quality that can obtain best " hole " shape in current various processing " hole " and not have " lateral erosion ".
Step 6, as shown in Figure 6, by the first loading plate 100 with active element, the dielectric-slab 300 of band " hole " and the second loading plate 200 carry out disposable hot pressing after aiming at.Its laminar structure is followed successively by from top to bottom: inverted the first loading plate 100 being connected with active element 104 of one deck, and the dielectric-slab 300 of one deck band " hole " and one deck are with the second loading plate 200 of circuitous pattern.The making first carrying out location hole is needed, effectively to aim in lamination process in making.Multilager base plate profile after lamination as shown in Figure 7.Concrete implementing process is: under 10 pressure to 20kgf/cm2, at the temperature of about 200 DEG C, (this is the glass transition temperature of dielectric-slab) carries out disposable pressing.
Step 7, as shown in Figure 8, adopts laser drill multilager base plate to be carried out to the preparation of through hole 400.Adopt laser drilling process method, process multiple-plate vertical openings, guarantee the dimensional accuracy of opening, and physical property not too large change.
Step 8, as shown in Figure 8, carries out metallization processes to the through hole of multilager base plate.Hole metallization process is divided into desmearing, electroless copper plating and plating three processes.The effect of desmearing is the resin diamond dirt of removing Yin Gaowen in high-speed drilling process and producing, the height reliability that after ensureing hole metallization, circuit connects.In hole and on plate surface deposition, 0.5-1.0 micron chemical copper is as Seed Layer first to use chemical deposition mode, and then employing electro-plating method carries out metallization and the filling of through hole.For plating, concrete technological parameter is: plating solution main component is copper sulphate and sulfuric acid, adopts the low copper formula of peracid, and when ensureing to electroplate, the uniformity of plate face thickness distribution and the covering power to deep hole aperture, be added with the chloride ion of trace in plating solution; Temperature maintains room temperature state, and general temperature is no more than 32 degree, multi-control at 22 degree, therefore in summer because temperature is too high, need cooling temperature control system be installed additional.
Step 9, by embedding have an active element cover copper multi-layer sheet by traditional PCB technology step, comprise gluing, exposure, etching and remove the steps such as glue in the layers of copper 112 of the first loading plate 100 and the layers of copper 212 of the second loading plate 200, form different outer circuit figure, as shown in Figure 9.
In addition, this is the simplest " interlayer " structure just, can according to the demand of circuit module, carry out more complicated structural design, the such as compound of multiple " interlayer " structure, as shown in FIG. 10 and 11, here select different modes stacking as required, both the stacking different active element of sequential system can have been adopted to imbed module, module can also be imbedded by the stacking different active element of back-to-back mode, in addition, can also simultaneously by active element (104) and passive component (502, 504) be embedded in together in multilager base plate, form system-level three-dimension packaging, as shown in figure 12, wherein ... for being packaged in the passive component within substrate.
In sum, the present invention has following beneficial effect: the method for (1) the present invention embedding active element in a substrate adopts new " finally " embedding active element form, namely disposable lamination " interlayer " imbeds the method for active element, has the reworkable property of simple processing step, high productivity ratio and excellence; (2) in the present invention, active element or passive have adhered to floor height thermally-conductive interface heat sink material and/or a metal fin, or substrate arranges louvre, and therefore active element can efficiently radiates heat; (3) the embedding substrate module of active element in the present invention, can also carry out " lamination " again and connect, and the three-dimensional realizing active element in encapsulation is carried, thus realizes the system in package of carrying whole passive component and active element in same encapsulation; (4) method that adopts of whole technique can with planar semiconductor process compatible, finally realize integration and make.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (17)
1. a method for embedding active element in a substrate, it is characterized in that, the method comprises:
The conductive layer of the first loading plate is formed the first internal layer circuit figure;
Active element is connected to the described first internal layer circuit figure on the first loading plate;
The correspondence position processing hole of described active element on dielectric-slab, the length in described hole and width are equal to or are greater than length and the width of described active element;
By the second loading plate, the dielectric-slab with described hole and the first loading plate aligned stack successively with active element, form active element and imbed module, active element on described first loading plate is positioned at the inside that described active element imbeds module, inserts the described hole on dielectric-slab;
Described active element is imbedded module and carries out hot pressing, form the substrate of embedding active element, the temperature of described hot pressing is more than or equal to the glass transition temperature of described dielectric-slab;
Wherein, describedly also to comprise before the step of the second loading plate, the dielectric-slab with described hole and the first loading plate with active element successively aligned stack: on the conductive layer of the second loading plate, form the second internal layer circuit figure; Described by the step of the second loading plate, the dielectric-slab with described hole and the first loading plate with active element successively aligned stack: the described second internal layer circuit figure on the second loading plate is imbedded inside module towards described active element.
2. method according to claim 1, is characterized in that: described dielectric-slab is one or more layers, and one or more layers the gross thickness of dielectric-slab described is greater than the thickness of described active element.
3. method according to claim 2, it is characterized in that, described dielectric-slab adopts the one in following material to prepare: polyimides, polypropylene, liquid crystal polymer, span come vinegar imines-cyanate resin, epoxy resin, polytetrafluoroethylene or phenylpropyl alcohol cyclobutane.
4. method according to claim 2, it is characterized in that: in the step in the correspondence position processing hole of described described active element on dielectric-slab, the mode of described processing is the one in following methods: photoetching process, plasma etching method or laser processing method.
5. method according to claim 1, is characterized in that, for the active element with salient point, the step of the described described first internal layer circuit figure be connected to by active element on the first loading plate comprises:
Flip chip machine is used to be held in the passive face of active element;
According to the bonding parameter preset, by the first internal layer circuit figure of active surface back bonding to the first loading plate of described active element.
6. method according to claim 5, is characterized in that,
Describedly also to comprise after the step of the first internal layer circuit figure of active surface back bonding to the first loading plate of active element: fill underfill in the joint portion of described active element and described first loading plate, carry out reflow soldering; Or
Describedly also to comprise before the step of the first internal layer circuit figure of active surface back bonding to the first loading plate of active element: on described first loading plate, cover connecting material, this connecting material is anisotropic conducting film or anisotropy conductiving glue.
7. method according to claim 1, is characterized in that,
Also comprise after the step of described described first internal layer circuit figure active element is connected on the first loading plate: Adhesion Interface heat sink material or interpolation metal fin on passive of described active element; Or
Described module of being imbedded by active element carries out hot pressing, also comprises: arrange louvre on the substrate after forming the step of the substrate of embedding active element, and this louvre is used for the heat radiation of embedding described active element in it.
8. method according to claim 7, is characterized in that,
Described interface heat sink material is adopt electrostatic spinning technique polyurethane to be prepared into the nanofiber substrate of interface heat sink material, and adds high hot nano particle on this basis and be prepared from.
9. method according to claim 1, is characterized in that, described being imbedded after module carries out the step of hot pressing by described active element also comprises:
The opposite side conductive layer that described first internal layer circuit figure place conductive layer is relative on described first loading plate forms the first outer circuit figure; And/or
The opposite side conductive layer that described second internal layer circuit figure place conductive layer is relative on described second loading plate forms the second outer circuit figure.
10. method according to claim 1, is characterized in that, described by the second loading plate, also comprise with before cuniculate dielectric-slab and the step with the first loading plate aligned stack successively of active element:
Passive component is connected to the first internal layer circuit figure or the second internal layer circuit figure;
The correspondence position processing hole of described passive component on dielectric-slab, the length in described hole and width are equal to or are greater than length and the width of described passive component.
11. methods according to any one of claim 1 to 8, is characterized in that, described being imbedded after module carries out the step of hot pressing by described active element also comprises:
The through hole perpendicular to described substrate is processed at the predeterminated position of described substrate;
Metallize to the described through hole on substrate, this through hole is used for the connection of active element and outer first circuitous pattern and outer second circuit figure.
12. methods according to any one of claim 1 to 8, is characterized in that,
Described by the second loading plate, with cuniculate dielectric-slab and the first loading plate aligned stack successively with active element, formed after active element imbeds the step of module and comprise: stacking multiple described active element imbeds module, each active element is imbedded module and is all imbedded default active element, every two described active elements are imbedded between module has intermodule dielectric-slab, the material of this intermodule dielectric-slab is identical with the material of described dielectric-slab, also can adopt different materials;
Describedly described active element is imbedded module carry out hot pressing, the step forming the substrate of embedding active element comprises: stacking multiple active elements are imbedded module and carries out hot pressing, forms the substrate of embedding multiple active element.
13. methods according to claim 12, is characterized in that, described stacking multiple active element is imbedded in the step of module: the adjacent active element active element imbedded in module is arranged or back-to-back setting in opposite directions.
The substrate of 14. 1 kinds of embedding active elements, is characterized in that, this substrate is comprised and being combined successively by hot pressing: the first loading plate, dielectric-slab and the second loading plate;
On described dielectric-slab, the correspondence position of described active element arranges hole, and the length in described hole and width are equal to or are greater than length and the width of described active element;
Active element is connected to the first internal layer circuit figure on the first loading plate, and inserts in the hole of described dielectric-slab;
Wherein, the conductive layer of the second loading plate forms the second internal layer circuit figure, this second internal layer circuit figure is towards the inner side of described substrate.
15. substrates according to claim 14, is characterized in that: described dielectric-slab is one or more layers, and one or more layers the gross thickness of dielectric-slab described is greater than the thickness of described active element.
16. substrates according to claim 14, it is characterized in that, described dielectric-slab adopts the one in following material to prepare: polyimides, polypropylene, liquid crystal polymer, span come vinegar imines-cyanate resin, epoxy resin, polytetrafluoroethylene or phenylpropyl alcohol cyclobutane.
17. substrates according to claim 14, is characterized in that,
Adhesion Interface heat sink material or interpolation metal fin on passive of described active element;
Or louvre established by described substrate, described louvre is used for the heat radiation of embedding described active element in it.
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| CN107305849B (en) * | 2016-04-22 | 2020-05-19 | 碁鼎科技秦皇岛有限公司 | Packaging structure and manufacturing method thereof |
| CN107946252A (en) * | 2017-12-22 | 2018-04-20 | 江苏宏微科技股份有限公司 | A kind of bottom plate of power module package |
| CN111637886A (en) * | 2020-05-28 | 2020-09-08 | 青岛歌尔智能传感器有限公司 | Navigation module and manufacturing process thereof |
| CN113727516B (en) * | 2021-08-27 | 2023-02-03 | Oppo广东移动通信有限公司 | Circuit board packaging structure and method thereof, and electronic equipment |
| CN116782506B (en) * | 2023-08-24 | 2023-11-24 | 荣耀终端有限公司 | Circuit board assembly, processing method thereof, circuit board stacking structure and electronic equipment |
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| TW201008410A (en) * | 2008-07-21 | 2010-02-16 | Samsung Electro Mech | Method of manufacturing electronic component embedded circuit board |
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| TW201008410A (en) * | 2008-07-21 | 2010-02-16 | Samsung Electro Mech | Method of manufacturing electronic component embedded circuit board |
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