US20120098800A1 - Gate driver and liquid crystal display including same - Google Patents

Gate driver and liquid crystal display including same Download PDF

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Publication number
US20120098800A1
US20120098800A1 US13/070,394 US201113070394A US2012098800A1 US 20120098800 A1 US20120098800 A1 US 20120098800A1 US 201113070394 A US201113070394 A US 201113070394A US 2012098800 A1 US2012098800 A1 US 2012098800A1
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United States
Prior art keywords
signal line
signal
wiring
shift registers
line
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US13/070,394
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English (en)
Inventor
Kwi-Hyun Kim
Jang-Soo Kim
Hyeong-Jun Jin
Soo-Chul Kim
Kyoung-Hae Min
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, HYEONG-JUN, KIM, JANG-SOO, KIM, KWI-HYUN, KIM, SOO-CHUL, MIN, KYOUNG-HAE
Publication of US20120098800A1 publication Critical patent/US20120098800A1/en
Assigned to SAMSUNG DISPLAY CO., LTD reassignment SAMSUNG DISPLAY CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG ELECTRONICS, CO., LTD
Priority to US14/459,140 priority Critical patent/US9275593B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure of invention relates to a gate driver structured such that its elements are better protected against being burned by static electricity and a liquid crystal display (LCD) including the gate driver.
  • LCD liquid crystal display
  • a liquid crystal display includes a display panel having a plurality of gate lines and a plurality of data lines, a gate driver transmitting a plurality of gate signals to the gate lines, and a data driver transmitting a plurality of data signals to the data lines.
  • each of the gate driver and data driver is mounted on a display panel in the form of one or more respective IC chips.
  • TFTs thin-film transistors
  • aspects of the present disclosure provide a gate-lines driver circuit structured such that the danger of its elements being burned out by static electricity is reduced.
  • aspects of the present disclosure also provide a liquid crystal display (LCD) including the static electricity tolerant gate-lines driver circuit.
  • LCD liquid crystal display
  • a gate driver including: a wiring unit which receives signals from an external source; and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit and includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th signal lines arranged sequentially in order of distance from the shift registers, with the first signal line being located farthest from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a shift register wiring extending to the first signal line, at least one of the second through n-th signal lines is divided into two spaced apart sections that have centered between them a line of the shift register wiring, and the two spaced apart sections are electrically connected (bridged) together by a connection line extending insulatively over the line of the shift register and having plural contact portions.
  • an LCD including a gate driver formed on a substrate, wherein the gate driver includes: a wiring unit which receives signals from an external source; and a circuit unit which outputs driving signals in response to a plurality of control signals received from the wiring unit and includes a plurality of shift registers, each having shift register wirings, wherein the wiring unit includes first through n-th signal lines arranged sequentially in order of distance from the shift registers, with the first signal line being located farthest from the shift registers, where n is a natural number, wherein the first signal line is connected to each of the shift registers by a first connection line, and the first connection line includes a first contact portion which is formed over and contacts the first signal line and a second contact portion which is located between the n-th signal line and the shift registers and is connected thereat to each of the shift registers by a shift register wiring.
  • FIG. 2 is an exemplary block diagram illustrating shift registers that constitute the gate driver shown in FIG. 1 ;
  • FIG. 3 is an exemplary circuit diagram of a j th shift register shown in FIG. 2 ;
  • FIG. 4 is a schematic layout diagram of the gate driver shown in FIG. 1 ;
  • FIG. 6 is a cross-sectional view of the wiring unit taken along the line I-I′ of FIG. 5 ;
  • FIG. 7 is a layout diagram of a wiring unit of a gate driver according to another exemplary embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view of the wiring unit taken along the line II-II′ of FIG. 7 .
  • Embodiments in accordance with the disclosure are described herein with reference to plan and cross-section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • a drain (or drain electrode) and a source (or source electrode) may be named differently according to the direction of current, an element called a drain or drain electrode hereinafter may operate as a source or source electrode, and an element called a source or source electrode may operate as a drain or drain electrode. Accordingly, an element called a drain or drain electrode is not limited to the drain or drain electrode. Also, the element called the source or source electrode is not limited to the source or source electrode.
  • FIG. 1 is a schematic of a gate driver 400 and an LCD 10 including the same according to the first exemplary embodiment.
  • FIG. 2 is an exemplary block diagram illustrating shift registers SR 1 through SR n+1 that constitute the gate driver 400 shown in FIG. 1 .
  • FIG. 3 is an exemplary circuit diagram of a j th shift register SR j shown in FIG. 2 .
  • FIG. 4 is a schematic layout diagram of the gate driver 400 shown in FIG. 1 .
  • FIG. 5 is an exemplary schematic layout diagram of a wiring unit LS of the gate driver 400 shown in FIG. 1 .
  • FIG. 6 is a cross-sectional view of the wiring unit LS taken along the line I-I′ of FIG. 5 .
  • the display device 10 includes a liquid crystal panel 300 , a gate driver 400 integrally incorporated in the panel 300 , a timing controller 500 , a clock generator 600 , and a data driver 700 .
  • the liquid crystal display 300 is divided into a display area DA in which an image is displayed and a non-display or peripheral area PA in which the image is not displayed.
  • the display area DA includes a first substrate (not explicitly shown) on which there are formed a plurality of gate lines G 1 through Gn, a plurality of data lines D 1 through Dm, a plurality of pixel switching devices (not explicitly shown) and a plurality of pixel electrodes (not explicitly shown) are disposed.
  • a second substrate (not shown) is further provided and spaced apart from the first substrate where the second substrate has a plurality of color filters (not shown) and a common electrode (not shown).
  • a liquid crystal layer (not shown) is interposed between the first and second substrates and orientations of its liquid crystal molecules are controlled by electric fields formed between the pixel-electrodes and corresponding portions of the common electrode.
  • the gate lines G 1 through Gn and the data lines D 1 through Dm respectively extend on their supporting first substrate in the display area DA thereof and in respective a row and column directions.
  • switching devices and a plurality of pixels PX connected to the gate lines G 1 through Gn and the data lines D 1 through Dm are formed in pixel regions PX defined by intersections of the gate lines G 1 through Gn and the data lines D 1 through Dm.
  • the timing controller 500 receives input control signals, such as a horizontal synchronization signal Hsync, a main clock signal Mclk and a data enable signal DE, and outputs an image signal DAT and a first control signal CONT 1 .
  • the first control signal CONT 1 controls the operations of the data driver 700 .
  • Examples of the first control signal CONT 1 include a horizontal start signal for starting the data driver 700 and a load signal for instructing the output of corresponding analog data voltages.
  • the timing controller 500 sends a vertical synchronization start signal to the clock generator 600 by being synchronized with a vertical synchronization signal Vsync and provides a second control signal CONT 2 to the clock generator 600 .
  • the clock generator 600 receives the second control signal CONT 2 from timing controller 500 and outputs a clock signal CKV and a clock bar signal CKVB. That is, in response to the second control signal CONT 2 , the clock generator 600 outputs the clock signal CKV and the clock bar signal CKVB using a gate-on voltage level, Von and a gate-off voltage level Voff. Examples of the second control signal CONT 2 include an output enable signal OE and a gate clock signal CPV.
  • the clock signal CKV and the clock bar signal CKVB are pulse signals that swing between the gate-on voltage level Von and the gate-off voltage level Voff.
  • the clock signal CKV may be a reverse phase signal of the clock bar signal CKVB.
  • the gate driver 400 may be disposed in the non-display area PA of the first substrate. Although only a one-side version is shown in the drawings, a plurality of the gate drivers 400 may be respectively disposed on two opposed sides of the non-display region PA of the first substrate with the display area DA between them. In the latter case, a gate driver 400 a (not shown) disposed on a first side of the non-display area PA of the first substrate may drive, e.g., even gate lines of the gate lines, while a different gate driver 400 b (not shown) disposed on the opposite second side of the non-display area PA may drive, e.g., odd gate lines of the gate lines. Alternatively, the gate drivers 400 formed on both sides of the non-display region PA may each drive all of the gate lines G 1 through Gn, respectively.
  • the gate driver 400 When enabled by a scan start signal STVP, the gate driver 400 generates a plurality of gate signals using the clock signal CKV, the clock bar signal CKVB and a direct current (DC) voltage signal Vss. The gate driver 400 sequentially transmits Von pulses of the gate signals to corresponding ones the gate lines G 1 through Gn, one after the next.
  • a scan start signal STVP When enabled by a scan start signal STVP, the gate driver 400 generates a plurality of gate signals using the clock signal CKV, the clock bar signal CKVB and a direct current (DC) voltage signal Vss.
  • the gate driver 400 sequentially transmits Von pulses of the gate signals to corresponding ones the gate lines G 1 through Gn, one after the next.
  • the gate driver 400 includes a plurality of shift registers SR 1 through SR n+1 , where n is a natural number greater than one.
  • the shift registers SR 1 through SR n+1 receive the clock signal CKV, the clock bar signal CKVB and the DC voltage signal Vss and sequentially provide a plurality of gate signals to the gate lines G 1 through Gn.
  • the gate lines G 1 through Gn are connected to output terminals of the shift registers SR 1 through SR n+1 , respectively.
  • the shift registers SR 1 through SR n+1 are connected to each other in a cascade manner.
  • Each of the shift registers SR 1 through SR n+1 includes a first clock terminal CK 1 , a second clock terminal CK 2 , a set terminal S, a reset terminal R, a source voltage terminal GV (ground voltage), a frame reset terminal FR, a gate signal output terminal OUT 1 and a carry output terminal OUT 2 .
  • the j th shift register SR j for example, connected to a j th gate line (where j ⁇ 1 and is a natural number ranging from 2 through n ⁇ 1) will now be described in further detail still with reference to FIG. 2 .
  • a carry signal Cout (j ⁇ 1) of a previous shift register e.g., the (j ⁇ 1) th shift register SR j ⁇ 1
  • the gate signal Gout (j ⁇ 1) of a subsequent shift register e.g., the (j+1) th shift register SR j+1
  • the clock signal CKV and the clock bar signal CKVB are input to the first clock terminal CK 1 and the second clock terminal CK 2 , respectively, of the j th shift register SR j .
  • the DC voltage signal Vss is input to the source voltage terminal GV of the j th shift register SR j , and an initialization signal INT or, alternatively, a carry signal Cout (n+1) of a last shift register, e.g., the (n+1) th shift register SR n+1 , is input to the frame reset terminal FR of the j th shift register SR 1 .
  • the gate output terminal OUT 1 outputs the gate signal Gout (j)
  • the carry output terminal OUT 2 outputs a carry signal Cout j ) for application to the S input of the next stage.
  • the scan start signal STVP instead of a carry signal of a previous shift register of the first shift register SR 1 , is input to the first shift register SR 1 .
  • the scan start signal STVP instead of a gate signal of a next shift register of the last shift register SR n+1 , is input to the last shift register SR n+1 .
  • the scan start signal STVP input to the first shift register SR 1 is substantially the same as the scan start signal STVP input to the last shift register SR n+1 .
  • the buffer unit 410 includes a transistor T 4 .
  • a gate electrode and a drain electrode of the transistor T 4 are shorted together and connected to the set terminal S of the j th shift register SR j . Since the gate and drain electrode of the transistor T 4 are connected to each other, transistor T 4 operates substantially like a diode.
  • the buffer unit 410 provides to the N 1 node, the high level if present of the carry signal Cout (j ⁇ 1) of the previous shift register SR j ⁇ 1 , which is received through the set terminal S. In other words, if N 1 is low, the buffer unit 410 provides a recharging voltage to the charging unit 420 , as well as to the gate of the carry signal generation unit 470 , and to the gate of the pull-up unit 430 .
  • the pull-up unit 430 includes a gate-line driving transistor (TFT) T 1 including a drain electrode connected to the first clock terminal CK 1 , a gate electrode connected to the charging unit 420 , and a source electrode connected to the gate-line driving first output terminal, OUT 1 .
  • TFT gate-line driving transistor
  • the pull-down unit 440 includes a transistor T 2 including a drain electrode connected to the source electrode of the transistor T 1 and the second terminal of the capacitor C 1 , a source electrode connected to the voltage source terminal GV, and a gate electrode connected to the reset terminal R.
  • the gate electrode controls the transistor T 2 by receiving the gate signal Gout (j+1) of the next shift register SR j+1 . Accordingly, if the Gout (j+1) signal of the next shift register SR j+1 is high (logic high (“1”) as well as voltage high), the pull-down unit 440 will be activated to pull the gate-line driving first output terminal, OUT 1 low.
  • the discharging unit 450 includes transistors T 6 and T 9 .
  • the transistor T 9 includes a gate electrode connected to the reset terminal R, a drain electrode connected to the first terminal of the capacitor C 1 , and a source electrode connected to the voltage source terminal GV.
  • the transistor T 9 discharges the charging unit 420 in response to the gate signal Gout (j+1) of the next shift register SR (j+1) . In other words, if the Gout (j+1) signal of the next shift register SR j+1 is high, the discharging unit 450 will be activated to pull the N 1 node low.
  • the transistor T 6 includes a gate electrode connected to the frame reset terminal FR, a drain electrode connected to the first terminal of the capacitor C 1 , and a source electrode connected to the voltage source terminal GV.
  • the transistor T 6 discharges the charging unit 420 in response to the initialization signal INT. In other words, if the INT signal is high, the discharging unit 450 will be activated to pull the N 1 node low.
  • the holding unit 460 includes a large plurality of transistors, namely, T 3 , T 5 , T 7 , T 8 , T 10 , T 11 , T 12 and T 13 .
  • the holding unit 460 switches to state in which it urges the gate signal Gout (j) to remain at the high level.
  • the holding unit 460 switches to state in which it urges the gate signal Gout (j) to remain at the low level during a frame, where the held level is without regard to switching voltage levels of other signals such as those of the clock signal CKV or the clock bar signal CKVB.
  • the driven gate line connected to the OUT 1 terminal has inherent capacitance and this works to keep the gate-line signal Gout (j) steady.
  • the layout of the gate driver 400 includes circuit unit (CS).
  • This circuit unit(CS) includes the plurality of shift registers SR 1 through SR n+1 .
  • the layout of the gate driver 400 further includes a wiring unit (LS).
  • This wiring unit (LS) contains vertically elongated conductors and horizontally elongated conductors which deliver various external signals (Vss, STVP, INT, CKV, CKVB, etc.) to the shift registers SR 1 through SR n+1 .
  • the circuit unit CS includes the shift registers SR 1 through SR n+1 , each including its respective plurality of TFTs T 1 through T 13 and T 15 .
  • the transistors T 1 through T 13 and T 15 in, for example, the j th shift register SR j shown in the upper portion of FIG. 4 , the transistor T 4 to which the carry signal Cout (j ⁇ 1) of the previous shift register SR j ⁇ 1 is input is disposed in an upper part of the j th shifter register SR j which is close to the lower boundary of previous shift register SR j ⁇ 1 (not shown).
  • the transistors T 15 and T 1 of SR j which receive the CK 1 clock signal from the CKV transmission line extend horizontally adjacent to the upper boundary of the j th shifter register SR j
  • the transistors T 7 , T 10 and T 12 which also receive the CK 1 clock signal from the CKV transmission line are also disposed adjacent to the upper boundary of the j th shifter register SR j , but vertically under the transistor T 15 .
  • the transistors T 11 and T 5 of SR j which receive the CK 2 clock bar signal from the CKVB transmission line arriving from thereunder are disposed in a lower left boundary part of the j th shifter register SR j .
  • the wiring unit LS includes first through n th vertically elongated signal lines, where n is a natural number.
  • the first through n th vertical signal lines (e.g., the ones denoted as 21 - 25 in FIG. 5 ) extend parallel to each other in a substantially vertical direction.
  • the first through n th vertical signal lines are arranged sequentially in order of their distance from the left side boundaries of adjacent shift registers SR 1 through SR n+1 , with the first such vertical signal line (e.g., Vss 21 ) being farthest away from the corresponding adjacent edge boundaries of the adjacent layouts of shift registers SR 1 through SR n+1 .
  • Vss 21 vertical signal line
  • first through fifth signal lines 21 through 25 are arranged sequentially in order of their distance from the shift registers SR 1 through SR n+1 , with the first signal line 21 (Vss) being farthest from the shift registers SR 1 through SR n+1 .
  • the wiring unit LS includes as its first vertical signal line 21 , the DC voltage signal line which delivers the DC voltage signal Vss. Moreover, the wiring unit LS includes as its second vertical signal line 22 , the scan start signal line which delivers the scan start signal STVP, as its third vertical signal line 23 , the initialization signal line which delivers the initialization signal INT, as its fourth vertical signal line 24 , the clock signal line which delivers the clock signal CKV, and as its fifth vertical signal line 25 , the clock bar signal line which delivers the clock bar signal CKVB.
  • the number of differently phased ones of such vertical clock signal lines may vary and when more than two such vertical clock signal lines (e.g., 24 , 25 ) are provided, the connections to the CK 1 and CK 2 terminals of each register stage may vary depending on design specifics.
  • the connections to the CK 1 and CK 2 terminals of each register stage may vary depending on design specifics.
  • the DC voltage signal line e.g., the first vertical signal line 21
  • the scan start signal line e.g., the second vertical signal line 22
  • the initialization signal line e.g., the third vertical signal line 23
  • the clock signal line e.g., the fourth vertical signal line 24
  • the clock bar signal line e.g., the fifth vertical signal line 25
  • the clock bar vertical signal line 25 being located closest to such adjacent to the left edge boundaries of the shift registers SR 1 through SR n+1 and the DC voltage vertical signal line 25 being located farthest away from the left edge boundaries.
  • the first through n th vertical signal lines are connected to the shift registers SR 1 through SR n+1 .
  • the DC voltage signal line e.g., the first signal line 21
  • the initialization signal line e.g., the third signal line 23
  • the scan start signal line e.g., the second signal line 22
  • the scan start signal line is not shown as being connected to the j th shift register SR j .
  • the clock signal line (e.g., the fourth signal line 24 ) and the clock bar signal line (e.g., the fifth signal line 25 ) are located near the upper and lower boundaries of the shift registers SR 1 and SR n+1 and are alternately connected to respective ones of the Ck 1 and CK 2 terminals of each of the shift registers SR 1 and SR n+1 . Since substantially all current is sunk through it, the DC voltage vertical signal line carries more current. Therefore, the DC voltage vertical signal line 21 should have a smaller resistivity per unit length than the other vertical signal lines. In one embodiment, the DC voltage vertical signal line is formed with a greater width (as seen from a top plan view) than the other vertical signal lines.
  • first vertical signal line 21 is connected into the interiors of each of the shift registers SR 1 through SR n+1 by way of a corresponding set of first horizontal connection lines 81 .
  • Each first horizontal connection line 81 includes a first cross-layer contact portion 81 a and a second cross-layer contact portion 81 b.
  • the first cross-layer contact portion 81 a is a region which is formed by contiguously extending an end of the first horizontal connection line 81 through corresponding openings in one or more insulation (dielectric) layers so as to directly contact the first vertical signal line 21 .
  • the first contact portion 81 a is formed through a plurality of contact holes 71 that expose an upper surface of the first vertical signal line 21 .
  • the first connection line 81 is thus directly connected to the first signal line 21 by way of the contact holes 71 .
  • the second cross-layer contact portion 81 b is a region which is formed by extending the other end of the first connection line 81 contiguously through one or more openings of a one or more insulation (dielectric) layers so as to directly contact a shift register wiring 61 provided in the corresponding one of shift registers SR 1 through SR n+1 .
  • the second contact portion 81 b overlaps a bent extension portion 61 a of the shift register wiring 61 , and a plurality of contact holes 72 are provided along that bent extension portion 61 a for exposing the underlying shift register wiring 61 whereby any one or more of the plural contact holes 72 can provide a good contact between the second contact portion 81 b and its overlapped area along the extension portion 61 a of the shift register wiring 61 .
  • a first insulating film 30 is formed over the base substrate 10 after the first through fifth vertical signal lines 21 through 25 are formed on the base substrate 10 .
  • the shift register wiring 61 is thereafter formed on the first insulating film 30 .
  • a second insulating film 70 is then formed over the shift register wiring 61 and the first insulating film 30 .
  • Respective contact holes 71 and 72 are formed and then the first horizontal connection line 81 is formed on the second insulating film 70 .
  • the first through fifth vertical signal lines 21 through 25 and the shift register wiring 61 may each be made for example of an aluminum (Al)-based metal such as Al and/or an Al alloy, a silver (Ag)-based metal such as Ag and/or an Ag alloy, a copper (Cu)-based metal such as Cu and/or a Cu alloy, a molybdenum (Mo)-based metal such as Mo and/or a Mo alloy, chrome (Cr), titanium (Ti), or tantalum (Ta) or appropriate multi-layer combinations of two or more of these.
  • the first insulating film 30 may be formed of an inorganic material such as a silicon nitride or a silicon oxide, or a low-k insulating material formed by plasma enhanced chemical vapor deposition (PECVD), such as a-Si:C:O or a-Si:O:F.
  • PECVD plasma enhanced chemical vapor deposition
  • the first insulating film 30 may be formed to a thickness of 3,000 to 5,000 ⁇ .
  • the shift register wiring 61 extends on the first insulating film 30 . However, the shift register wiring 61 does not extend onto the first through n th vertical signal lines 21 through 25 . Also, as shown in FIG. 6 , the shift register wiring 61 is spaced apart from the second through n th vertical signal lines 21 - 25 by the combined thickness of dielectric layers 70 and 30 . Thus, even when static electricity flows into one or more of the second through n th vertical signal lines 21 - 25 of the gate-line driver 400 , it is unlikely to rapidly breakdown and through the double layer of dielectric layers 70 and 30 and thus it is unlikely to produce a surge current that can cause one or more of the shift register wiring 61 and the second through n th vertical signal lines 21 - 25 to be burned out.
  • the second insulating film 70 is formed on the first insulating film 30 as mentioned.
  • the second insulating film 70 may be formed of an inorganic material such as a silicon nitride or a silicon oxide, an organic material having photosensitivity and superior planarization characteristics, or a low-k insulating material formed by PECVD, such as a-Si:C:O or a-Si:O:F.
  • the second insulating film 70 may be formed to a thickness of 1,500 through 3,000 ⁇ .
  • the second insulating film 70 includes the contact holes 71 exposing the first signal line 21 and the contact holes 72 exposing the shift register wiring 61 .
  • the first horizontal connection line 81 is formed on the second insulating film 70 .
  • the first contact portion 80 a and the second contact portion 80 b are connected to form the first connection line 81 .
  • the first connection line 81 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO) and it may be formed to a width of 5 to 50 ⁇ m.
  • the first contact portion 81 a is formed on or close to the first vertical signal line 21 in order to be in contact with the first signal line 21 .
  • the second contact portion 81 b is located between the bulk of circuitry of each of the shift registers SR 1 through SR n+1 and the fifth vertical signal line 25 most adjacent to the left boundary of that bulk of circuitry.
  • the shift register wiring 61 formed on the first insulating film 30 terminates before crossing above the fifth signal line 25 as opposed to extending above any of the first through n th signal lines 21 - 25 . That is, the shift register wiring 61 is not formed in close overlapping proximity with one or more of the second through fifth signal lines 22 through 25 such that that static current can easily surge from one of those lines 22 through 25 up through the dielectric and into the shift register wiring 61 .
  • first horizontal connection line 81 including the first and second contact portions 81 a and 81 b is formed on the second insulating film 70 , a double dielectric layer comprised of the first and second insulating films 30 and 70 is interposed between the second through fifth vertical signal lines 22 through 25 and the first connection line 81 . That is, a thicker insulating film is formed between the second through fifth signal lines 22 through 25 and the first connection line 81 and this helps to reduce the danger that they will by burned out by a surge of static electricity current flowing into the gate-line driver 400 by way of any one or more of lines 22 - 25 .
  • the first vertical signal line 21 is located farthest from the bulk circuitry of the shift registers SR 1 through SR n+1 .
  • the shift register wiring 61 may be formed on the first insulating film 30 to overlap the second through n th signal lines. In this case, however, only the first insulating film 30 exists as separation for example between the second through n th vertical signal line Thus, the relative distance between the second vertical through n th signal lines and the shift register wiring 61 . is reduced, thus putting the shift registers at risk of being burned out by static electricity. For this reason, the first signal line 21 is connected to each of the shift registers SR 1 through SR n+1 only by way of the first connection line 81 which line is also spaced apart by double films 30 and 70 from the other vertical lines 21 - 25 .
  • the first vertical signal line 21 may be the DC voltage signal line.
  • the DC voltage signal line may be formed wider than the other vertical signal lines in order to reduce its resistivity. Also it may be placed first and thus closest to an edge of the substrate so as to protectively ring around the substrate and first absorb and redistribute any static shock that comes in from the edge of the substrate.
  • the shift register wiring 61 includes a gate line and a source or drain line formed in each of the shift registers SR 1 through SR n+1 .
  • the shifter register wiring 61 includes the extension portion 61 a formed by extending an end thereof The extension portion 61 a is overlapped by the second contact portion 81 b, and the contact holes 72 expose the shift register wiring 61 multiple times.
  • the first through n th signal lines formed in the wiring unit LS are connected to deliver respective external signals to the bulk circuitry of each of the shift registers SR 1 through SR n+1 .
  • the first signal line 21 is the DC voltage signal line, it may be connected to serve as a static electricity absorbing and redistributing conductor for each of the shift registers SR 1 through SR n+1 .
  • At least one of the second through n th vertical signal lines 22 - 25 may be connected to each of the shift registers SR 1 through SR n+1 by at least one of second through n th horizontal connection lines of similar structure to the detailed structure of the first horizontal connection line 81 .
  • the third vertical signal line 23 INT is shown connected to SR j by a third horizontal connection line 83 .
  • the third horizontal connection line 83 includes its own corresponding first contact portion 83 a and a second contact portion 83 b.
  • the first contact portion 83 a extends through plural dielectric layers (e.g., 30 and 70 ) to contact the third vertical signal line 23 at multiple locations there-along.
  • the second contact portion 83 b is located between the n th vertical signal line ( 25 ) and the left boundary each of the shift registers SR 1 through SR n+1 and is connected multiple times to each of the shift registers SR 1 through SR n+1 as is indicated in FIG. 5 .
  • the first contact portion 83 a extends through plural ones of spaced apart contact holes 73 which expose the third signal line 23 in multiple places so as to thereby more assuredly connect its end of the third horizontal connection line 83 to the third vertical signal line 23 .
  • the second contact portion 83 b similarly overlaps an extension portion 62 a formed by extending an end of a shift register wiring 62 and includes multiple spaced apart contact holes 74 exposing the shift register wiring 62 in different places so as to thereby more assuredly connect its end of the third horizontal connection line 83 to the corresponding extension portion 62 a of the shift register wiring.
  • the corresponding shift register wiring 62 is formed on the first insulating film 30 but does not extend directly over the third through n th signal lines.
  • the third horizontal connection line 83 is formed on the second insulating film 70 which is disposed above the first insulating film 30 . Since the first and second insulating films 30 and 70 are interposed between the third through n th signal lines and the third connection line 83 , the third through n th signal lines are located relatively far apart from the third connection line 83 . Accordingly, the third through n th signal lines and the third connection line 83 can be prevented from being burned by static electricity flowing into the gate driver 400 .
  • the third vertical signal line 23 may be any type of signal line, such as the scan start signal line (STVP), the initialization signal line (INT), a first clock signal line (e.g., CKV), or a clock bar signal line (e.g., CKVB).
  • STVP scan start signal line
  • INT initialization signal line
  • CKV first clock signal line
  • CKVB clock bar signal line
  • the third vertical connection line 23 is shown to be the initialization signal line.
  • the shift register wiring 62 may be a gate line of transistor T 6 . This is because the initialization signal line is connected to the gate line of the T 6 transistor of each of the shift registers SR 1 through SR n+1 .
  • the n th vertical signal line (e.g., the fifth signal line 25 ) which is the last signal line and thus closest to the shift registers SR 1 through SR n+1 is connected to each of the shift registers SR 1 through SR n+1 by a shift register clock wiring 63 extending to the n th signal line.
  • the shift register wiring 63 is extended to the fifth signal line 25 , and the extended shift register wiring 63 and the fifth signal line 25 are connected to each other by a fifth and relatively short, horizontal connection line 95 .
  • an extension portion 63 a is formed at an end of the extended shift register wiring 63 .
  • the fifth connection line 95 overlaps the fifth signal line 25 and overlaps the extension portion 63 a of the shift register wiring 63 , and uses contact holes 75 and 76 to make contact with the underlying conductors. More specifically, the fifth signal line 25 and the shift register wiring 63 are connected by the contact holes 75 and 76 .
  • the shift register wiring 63 is extended to the n th signal line (e.g., the fifth signal line 25 ) which is the last signal line and closest to the shift registers SR 1 through SR n+1 , it is not formed directly above the first through n th signal lines. Therefore, the shift register wiring 63 and the first through n th signal lines are prevented from being burned by static electricity flowing into the gate driver 400 .
  • FIG. 7 is a layout diagram of a wiring unit LS of the second gate-line driver 400 ′ according to the second exemplary embodiment.
  • FIG. 8 is a cross-sectional view of the wiring unit LS taken along the line II-II′ of FIG. 7 .
  • elements having the same functions as those of the previous exemplary embodiment of FIGS. 1 through 6 are indicated by like reference numerals, and thus their description will be omitted.
  • the gate-line driver 400 ′ and the LCD according to the current exemplary embodiment have substantially the same structures as the gate driver 400 and the LCD 10 according to the previous exemplary embodiment, except for the connection structure between the wiring unit LS of the gate driver 400 and shift registers SR 1 through SR n+1 . Thus, the following description will focus on this difference.
  • the gate driver 400 ′ includes a circuit unit CS which includes a plurality of shift registers SR 1 through SR n+1 and the wiring unit LS which delivers various signals (Vss, STVP, INT, CKV, CKVB, etc.) to the shift registers SR 1 through SR n+1 .
  • the wiring unit LS includes first through n th vertical signal lines, where n is a natural number.
  • the first through n th vertical signal lines extend parallel to each other in a substantially vertical direction.
  • the first through n th vertical signal lines are arranged sequentially in order of their distance from the shift registers SR 1 through SR n+1 , with the first vertical signal line being farthest from the shift registers SR 1 through SR n+1 .
  • a first vertical signal line 21 is connected to each of the shift registers SR 1 through SR n+1 by a relatively short sixth horizontal connection line 91 .
  • a shift register wiring 61 extends to the first signal line 21 and is connected to the relatively short sixth connection line 91 .
  • the Vss conveying shift register wiring 61 includes a vertically elongated extension portion 61 a formed by extending an end thereof.
  • the sixth connection line 91 overlaps the extension portion 61 a and makes contact to it at plural points ( 72 ).
  • the sixth connection line 91 also overlaps the first signal line 21 and makes contact to it at plural points ( 71 ).
  • plural contact holes 71 and 72 are formed in regions in which the sixth connection line 91 overlaps the first signal line 21 and the extension portion 61 a, respectively.
  • the first signal line 21 (Vss) and the shift register wiring 61 are thus connected plural times to each other by means of the corresponding portions of the sixth connection line 91 where the latter extends in and out through the contact holes 71 and 72 .
  • the shift register wiring 61 extends to and contacts the first signal line 21 , as shown in FIG. 8 , the shift register wiring 61 extends closely under (bit not connected to) electrostatic bridge conductors 96 and 97 which are provided to overlap the shift register wiring 61 at predetermined regions of one or more of the second through n th signal lines 22 - 25 . More specifically, in FIG. 8 , at least two of the second through n th vertical signal lines ( 22 , 23 ) are forked and the space between the fork tongs is partially overlapped with the shift register wiring 61 while the forks are connected to one another by electrostatic bridge conductors 96 and 97 (also referred to herein as horizontal connection lines).
  • each of a second vertical signal line 22 and a third vertical signal line 23 is divided into two sections (fork tongs) 22 a and 22 b of second vertical signal line 22 , or 23 a and 23 b of third vertical signal line 23 and the space between the two sections (fork tongs) is insulatively overlapped by the Vss-carrying shift register wiring 61 .
  • the second signal line 22 may be a scan start signal line
  • the third signal line 23 may be an initialization signal line.
  • the two sections 22 a and 22 b of the second signal line 22 are connected by a ( 7 - 1 ) th horizontal connection line 96 (also called an electrostatic bridge conductor here), and the two sections 23 a and 23 b of the third signal line 23 are connected by a ( 8 - 1 ) th horizontal connection line 97 (also referenced to as a second electrostatic bridge conductor here).
  • the ( 7 - 1 ) th connection line 96 extends into contact holes 77 and 78 formed to expose respective ends of the two sections 22 a and 22 b of the second signal line 22
  • the ( 8 - 1 ) th connection line 97 extends into contact holes 79 and 80 formed to expose respective ends of the two sections 23 a and 23 b of the third signal line 23 .
  • the two sections 22 a and 22 b of the second signal line 22 are thus electrically connected or bridged to each other by the bridge 96 made between contact holes 77 and 78
  • the two sections 23 a and 23 b of the third signal line 23 are electrically connected or bridged to each other by the bridge 97 made between contact holes 79 and 80 .
  • a first insulating film 30 is formed on the first through fifth vertical signal lines 21 through 25 , and the shift register wiring 61 extends on the first insulating film 30 .
  • the second vertical signal line 22 and the third vertical signal line 23 are not formed under regions of the shift register wiring 61 so that the second signal line 22 and the third signal line 23 are not directly overlapped with the shift register wiring 61
  • a second insulating film 70 is formed on the first insulating film 30 and on the shift register wiring 61 .
  • the sixth connection line 91 , the ( 7 - 1 ) th connection line 96 and the ( 8 - 1 ) th connection line 97 are formed on the second insulating film 70 .
  • the first insulating film 30 and the second insulating film 70 include contact holes 71 , 72 , 77 , 78 , 79 and 80 exposing the first through third signal lines 21 through 23 and the shift register wiring 61 .
  • the respective two sections 22 a and 22 b of the second signal line 22 and the respective two sections 23 a and 23 b of the third signal line 23 are connected (bridged to each other) by the ( 7 - 1 ) th connection line 96 and the ( 8 - 1 ) th connection line 97 , respectively.
  • the ( 7 - 1 ) th connection line 96 and the ( 8 - 1 ) th connection line 97 may be made of ITO or IZO
  • the shift register wiring 61 is extended to and connected to the first signal line 21 .
  • a signal line located under the extended shift register wiring 61 is divided into two spaced apart sections (fork tongs) where the spacing is overlapped by the shift register wiring 61 , and the two sections are connected to each other (bridged) by a connection line formed on the shift register wiring 61 .
  • non-grounded vertical signal line e.g., 22 or 23
  • static electricity that may flow into the gate-line driver circuit 400 by way of one of the non-grounded vertical signal lines does not dissipate its energy by burning out the signal line or the shift register wiring 61 but instead does so more preferentially by burning out the sacrificial fuse provided by one of the electrostatic bridge conductors or by dissipated itself into the wide conductive region provided by the outermost and first vertical signal line 21 .
  • the shift register wiring 61 and the main vertical connection lines are prevented from being burned by the static electricity.
  • a gate driver circuit is thus structured such that its elements are prevented from being burned by static electricity which might flow into the gate driver circuit in the process of forming (e.g., assembling) the Liquid Crystal Display (LCD) device.
  • LCD Liquid Crystal Display
  • an LCD device includes a gate driver circuit formed on a substrate and structured to prevent its active elements and/or the vertical signal lines (e.g., 22 - 25 ) that connect to the gate driver circuit from being burned by static electricity that may flow into the LCD device from activities occurring in the manufacturing facilities or elsewhere. Accordingly, productivity can be improved, and costs are reduced.
  • a gate driver circuit formed on a substrate and structured to prevent its active elements and/or the vertical signal lines (e.g., 22 - 25 ) that connect to the gate driver circuit from being burned by static electricity that may flow into the LCD device from activities occurring in the manufacturing facilities or elsewhere. Accordingly, productivity can be improved, and costs are reduced.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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US10878745B2 (en) * 2019-05-28 2020-12-29 Samsung Display Co., Ltd. Scan driver and display device including the same
EP3796077A4 (en) * 2018-05-14 2022-05-04 Boe Technology Group Co., Ltd. NETWORK SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE
US11436991B2 (en) * 2020-07-10 2022-09-06 Samsung Display Co., Ltd. Display device including an embedded gate driving circuit
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CN103943054B (zh) * 2014-01-27 2016-07-13 上海中航光电子有限公司 栅极驱动电路、tft阵列基板、显示面板及显示装置
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CN105448259B (zh) * 2015-12-25 2018-03-30 上海中航光电子有限公司 栅极驱动器以及显示面板
CN107134264B (zh) * 2016-02-26 2020-08-14 瀚宇彩晶股份有限公司 驱动电路和显示装置
CN107799579B (zh) * 2017-11-29 2024-02-02 京东方科技集团股份有限公司 用于有机发光显示器件的背板及其制备方法、显示装置
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US20160189646A1 (en) * 2014-12-31 2016-06-30 Lg Display Co., Ltd. Gate driver, display device with the same and driving method thereof
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US10878745B2 (en) * 2019-05-28 2020-12-29 Samsung Display Co., Ltd. Scan driver and display device including the same
US11436991B2 (en) * 2020-07-10 2022-09-06 Samsung Display Co., Ltd. Display device including an embedded gate driving circuit

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KR20120040918A (ko) 2012-04-30
US20140347349A1 (en) 2014-11-27
US9275593B2 (en) 2016-03-01

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