US20110025898A1 - Cmos active pixel with very high functional dynamics - Google Patents

Cmos active pixel with very high functional dynamics Download PDF

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Publication number
US20110025898A1
US20110025898A1 US12/674,393 US67439308A US2011025898A1 US 20110025898 A1 US20110025898 A1 US 20110025898A1 US 67439308 A US67439308 A US 67439308A US 2011025898 A1 US2011025898 A1 US 2011025898A1
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transistor
photodiode
voltage
active pixel
cmos type
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US12/674,393
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English (en)
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Yang Ni
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New Imaging Technologies SAS
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New Imaging Technologies SAS
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Publication of US20110025898A1 publication Critical patent/US20110025898A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
    • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor

Definitions

  • the invention relates to CMOS (Complementary Metal Oxide Semiconductor) integration technology which applies a family of electronic components with low electric consumption.
  • CMOS Complementary Metal Oxide Semiconductor
  • the invention in particular relates to CMOS pixels.
  • CMOS integration technology it is possible to make chips for monolithic cameras with good resolution and a reasonable image quality.
  • monolithic cameras are mainly intended for mobile devices such as mobile telephones, personal digital assistants (PDAs), or portable computers.
  • PDAs personal digital assistants
  • the images taken by these cameras are essentially used for viewing on a screen or on Internet.
  • a second difficulty lies in the extent and rate of variation of the light in a dynamic scene.
  • the automatic exposure control system produced by a conventional camera cannot suitably respond to this and therefore produces total or partial saturations.
  • Document EP1354360 describes an active pixel structure with a logarithmic response based on utilizing a photodiode in the photovoltaic regime.
  • a photodiode In the field of standard CMOS technology, a photodiode is generally formed with a PN junction with N diffusion into a substrate of type P. In the photovoltaic operating mode, this photodiode generates a negative voltage in an open circuit, the absolute value of which is proportional to the logarithm of the illumination level of the photodiode. With a switch, it is possible to generate a short circuit in this photodiode in order to simulate the darkness condition in the presence of normal illumination. By reading the difference between the voltage generated by the photodiode in an open circuit and that in a short circuit, it is possible to suppress the additive offset noises in the read-out chain and to thereby obtain a clean image.
  • Prototype circuits implementing the structure of the pixel described in document EP1354360 have provided very high functional dynamics and satisfactory image quality. Nevertheless, this pixel structure still suffers from a certain number of deficiencies.
  • the photodiode only operates in the photovoltaic mode. Now, because of strong logarithmic compression, this operating mode generates an output signal of very low amplitude, thereby limiting the signal-to-noise ratio which may be obtained in the case of diurnal illumination.
  • the short-circuit switching transistor has some residual conductivity during its disabling. This phenomenon becomes critical in a creation of submicron CMOS technology.
  • document EP1354360 describes an active pixel structure utilizing the logarithmic area, this is not the same for the majority of the existing active pixels, which on the contrary utilize the linear area of the variation of the voltage on a photodiode after its reset.
  • the reason for this is that the operation of a photodiode in the mixed or logarithmic portion is supposed to pose photoelectric problems within an array, therefore, a photodiode is generally prevented from entering these areas.
  • An object of the invention is to provide at least one pixel structure with very high functional dynamics, which not only has a large physical compactness but also allows significant improvement of the signal-to-noise ratio.
  • an active pixel structure of the CMOS type comprising at least one photodiode, characterized in that it includes means for reading out a voltage of any polarity in the time-dependent variation phase of the photodiode during exposure.
  • the structure includes at least one of the following features:
  • a method for operating a pixel according to the invention comprises the steps consisting of: resetting a photodiode, before taking shots, to an initial voltage V by means of a zero-resetting signal (RAZ) which enables the reset transistor; disabling the reset transistor and letting the photodiode vary under an illumination during the exposure; performing a first read-out at the end of the exposure by means of a selection signal SEL; and performing a second read-out during or suddenly after re-enabling of the reset transistor.
  • RZA zero-resetting signal
  • the method for operating a pixel utilizes the following areas of the variation of the voltage on the photodiode after its reset:
  • FIG. 1 a is a view of a photoreceiver with a photodiode in a photovoltaic mode according to the prior art
  • FIG. 1 b is a view of a structure of a pixel provided with a photoreceiver according to the prior art
  • FIG. 2 is a curve illustrating the variation of the voltage on a photodiode after its reset
  • FIGS. 3 a and 3 b are two views of a pixel structure according to a first embodiment of the invention.
  • FIGS. 4 a and 4 b are two time diagrams showing the operation of a pixel according to the first and a second embodiment of the invention, respectively,
  • FIG. 5 is a view of a pixel structure according to a second embodiment of the invention.
  • FIGS. 6 a , 6 b , 6 c , 6 d and 6 e are five views of a pixel structure according to five alternatives of the second embodiment of the invention.
  • FIGS. 7 a and 7 b are two views of a pixel structure according to two other alternatives of the second embodiment of the invention.
  • FIG. 8 a is a view of a pixel structure according to another alternative of the second embodiment of the invention.
  • FIG. 8 b is a partial view of a pixel structure according to another alternative of the second embodiment of the invention.
  • FIG. 9 is a view of a typical transistor
  • FIG. 10 is a view of an array configuration of a pixel structure.
  • a pixel structure 1 includes:
  • the depleted N type transistor has a negative threshold voltage T S —the threshold voltage T S being the voltage at one of the poles of the transistor called the “gate” G, the two other poles being the “source” S and the “drain” D—which allows it to be kept “conducting” when a voltage greater than T S , and in particular a negative voltage belonging to the interval [T S ; 0], is applied between the gate G and the source S.
  • T S negative threshold voltage
  • a threshold voltage T S of the order of ⁇ 1 V allows the voltage of the photodiode 10 to be read out over the whole range of its variation over time and it may be translated into a purely positive voltage by means of such a depleted transistor, which may be utilized by conventional read-out circuits.
  • the photodiode 10 is used with reverse bias. Before taking shots, a generator, either external or internal to the pixel produces a reverse initial voltage V init powering the reset transistor T 1 , which sets up this initial reverse voltage V init in the photodiode 10 . This operation is called “initializing or resetting to zero (RAZ) the photodiode”.
  • the initial voltage V init is programmable.
  • the initial voltage V init is programmable.
  • it allows determination of the range of use of the photodiode 10 , which either starts in the linear area, or in the mixed area or in the logarithmic area (cf. FIG. 2 ), depending on the luminosity to which it is subject and on the conditions of its use which follows this reset.
  • the transistor T 1 is disabled, so that a photoelectric current I ⁇ induced within the photodiode 10 then illuminated, gradually discharges the voltage into the photodiode 10 .
  • a variation between the initial voltage in the photodiode 10 and a voltage obtained at the end of the exposure forms the output signal of the pixel 1 .
  • the voltage curve of the photodiode 10 is visible in FIG. 2 .
  • the time-dependent variation range of a photodiode is divided into two main areas, defined as follows.
  • the photodiode remains under reverse bias. That is to say that the voltage on the photodiode remains positive:
  • V PD V init - I ⁇ * T exp C PD > 0
  • C PD is the junction capacitance of the photodiode and T exp is the exposure time. Therefore, it is stated in this case that the photodiode is operating in the linear area.
  • V PD - kT q ⁇ ln ⁇ ( I ⁇ I S + 1 ) ⁇ 0
  • k is the Boltzmann constant
  • q is the elementary charge
  • T is the absolute operating temperature of the photodiode
  • I S represents a reverse current also called the saturation current of the junction of the photodiode, observed when a diode is reverse-biased in the total absence of light.
  • the voltage on the photodiode becomes proportional to the logarithm of the light intensity. It is stated in this case that the photodiode operates in the logarithmic area.
  • V PD V init - I ⁇ * T exp C PD > 0
  • V PD - kT q ⁇ ln ⁇ ( I ⁇ I S + 1 ) ⁇ 0 ⁇ ⁇ if
  • the photodiode enters the logarithmic area.
  • a MOS follower 30 also called a buffer amplifier—is connected between the reset transistor T 1 and the photodiode 10 . It includes means for reading out a voltage of any polarity in the photodiode 10 . These read-out means comprise a read-out depleted NMOS transistor T 2 .
  • the follower 30 also includes a transistor T 3 having a charging function included in the pixel 1 . Alternatively, the transistor 13 is positioned outside the pixel 1 . The configuration which places the charge T 3 in the pixel 1 is however more stable than the one which places it outside the pixel 1 .
  • the read-out depleted NMOS transistor T 2 is used here, over the whole range where it is conducting, in order to translate the electric level of the voltage read on the photodiode 10 so as to obtain a voltage forming an output signal, which may be utilized by the circuit using this output signal.
  • the follower 30 is selectively connected onto the bus 40 with a fourth transistor T 4 , called a selection transistor.
  • the latter may be enabled by a selection signal SEL, arriving on the gate of the transistor T 4 .
  • This selection mechanism allows access to a determined pixel in a pixel array.
  • a first read-out L 1 is achieved by means of this SEL signal. This read-out gives the final voltage in the photodiode 10 plus an offset component V offset of the translation, provided by the voltage follower 30 .
  • the reset transistor T 1 is re-enabled.
  • a second read-out L 2 is then made during or immediately after the end of the re-enabling of the reset transistor T 1 .
  • This read-out L 2 gives the initial voltage in the photodiode 10 added to the offset component V offset of the voltage follower 30 .
  • FIG. 4 a gives a time diagram of the operation of the pixel 1 .
  • the pixel structure 1 only uses a single type of transistor 20 . This suppresses the need for an insulation case, required upon the simultaneous presence of NMOS and PMOS transistors within a same pixel 1 , and provides a significant gain in space within the pixel 1 . By saving a useful surface area, it is possible not to reduce the photodiode 10 and therefore to gain in photoelectric performance.
  • Another object of the invention is to provide at least one pixel structure which may utilize the whole range of variation of a photodiode, which means the possibility of utilizing in addition to the linear area, the mixed and logarithmic portions for which the voltage on the photodiode becomes negative.
  • a compact pixel using a single type of transistors can normally only read a positive voltage of the illuminated photodiode.
  • Another object of the invention is therefore to provide at least one pixel structure enabling by using a single type of transistor the utilization or all the variation areas of the photodiode.
  • a pixel structure 1 includes:
  • This second pixel structure 1 proposes the utilization of the complete range of the variation of a photodiode 10 without using any depleted NMOS transistor for T 2 .
  • the operation of the pixel 1 is identical with that of the first structure: the photodiode 10 is reset to a reference voltage by enabling the transistor T 1 , and then when the transistor T 1 is disabled, the photodiode 10 is discharged during the exposure period, at the end of which two read-outs of the voltage of the photodiode 10 are performed, one before the re-enabling of the transistor T 1 and the other one after or during the re-enabling of the transistor T 1 . A subtraction between the values of these two read-outs gives a clean image signal since it is free of the offset of the voltage follower 30 within the pixel 1 .
  • the difference relatively to the first pixel structure 1 lies in the fact that the cathode of the photodiode 10 is coupled, not with a read-out depleted NMOS transistor T 2 , but with a normal read-out NMOS type transistor T 2 with a positive threshold voltage T S , by means of a capacitive coupling capacitor 50 .
  • the voltage at the input of the read-out transistor T 2 is thus the result of the sum between the voltage of the photodiode 10 and the voltage of the capacitor 50 mounted in series. It is possible, depending on the amount and on the polarity of the charges within the capacitor 50 , to translate the voltage of the photodiode 10 into a range which may be handled by the read-out transistor T 2 .
  • a first method illustrated in FIGS. 6 a - 6 e consists of connecting the input (gate) of the read-out transistor T 2 to a positive voltage with a value greater than the threshold voltage T S of the read-out transistor T 2 through a resistor 60 consisting of an NMOS transistor TR and connected to a positive voltage source 70 .
  • the resistor 60 is of a determined value R such that a time constant RC, wherein C is the capacitance of the coupling capacitor 50 , is, for example, ten times greater than the time interval existing between two read-outs L 1 , L 2 at the end of the exposure. In this way, there is practically no loss of charge on the capacitor 50 between the two read-outs and the image signal is then reliably retransmitted to the input of the read-out transistor T 2 .
  • the transistor TR is powered at its gate by a voltage source 72 while its drain is connected to the voltage source 70 .
  • Both voltage sources 70 and 72 may be of the same voltage or of different voltages.
  • the first read-out measures the voltage at the output of the follower 30 , this voltage being substantially equal to V DD ⁇ V th wherein V DD is the power supply voltage 70 and V th , is the threshold voltage of the transistor TR.
  • the output of the follower 30 is expressed by: (V DD ⁇ V th ) ⁇ V offset .
  • the value of this read-out is subsequently stored in a memory, either an analog or digital memory, which may either be found on a chip including pixels or outside the latter.
  • the second read-out is accomplished in the same way as for the first embodiment of the invention: by enabling the RAZ signal.
  • the voltage on the photodiode 10 is again reset to V init . This causes a change in voltage on the photodiode 10 which is either equal to
  • C T represents the equivalent parasitic capacitance at the input of the follower 30 and C is the capacitance of the capacitor 50 .
  • the voltage change at the output of the follower 30 after re-enabling of the reset transistor T 1 may be written in the following way:
  • ⁇ represents the gain of the follower 30 .
  • a read-out of this value is performed, but this value is subtracted from the value of the first read-out: (V DD ⁇ V th ) ⁇ V offset . In this way, an image signal is obtained:
  • the resistor 60 is made in thin layer(s) after forming the integrated transistors 20 .
  • a second method illustrated in FIGS. 7 a and 7 b consists of using point-like conductivity within an electric insulator. This point-like conductivity may come from different physical phenomena:
  • the capacitor 50 may be made with a transistor 20 , for which the drain D or the source S or both coincide with the N diffusion of the photodiode 10 (see FIG. 8 b ).
  • the negative voltage of the photodiode 10 may cause involuntary conduction of the reset transistor T 1 , causing fixed or variable noises on the acquired image and thereby strongly reducing the quality of the image.
  • a negative voltage is applied to the gate G of the transistor T 1 during the exposure period. This negative voltage suppresses the parasitic conduction of transistor T 1 so as to disable it. It may be provided by an external power supply source or by a generator internal to the CMOS sensor comprising the pixel 1 .
  • FIG. 10 An incorporation of the pixel of the invention in an array configuration of two dimensions with (m+1) lines and (n+1) columns is illustrated in FIG. 10 .
  • This figure illustrates in a non-exclusive way a particular embodiment compliant with the description of the pixel structure 1 of the invention, from which other designs may easily be inferred by one skilled in the art.
  • a line of pixels is selected by applying an address Y i to an addressing circuit Y.
  • An output of pixels of the line Y i is connected onto a column read-out bus COL.
  • the output of this line is sampled and stored in an analog memory MA 1 by enabling the signal L 1 .
  • a signal RAZ_ G is then enabled, also causing the enabling for resetting to zero the pixels of the selected line Y i .
  • the output of this line is sampled in a second analog memory MA 2 by the signal L 2 .
  • an address X is applied to an addressing circuit X.
  • the contents of the analog memories MA 1 and MA 2 are directed towards a differential amplifier via the busses OB 1 and OB 2 . This differential amplifier produces a difference which allows suppression of the offset errors in the read-out.
  • the transistors T 1 , T 2 , T 3 , T 4 and TR are of the PMOS type.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
US12/674,393 2007-08-28 2008-08-27 Cmos active pixel with very high functional dynamics Abandoned US20110025898A1 (en)

Applications Claiming Priority (3)

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FR0757225A FR2920590B1 (fr) 2007-08-28 2007-08-28 Pixel actif cmos a tres grande dynamique de fonctionnement
FR0757225 2007-08-28
PCT/EP2008/061261 WO2009027449A1 (fr) 2007-08-28 2008-08-27 Pixel actif cmos a tres grande dynamique de fonctionnement

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JP2013211840A (ja) * 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd イメージセンサ、カメラ、監視システムおよびイメージセンサの駆動方法
WO2014064274A1 (fr) 2012-10-26 2014-05-01 New Imaging Technologies Structure d'un pixel actif de type cmos
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JP6743011B2 (ja) * 2014-12-11 2020-08-19 ソニーセミコンダクタソリューションズ株式会社 撮像装置、駆動方法、電子機器
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CN101796810B (zh) 2013-12-25
EP2186318B1 (de) 2011-11-16
FR2920590B1 (fr) 2009-11-20
FR2920590A1 (fr) 2009-03-06
EP2186318A1 (de) 2010-05-19
US20150207470A1 (en) 2015-07-23
US9768742B2 (en) 2017-09-19
ATE534237T1 (de) 2011-12-15

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