US20090267122A1 - Semiconductor device and method of manufacturing the semiconductor device - Google Patents

Semiconductor device and method of manufacturing the semiconductor device Download PDF

Info

Publication number
US20090267122A1
US20090267122A1 US12/385,868 US38586809A US2009267122A1 US 20090267122 A1 US20090267122 A1 US 20090267122A1 US 38586809 A US38586809 A US 38586809A US 2009267122 A1 US2009267122 A1 US 2009267122A1
Authority
US
United States
Prior art keywords
film
semiconductor device
ferroelectric
manufacturing
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/385,868
Other languages
English (en)
Inventor
Tadahiro Ohmi
Ichiro Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tohoku University NUC
Foundation for Advancement of International Science
Original Assignee
Tohoku University NUC
Foundation for Advancement of International Science
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku University NUC, Foundation for Advancement of International Science filed Critical Tohoku University NUC
Assigned to FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY reassignment FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OHMI, TADAHIRO, TAKAHASHI, ICHIRO
Publication of US20090267122A1 publication Critical patent/US20090267122A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02Pretreatment of the material to be coated
    • C23C14/024Deposition of sublayers, e.g. to promote adhesion of the coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08Oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58After-treatment
    • C23C14/5826Treatment with charged particles
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G7/00Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
    • H01G7/06Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192Microwave generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32715Workpiece holder
    • H01J37/32724Temperature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/60Capacitors
    • H10D1/68Capacitors having no potential barriers
    • H10D1/682Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/701IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/033Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/20Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
    • H01J2237/2001Maintaining constant desired temperature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer

Definitions

  • the present invention relates to a ferroelectric film, a semiconductor device with a ferroelectric film, and a method of manufacturing the ferroelectric film and the semiconductor device.
  • a ferroelectric memory As a nonvolatile semiconductor memory, a ferroelectric memory is known, which makes use of spontaneous polarization of a ferroelectric.
  • the ferroelectric memory stores two stable electric polarization states generated by application of an electric field by associating them with “0” and “1”.
  • the ferroelectric memory is advantageous for its lower power consumption and higher operation speed than other nonvolatile memories.
  • ferroelectric memory comprises a ferroelectric film formed in a capacitor portion.
  • FET field-effect transistor
  • MFIS-FET field-effect transistor
  • MFMIS-FET field-effect transistor
  • Pb(Zr 1-x Ti x )O 3 (0 ⁇ x ⁇ 1) (PZT), SrBi 2 Ta 2 O 9 (SBT), or the like is conventionally used, but in recent years, attention is given to Sr 2 (Ta 1-x Nb x ) 2 O 7 (0 ⁇ x ⁇ 1) (STN) which has a relatively low relative dielectric constant and is hard to be deteriorated in the hydrogen atmosphere.
  • an STN ferroelectric film is formed, as described in JP-A-10-326872 (Patent Document 1), by a sol-gel process in which a precursor solution of a ferroelectric material is applied and dried to remove organic composition, and then heated to be crystallized.
  • STN is formed of Ta and Nb which have high ionization energy, and hence extremely high energy is necessary for the oxidation of Ta and Nb atoms.
  • the reasons that the above-mentioned sol-gel process is adopted are that an oxygen component is contained in the precursor from the first and hence relatively small amount of oxidation energy is required and that an STN film composition is easily matched.
  • a ferroelectric film formed by the sol-gel process is rather thick and low in coercive field to be used in a memory. This is why sputtering as described in JP-A-2004-265915 (Patent Document 2) is employed in some cases as a method of forming an STN ferroelectric film.
  • a ferroelectric film is formed first on a surface of a base by a sputtering process then heated and subjected to radical oxidation, to thereby obtain STN.
  • the crystallization of STN requires generating STN on a base that is a crystalline substance.
  • an element Pt comprising a lattice constant close to that of STN has conventionally been used as a material of the base as described in, for example, Ichiro Takahashi, “A Research on Techniques of Forming a Ferroelectric STN Thin Film and Its Application to Devices (Summary of Thesis (DR) and Summary of Examination Result)”, Tohoku University, Dec. 15, 2006, p. 390-394 (Non-Patent Document 1).
  • Pt is not an oxide and raises a problem in that the loss of oxygen from STN during the crystallization of STN creates an oxygen-deficient crystal phase.
  • Non-Patent Document 1 Alternative material for the base has been proposed in which IrO 2 is used as a material that comprises lattice information approximate to that of STN and that contains oxygen (Non-Patent Document 1, Patent Document 2).
  • a structure using IrO 2 as described in Patent Document 2 is a useful structure in terms of accelerating the crystallization of STN while preventing oxygen deficiency.
  • a drawback is that the grain size of the crystallized STN in the above-mentioned structure is as large as 1 ⁇ m or more and is not suitable for use as a semiconductor memory.
  • the coercive field of the obtained STN is on the order of several tens V/cm, which makes the above-mentioned structure impractical as a semiconductor memory in terms of stable operation.
  • the object of the present invention is to provide a ferroelectric film that enables a device to operate stably and that adheres very closely to a base.
  • a ferroelectric film comprising as a film material a ferroelectric material containing Sr, Ta, and Nb as its main components, the ferroelectric film being formed on a base that contains yttrium oxide.
  • a method of manufacturing a ferroelectric film comprising: forming a ferroelectric film containing Sr, Ta, and Nb as its main components on a substrate that contains yttrium oxide.
  • a semiconductor device comprising: a ferroelectric film that is formed from a ferroelectric material containing Sr, Ta, and Nb as its main components, on a base film that contains yttrium oxide; and a conductive electrode placed directly on or indirectly above the ferroelectric film.
  • a method of manufacturing a semiconductor device comprising: forming a ferroelectric film containing Sr, Ta, and Nb as its main components on a base film that contains yttrium oxide.
  • a ferroelectric device comprising: a base that contains yttrium oxide; and a ferroelectric film formed on the base from a ferroelectric material containing Sr, Ta, and Nb as its main components.
  • the present invention can provide a ferroelectric film that enables a device to operate stably and that adheres very closely to a base, as well as a semiconductor device using the ferroelectric film, methods of manufacturing the ferroelectric film and the semiconductor device, and a practical ferroelectric device using the ferroelectric film.
  • FIG. 1 is a cross sectional view of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 shows a sputtering apparatus, with a processing container, a casing, an electrode, a target, and a protective member illustrated in a cross sectional view;
  • FIG. 3 shows an apparatus for radical-oxidation by plasma, with a processing container, a dielectric window, an antenna member, and a shutter illustrated in a cross sectional view;
  • FIG. 4 shows an annealing apparatus (furnace), with a casing, a flange, and a heater illustrated in a cross sectional view;
  • FIG. 5 is a cross sectional view of the annealing apparatus (furnace) of FIG. 3 viewed from the front, with a substrate-to-be-processed and a mounting table illustrated in a side view;
  • FIG. 6 is a cross sectional view of a substrate-to-be-processed according to the first embodiment
  • FIG. 7 is a cross sectional view of the substrate-to-be-processed where a ferroelectric film (STN film) has been formed on the yttrium oxide film according to the first embodiment;
  • STN film ferroelectric film
  • FIG. 8 is a cross sectional view of the substrate-to-be-processed where oxygen radicals have been introduced into the ferroelectric film (STN film) according to the first embodiment;
  • FIG. 9 is a view illustrating a modified example of FIG. 8 ;
  • FIG. 10 is an electron microscopic picture of the ferroelectric film (STN film) that is formed on the yttrium oxide film;
  • FIG. 11 is a diagram illustrating results of an X-ray diffraction (XRD) analysis on the ferroelectric film (STN film) that is formed on the yttrium oxide film according to the first embodiment;
  • XRD X-ray diffraction
  • FIG. 12 is a diagram illustrating CV (Capacitance Voltage) characteristics of the ferroelectric film (STN film) that is formed on the yttrium oxide film according to the first embodiment;
  • FIG. 13 is a cross sectional view of a ferroelectric memory:
  • FIG. 14 is a cross sectional view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 15 is a cross sectional view of a substrate-to-be-processed that is obtained by forming an SiN film on a substrate according to the second embodiment.
  • FIG. 16 is a cross sectional view of the substrate-to-be-processed where the SiN film has been formed on the substrate and an yttrium oxide film has been formed on the SiN film according to the second embodiment.
  • a ferroelectric memory 201 (field-effect transistor type ferroelectric memory) is structured to comprise, for example, a semiconductor substrate 202 , an insulator layer 203 , which is formed on the semiconductor substrate 202 ; a ferroelectric layer 204 , which is formed on the insulator layer 203 , and an electrode layer 205 , which is formed on the ferroelectric layer 204 .
  • a source region 202 a is formed at one end of the insulator layer 203 on a surface of the semiconductor substrate 202 , and a drain region 202 b is formed at the other end of the insulator layer 203 .
  • the ferroelectric layer 204 is polarized by, for example, applying a positive or negative voltage of a certain level or higher to the electrode layer 205 , and the resultant polarized state is maintained even after the voltage is removed.
  • ferroelectric memory 201 is used as a memory.
  • FIG. 1 Described next with reference to FIG. 1 is the structure of a semiconductor device 71 according to the present invention which can be used as the ferroelectric memory 201 .
  • the semiconductor device 71 comprises a semiconductor substrate 55 , which is made of Si or the like, an insulator 56 , which is provided on the substrate 55 , an yttrium oxide film 66 , which is provided on the insulator 56 , a ferroelectric film (STN film) 57 , which is provided on the yttrium oxide film 66 , and an upper electrode 62 (conductive electrode), which is provided on the ferroelectric film (STN film) 57 .
  • STN film ferroelectric film
  • the upper electrode 62 can be placed directly on or indirectly above the ferroelectric film (STN film) 57 .
  • the components between the electrode 62 and the substrate 55 constitute a ferroelectric capacitor.
  • the substrate 55 which is a semiconductor substrate such as Si, may be an insulating film such as a silicon oxide film, a metal oxide film, or a conductive film.
  • the insulator 56 is made of an insulating material such as silicon oxide (SiO 2 ).
  • the yttrium oxide film 66 is a film that comprises crystals of yttrium oxide (Y 2 O 3 ), and serves as a base when the ferroelectric film (STN film) 57 is crystallized.
  • yttrium oxide contains oxygen and that the lattice information of yttrium oxide is approximate to that of crystals of the ferroelectric film (STN film) 57 .
  • ferroelectric film (STN film) 57 adheres more closely to the yttrium oxide film 66 than to an IrO 2 film.
  • crystallizing STN on the yttrium oxide film 66 gives the ferroelectric film (STN film) 57 a coercive field of 200 kV/cm or more while avoiding oxygen deficiency (details thereof are described later).
  • the resultant ferroelectric film (STN film) 57 also comprises as fine a crystal grain size as 100 nm, or smaller.
  • yttrium oxide is less expensive than IrO 2 or Pt, which makes yttrium oxide advantageous in terms of cost as well.
  • the material of the ferroelectric film (STN film) 57 is one containing Sr, Ta, and Nb.
  • the specific composition of the ferroelectric film (STN film) 57 is, for example, Sr 2 (Ta 1-x Nb x ) 2 O 7 (0 ⁇ x ⁇ 1) (STN).
  • the upper electrode 62 can be any conductor, for example, Al.
  • the semiconductor device 71 can be used as the ferroelectric memory 201 .
  • the substrate 55 corresponds to the semiconductor substrate 202 of the ferroelectric memory 201 , and a gate insulating film (insulator 56 ) such as a silicon oxide (SiO 2 ) film is formed as the insulator layer 203 on a channel region of the semiconductor substrate 202 .
  • the yttrium oxide film 66 and the ferroelectric film (STN film) 57 as the ferroelectric layer 204 are then formed on the insulator 56 , and the upper electrode 62 is provided as the electrode layer 205 .
  • the upper electrode 62 works as a gate of the field effect transistor and the ferroelectric film (STN film) 57 works as a part of a gate insulating film (insulator 56 )
  • the semiconductor device 71 when used as the ferroelectric memory 201 , can comprise a 1Tr structure, a 1T-1C structure, a 2T-2C structure, a 1T-2C structure, or other structures.
  • the semiconductor device 71 according to this embodiment can be manufactured by such methods as sputtering, application (sol-gel process described above), chemical vapor deposition (MOCVD, for example performed in plasma) using an organic metal compound, and a mist process in which an organometallic compound liquid is turned into a mist to be introduced onto the substrate (letting the organometallic compound react in plasma).
  • the semiconductor device 71 is obtained by first forming a ferroelectric film on a surface of a base through a sputtering process (step of forming a ferroelectric film), then subjecting the ferroelectric film to radical oxidation (step of oxidizing the ferroelectric film), and heating the ferroelectric film (step of heating the ferroelectric film),
  • the structure of a sputtering apparatus 101 is described first with reference to FIG. 2 .
  • the sputtering apparatus 101 comprises, for example, a cylindrical processing container 1 , which comprises an open top and a closed bottom, and a hollow, cylindrical casing 2 , which is installed such that the top of the processing container 1 can be closed.
  • a processing chamber 3 is formed.
  • a mounting table 4 for bearing a substrate-to-be-processed 10 is provided inside the processing chamber 3 .
  • the substrate-to-be-processed 10 is a semiconductor wafer or the like on which a ferroelectric film is formed.
  • An electrode 5 is embedded in the processing container 1 across from the mounting table 4 .
  • the electrode 5 is structured such that a voltage can be applied from a high-frequency power source 6 , which is placed outside the processing container 1 .
  • the electrode 5 is supported by a protective member 17 , and a target 7 is placed on the electrode 5 which faces the mounting table 4 .
  • the material of the target 7 is determined by what type of ferroelectric film is to be formed on the substrate-to-be-processed 10 .
  • a processing gas introducing port 8 is provided, and processing gas supply pipes 11 a , 11 b , and 11 c which lead to a processing gas supply source 9 are connected to the processing gas introducing port 8 .
  • a valve 12 and a mass flow controller 13 are provided to the processing gas supply pipes 11 a , 11 b , and 11 c, and the processing gas supply pipe 11 c is connected through a wall of the processing container 1 to the processing gas introducing port 8 of the processing chamber 3 .
  • processing gas at a predetermined pressure can be supplied into the processing chamber 3 .
  • the processing gas supply source 9 in this embodiment is connected to sources that separately supply rare gas such as Ar gas, Kr gas, and Xe gas, and oxygen gas as the processing gas.
  • an exhaust port 14 to exhaust the processing chamber 3 is provided in a side surface of the other end of the processing container 1 facing the above-mentioned processing gas introducing port 8 .
  • An exhaust pipe 16 which leads to an exhauster such as a vacuum pump 15 is connected to the exhaust port 14 .
  • the pressure in the processing chamber 3 for example, can be reduced to a predetermined pressure by the exhaust from the exhaust port 14 .
  • the processing gas supplied into the processing chamber 3 is turned into plasma by the high-frequency power source of the electrode, and rare gas ions are produced.
  • the potential of the electrode 5 By maintaining the potential of the electrode 5 at a negative potential, positively charged rare gas ions fly toward the target 7 side and collide therewith.
  • target species jump out of the target 7 .
  • the protective member 17 formed of the same component material as that of the target 7 is attached to a portion with which the rare gas ions may collide, for example, a periphery of the target 7 (at least a portion of an inner surface around the target 7 ).
  • oxygen radicals are produced in the processing chamber 3 .
  • the target species which have jumped out of the target 7 are oxidized by the oxygen radicals and deposited on the surface of a substrate-to-be-processed 10 .
  • a portion exposed to the oxygen radicals in the processing chamber 3 is provided with a quartz film. By the quartz film, the disappearance of the oxygen radicals is inhibited, and the target species in the processing chamber 3 are oxidized.
  • Described next with reference to FIG. 3 is a plasma process apparatus for introducing oxygen into a ferroelectric film with the use of oxygen radicals.
  • FIG. 3 schematically illustrates a cross sectional view of a plasma process apparatus 103 .
  • the plasma process apparatus 103 comprises a substantially cylindrical processing container 33 , which comprises an opening 32 in its ceiling.
  • the processing container 33 is grounded.
  • a susceptor 34 on which the substrate-to-be-processed 10 is set is installed on the bottom of the processing container 33 .
  • the susceptor 34 comprises a heater 36 inside.
  • An AC power source 35 placed outside the processing container 33 supplies a current with which the heater 36 generates heat, thereby heating the substrate-to-be-processed 10 on the susceptor 34 up to, for example, 500° C. or so.
  • An exhaust port 37 which communicates with an exhauster 38 such as a turbomolecular pump to exhaust the interior of the processing chamber 33 of gas is provided in the bottom of the processing container 33 .
  • a supply port 39 is provided in the ceiling of the processing container 33 which is across the susceptor 34 from the exhaust port 37 .
  • Supply pipes 42 a and 42 b leading to a processing gas supply source 41 are connected to the supply port 39 via a mass flow controller 43 .
  • the processing gas supply source 41 in this embodiment is connected to a source for supplying oxygen gas and a source for supplying krypton (Kr) gas, which is rare gas.
  • Krypton gas may be replaced with another rare gas.
  • a dielectric window 45 made of, for example, quartz glass is installed in the opening 32 of the processing container 33 via an O ring 44 or other types of sealing member that ensures the air-tightness.
  • the dielectric window 45 closes up the processing container 33 , thereby creating a processing space 46 inside the processing container 33 .
  • An antenna member 47 is placed above the dielectric window 45 .
  • a coaxial waveguide 48 is connected to the top of the antenna member 47 .
  • the coaxial waveguide 48 is connected to a microwave feeder 51 , which is placed outside the processing container 33 .
  • the microwave feeder 51 generates microwaves comprising a frequency of, for example, 2.45 GHz.
  • the microwaves propagate through the coaxial waveguide 48 to the antenna member 47 , and are emitted into the processing space 46 through the dielectric window 45 .
  • a shutter 53 is provided in a side of the processing container 33 in order to open and close a carry-in/out port 52 through which the substrate-to-be-processed 10 is loaded into the processing container 33 .
  • the annealing apparatus (furnace) 102 comprises, for example, a substantially cylindrical casing 18 comprising an axis running in the horizontal direction as illustrated in FIG. 4 .
  • a flange 19 closes each side surface of the casing 18 in the axial direction (each end of the horizontal casing 18 ), thereby creating a closed processing chamber 20 within the casing 18 .
  • a mounting plate 21 on which the substrate-to-be-processed 10 is set is provided in the middle part of the interior of the casing 18 .
  • a cylindrical part (wall) which constitutes a side surface of the casing 18 in the radial direction is formed thick and, as illustrated in FIG. 5 , heaters 22 are installed along the entire circumference of the cylindrical wall in order to heat the cylindrical wall uniformly.
  • the substrate-to-be-processed 10 on the mounting plate 21 is thus heated from 360-degree directions evenly.
  • the heaters 22 are connected to a power source 23 , which is set outside the casing 18 , and use power supplied from the power source 23 to generate heat.
  • the power source 23 is controlled by, for example, a temperature controller 28 , which controls the heater temperature by varying the power output of the power source 23 .
  • the mounting plate 21 is provided with a thermocouple as a temperature sensor, and the temperature read by the thermocouple is output to the temperature controller.
  • the temperature controller adjusts the heater temperature based on the temperature reading.
  • What is denoted by reference numeral 27 is a quartz tube.
  • a processing gas introducing port 24 is opened at one end of the casing 18 .
  • Processing gas supply pipes 26 a , 26 b , and 26 c leading to a processing gas supply source 25 are connected to the processing gas introducing port 24 .
  • the processing gas supply pipes 26 a , 26 b , and 26 c are provided with a valve 12 and a mass flow controller 13 , whereby gas comprising a given pressure is supplied into the processing chamber 20 .
  • the processing gas supply source 25 in this embodiment is connected to sources that separately supply oxygen gas and argon gas as processing gas.
  • Argon gas may be replaced with nitrogen gas.
  • An exhaust port 31 is provided at the other end of the casing 18 , across from the processing gas introducing port 24 .
  • the exhaust port 31 communicates with an exhauster 29 , which is set outside the casing 18 , to exhaust the atmosphere inside the processing chamber 20 .
  • the sputtering apparatus 101 illustrated in FIG. 2 , the plasma process apparatus 103 illustrated in FIG. 3 , and the annealing apparatus 102 illustrated in FIGS. 4 and 5 comprise the structures described above.
  • a method of manufacturing the ferroelectric film 57 (STN film) according to an embodiment of the present invention is described taking as an example a case of manufacturing the semiconductor device 71 as the ferroelectric memory 201 .
  • the substrate-to-be-processed 10 is prepared by forming the insulator 56 and the yttrium oxide film 66 on the substrate 55 , which is a silicon wafer.
  • the yttrium oxide film 66 can be formed by, for example, sputtering in an oxidizing atmosphere, sputtering in an inert gas atmosphere, sputtering in an oxidizing atmosphere, using a sol-gel process, and oxidizing an yttrium oxide film with oxygen radicals.
  • the prepared substrate is transported to the sputtering apparatus 101 and fixed onto the mounting table 4 as illustrated in FIG. 2 .
  • the processing chamber 3 is exhausted of gas through the exhaust port 14 so that the pressure in the processing chamber 3 is reduced to, for example, about 10 ⁇ 7 Pa.
  • Argon gas and oxygen gas are supplied from the processing gas introducing port 8 to fill the processing chamber 3 with argon gas and oxygen gas.
  • the pressure in the processing chamber 3 at this point is, for example, about 4 Pa.
  • a high-frequency voltage comprising a negative potential is applied to the electrode 5 , whereby the gas in the processing chamber 3 is turned into plasma and argon is turned into argon ions by the high-frequency voltage.
  • the argon ions are drawn toward the negative potential electrode 5 and collide with a target 7 at high speed.
  • target species jump out of the target 7 to be oxidized with oxygen radicals, which are generated from oxygen gas in plasma.
  • the ferroelectric film (STN film) 57 is thus formed on the yttrium oxide film 66 as illustrated in FIG. 7 .
  • the deposition of STN for forming the ferroelectric film (STN film) 57 is continued for a given period of time, and then the application of the high-frequency voltage is stopped to end the sputtering process in the sputtering apparatus.
  • the substrate-to-be-processed 10 is brought out of the sputtering apparatus 101 and transported to the plasma process apparatus 103 .
  • the substrate-to-be-processed 10 is loaded thereinto thorough the carry-in/out port 52 , and as illustrated in FIG. 3 , mounted on the susceptor 34 which is maintained, for example, at 400° C.
  • a mixed gas of the oxygen gas and the krypton gas is supplied into the processing space from the supply port 39 , and a mixed gas atmosphere is substituted in the processing space.
  • Gas in the processing space is exhausted from the exhaust pipe 37 , and the pressure in the processing space is reduced to a predetermined pressure, for example, approximately 133 Pa.
  • a microwave is generated by the microwave feeder 51 , and this microwave is propagated to the antenna member 47 .
  • the mixed gas in the processing space is turned into plasma by the microwave, and by oxygen radicals 58 thereby produced in the processing space, oxygen is introduced into the ferroelectric film (STN film) 57 as illustrated in FIG. 8 .
  • oxygen is introduced into the ferroelectric film (STN film) 57 as illustrated in FIG. 8 .
  • a small amount of krypton component is also introduced into the ferroelectric film (STN film) 57 .
  • the oxygen is introduced into the ferroelectric film (STN film) 57 by the oxygen radicals 58 for a predetermined time, the radiation of the microwave from the antenna member 47 is stopped, and the substrate-to-be-processed 10 is brought out of the plasma process apparatus 103 .
  • the substrate-to-be-processed 10 brought out of the plasma process apparatus 103 may be transported back to the sputtering apparatus 101 to receive the sputtering process and the plasma process repeatedly, whereby the ferroelectric film (STN film) 57 may be formed in a plurality of layers 57 a , 57 b . . . and 57 c as illustrated in FIG. 9 .
  • STN film ferroelectric film
  • the total thickness of the ferroelectric films (STN films) 57 a , 57 b . . . , and 57 c is, for example, 1 nm or more and 10 nm or less.
  • the substrate-to-be-processed 10 is transported to the annealing apparatus 102 to be set on the mounting plate 21 comprising a temperature that has been raised to, for example, 900° C. by the heaters 22 as illustrated in FIGS. 4 and 5 .
  • Oxygen gas or argon gas is introduced into the processing chamber 20 from the processing gas introducing port 24 and, at the same time, the processing chamber 20 is exhausted of gas through the exhaust port 31 . In this manner, an air current that flows in the axial direction is created in the processing chamber 20 , thereby substituting the existing atmosphere in the processing chamber 20 with an atmosphere of oxygen gas and argon gas while keeping purging the processing chamber 20 .
  • the substrate-to-be-processed 10 set on the mounting plate 21 which is maintained at 900° C. is heated and the ferroelectric film (STN film) 57 is crystallized through oxidation. Once the ferroelectric film (STN film) 57 is crystallized, the substrate-to-be-processed 10 is taken out of the annealing apparatus 102 and the annealing process is ended.
  • an upper conductive film is formed as the upper electrode 62 on the ferroelectric film (STN film) 57 as illustrated in FIG. 1 .
  • the upper conductive film is formed by, for example, the above-mentioned sputtering process.
  • the underlying ferroelectric film (STN film) 57 is less damaged due to the fact that the collision cross section of Xe is larger than that of Ar, and therefore the recovery annealing which usually needs to be performed can be omitted.
  • the semiconductor device 71 illustrated in FIG. 1 is manufactured through the above-mentioned method. It is preferred that the above-mentioned method is performed without exposing the semiconductor device 71 to outside air during transition from a preceding step.
  • the semiconductor device 71 comprises the substrate 55 , the insulator 56 , the yttrium oxide film 66 , the ferroelectric film (STN film) 57 , and the upper electrode 62 , with the ferroelectric film (STN film) 57 placed on the yttrium oxide film 66 , which serves as a base.
  • ferroelectric film (STN film) 57 a coercive field of 200 kV/cm or more, a fine crystal grain size, and an excellent adhesion to the base, while preventing oxygen deficiency.
  • the semiconductor device 71 structured to place the ferroelectric film (STN film) 57 on the yttrium oxide film 66 can be more reduced in size than in prior art and operate stably, and is low-cost.
  • a semiconductor device 71 a according to a second embodiment of the present invention is described next with reference to FIGS. 14 to 16 .
  • the semiconductor device 71 a according to the second embodiment is obtained by adding a silicon nitride (SiN) film 76 to the semiconductor device 71 of the first embodiment.
  • SiN silicon nitride
  • the semiconductor device 71 a comprises the SiN film 76 provided between an SiO 2 film 77 , which is an insulator, and the substrate 55 .
  • a semiconductor device thus may comprise the SiN film 76 between the SiO 2 film 77 and the substrate 55 and, when structured as this, can be increased in dielectric constant of the gate insulator.
  • a method of manufacturing the semiconductor device 71 a is described next with reference to FIGS. 15 and 16 .
  • An Si substrate is prepared as the substrate 55 first and, as illustrated in FIG. 15 , a surface of the substrate 55 is nitrided to form the SiN film 76 .
  • nitriding method there is no particular nitriding method to be employed.
  • the nitriding can be accomplished through a plasma process.
  • the yttrium oxide film 66 is formed on the surface of the substrate 55 that has been treated by nitriding.
  • the yttrium oxide film 66 is formed by one of the sputtering of yttrium in an oxidizing atmosphere, the sputtering of yttrium oxide in an inert gas atmosphere, the sputtering of yttrium oxide in an oxidizing atmosphere, and employing the sol-gel process.
  • the formed yttrium oxide film is oxidized preferably with oxygen radicals.
  • the sputtering of yttrium in an oxidizing atmosphere is employed. Sputtering is performed in an oxidizing atmosphere, and hence a surface of the SiN film 76 is oxidized and forms the SiO 2 film 77 during the formation of the yttrium oxide film 66 and, as illustrated in FIG. 16 , it is on the SiO 2 film 77 that the yttrium oxide film 66 is formed.
  • the SiN film 76 is thus provided between the SiO 2 film 77 and the substrate 55 .
  • ferroelectric film (STN film) 57 is not limited to a particular method, and any of the sol-gel process, sputtering, and chemical vapor deposition using an organic metal compound may be employed.
  • the ferroelectric film (STN film) 57 and the upper electrode 62 here are formed on the yttrium oxide film 66 the same way as in the first embodiment, and the description thereof is omitted.
  • the semiconductor device 71 a comprises the substrate 55 , the SiN film 76 , the SiO 2 film 77 , the yttrium oxide film 66 , the ferroelectric film (STN film) 57 , and the upper electrode 62 , with the ferroelectric film (STN film) 57 placed on the yttrium oxide film 66 , which serves as a base.
  • the second embodiment therefore comprises the same effects as the first embodiment.
  • the semiconductor device 71 a according to the second embodiment comprises the SiN film 76 provided between the SiO 2 film 77 and the substrate 55 .
  • An STN film was formed to a thickness of 130 nm on a 6 nm-thick yttrium oxide film with the use of the sputtering apparatus 101 , the plasma process apparatus 103 , and the annealing apparatus (furnace) 102 illustrated in FIGS. 2 to 5 .
  • a surface of the STN film was observed under 100,000 power magnification.
  • the STN film comprises fine crystals with a crystal grain size of several tens nm (for example, regions indicated by white arrows A and B of FIG. 10 ), and it was proven that forming an STN film on an yttrium oxide thin film makes crystal grains finer.
  • An STN film was formed on an yttrium oxide thin film in the same way as in Example 1, with the use of the sputtering apparatus 101 , the plasma process apparatus 103 , and the annealing apparatus (furnace) 102 illustrated in FIGS. 2 to 5 .
  • XRD X-ray diffraction
  • Results are shown in FIG. 11 .
  • perovskite STN (2/2/7) was formed as the STN film on the yttrium oxide thin film.
  • the semiconductor device 71 illustrated in FIG. 1 was built with the use of the sputtering apparatus 101 , the plasma process apparatus 103 , and the annealing apparatus (furnace) 102 illustrated in FIGS. 2 to 5 .
  • the high-frequency CV characteristics of the semiconductor device 71 were evaluated.
  • a Cz p-Si substrate was prepared as the substrate 55 and a 7 nm-thick SiO 2 film was formed as the insulator 56 on the substrate 55 .
  • Example 2 Under the same condition as in Example 1, a 6 nm-thick Y 2 O 3 film was formed as the yttrium oxide film 66 on the insulator 56 , and an STN film with a dielectric constant (STN) of 30 was formed to a thickness of 130 nm as the ferroelectric film (STN film) 57 .
  • STN dielectric constant
  • an Al film was formed by sputtering.
  • the high-frequency CV characteristics were evaluated under conditions where the capacitor area of the ferroelectric film (STN film) 57 is 4.9 ⁇ 10 ⁇ 4 cm 2 and the frequency of the applied voltage is 1 MHz.
  • Results are shown in FIG. 12 .
  • the CV characteristics of the semiconductor device 71 form a counter-clockwise hysteresis curve indicating ferroelectricity, and the coercive field of the ferroelectric film (STN film) 57 was revealed to be astonishingly high at 230 kV/cm.
  • a memory window ( ⁇ Vg) derived from the ferroelectric film (STN film) 57 is 6 V.
  • the ferroelectric film and the semiconductor device according to the present invention are applicable to the manufacture of electronic parts and electronic apparatuses such as a ferroelectric memory device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Analytical Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
US12/385,868 2008-04-23 2009-04-22 Semiconductor device and method of manufacturing the semiconductor device Abandoned US20090267122A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008112994A JP2009266967A (ja) 2008-04-23 2008-04-23 強誘電体膜、強誘電体膜を有する半導体装置、及びそれらの製造方法
JP2008-112994 2008-04-23

Publications (1)

Publication Number Publication Date
US20090267122A1 true US20090267122A1 (en) 2009-10-29

Family

ID=41214132

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/385,868 Abandoned US20090267122A1 (en) 2008-04-23 2009-04-22 Semiconductor device and method of manufacturing the semiconductor device

Country Status (2)

Country Link
US (1) US20090267122A1 (enrdf_load_stackoverflow)
JP (1) JP2009266967A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210083121A1 (en) * 2019-09-18 2021-03-18 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US20210151445A1 (en) * 2018-07-31 2021-05-20 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Ferroelectric semiconductor device and method for producing a memory cell
US20220271046A1 (en) * 2021-02-25 2022-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked ferroelectric structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834804A (en) * 1996-10-28 1998-11-10 Samsung Electronics Co., Ltd. Ferroelectric structure including MgTiO3 passivation
US5985404A (en) * 1996-08-28 1999-11-16 Tdk Corporation Recording medium, method of making, and information processing apparatus
US6097058A (en) * 1997-05-23 2000-08-01 Rohm Co., Ltd. Ferroelectric memory device and a method of manufacturing thereof
US20010028582A1 (en) * 2000-04-07 2001-10-11 Yasuo Tarui Ferroelectric memory element
US20030021479A1 (en) * 2001-06-29 2003-01-30 Rohm Co., Ltd. Ferroelectric memory
US6544857B1 (en) * 1999-02-12 2003-04-08 Sony Corporation Dielectric capacitor manufacturing method and semiconductor storage device manufacturing method
US20040222438A1 (en) * 2001-10-15 2004-11-11 Renesas Technology Corp. Semiconductor memory device and manufacturing process for the same
US20050006684A1 (en) * 2003-02-09 2005-01-13 Matsushita Electric Industrial Co., Ltd Capacitive element and semiconductor memory device
US20070004202A1 (en) * 2005-06-30 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US20070034918A1 (en) * 2003-02-05 2007-02-15 Tokyo Electron Limited Ferroelectric film, semiconductor device, ferroelectric film manufacturing method, and ferroelectric film manufacturing apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005101517A (ja) * 2003-09-02 2005-04-14 Matsushita Electric Ind Co Ltd 容量素子及び半導体記憶装置
JP2006261159A (ja) * 2005-03-15 2006-09-28 Tohoku Univ 強誘電体膜、金属酸化物、半導体装置、及びそれらの製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985404A (en) * 1996-08-28 1999-11-16 Tdk Corporation Recording medium, method of making, and information processing apparatus
US5834804A (en) * 1996-10-28 1998-11-10 Samsung Electronics Co., Ltd. Ferroelectric structure including MgTiO3 passivation
US6097058A (en) * 1997-05-23 2000-08-01 Rohm Co., Ltd. Ferroelectric memory device and a method of manufacturing thereof
US6544857B1 (en) * 1999-02-12 2003-04-08 Sony Corporation Dielectric capacitor manufacturing method and semiconductor storage device manufacturing method
US20010028582A1 (en) * 2000-04-07 2001-10-11 Yasuo Tarui Ferroelectric memory element
US20030021479A1 (en) * 2001-06-29 2003-01-30 Rohm Co., Ltd. Ferroelectric memory
US20040222438A1 (en) * 2001-10-15 2004-11-11 Renesas Technology Corp. Semiconductor memory device and manufacturing process for the same
US20070034918A1 (en) * 2003-02-05 2007-02-15 Tokyo Electron Limited Ferroelectric film, semiconductor device, ferroelectric film manufacturing method, and ferroelectric film manufacturing apparatus
US20050006684A1 (en) * 2003-02-09 2005-01-13 Matsushita Electric Industrial Co., Ltd Capacitive element and semiconductor memory device
US20070004202A1 (en) * 2005-06-30 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Jeff Hecht, Understanding Lasers: An Entry-Level Guide (IEEE Press Understanding Science & Technology Series), 2008, IEEE Press, 3rd edition, pgs 281-285, http://www.globalspec.com/reference/13681/160210/chapter-9-4-4-lattice-matching-and-strain *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210151445A1 (en) * 2018-07-31 2021-05-20 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Ferroelectric semiconductor device and method for producing a memory cell
US11672127B2 (en) * 2018-07-31 2023-06-06 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Ferroelectric semiconductor device and method for producing a memory cell
US20210083121A1 (en) * 2019-09-18 2021-03-18 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US11522082B2 (en) * 2019-09-18 2022-12-06 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US11824118B2 (en) 2019-09-18 2023-11-21 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US12230711B2 (en) 2019-09-18 2025-02-18 Samsung Electronics Co., Ltd. Electronic device and method of manufacturing the same
US20220271046A1 (en) * 2021-02-25 2022-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked ferroelectric structure
US11508755B2 (en) * 2021-02-25 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked ferroelectric structure
US12207474B2 (en) 2021-02-25 2025-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked ferroelectric structure
US12232329B2 (en) 2021-02-25 2025-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked ferroelectric structure

Also Published As

Publication number Publication date
JP2009266967A (ja) 2009-11-12

Similar Documents

Publication Publication Date Title
US5614252A (en) Method of fabricating barium strontium titanate
US8524617B2 (en) Methods for manufacturing dielectric films
US20140242808A1 (en) Semiconductor device manufacturing method and substrate processing system
US20050255711A1 (en) Method for forming underlying insulation film
JP2001131741A (ja) 触媒スパッタリングによる薄膜形成方法及び薄膜形成装置並びに半導体装置の製造方法
JP5460011B2 (ja) 窒化珪素膜の成膜方法、コンピュータ読み取り可能な記憶媒体およびプラズマcvd装置
EP2053642A1 (en) Film-forming method and film-forming apparatus
US7736446B2 (en) Method for manufacturing a lanthanum oxide compound
US20090267122A1 (en) Semiconductor device and method of manufacturing the semiconductor device
US20150087160A1 (en) Substrate processing apparatus, method of manufacturing semiconductor device, and recording medium
WO2006085427A1 (ja) 容量素子の製造方法及び半導体装置の製造方法並びに半導体製造装置
US20070034918A1 (en) Ferroelectric film, semiconductor device, ferroelectric film manufacturing method, and ferroelectric film manufacturing apparatus
KR100433465B1 (ko) 금속산화물유전체막의 기상성장방법 및 금속산화물유전체재료의 기상성장을 위한 장치
WO2009123335A1 (ja) Mos型半導体メモリ装置の製造方法およびプラズマcvd装置
JP3427362B2 (ja) 誘電体薄膜堆積方法
Lesaicherre et al. Preparation of SrTiO3 thin films by ECR and thermal MOCVD
JP2010016127A (ja) 強誘電体膜、強誘電体膜を有する半導体装置、及びそれらの製造方法
JP3111994B2 (ja) 金属酸化物誘電体材料の気相成長装置
JP5300017B2 (ja) 強誘電体膜の製造方法と、強誘電体膜を用いた半導体装置
JP3271113B2 (ja) 誘電体薄膜の成膜方法
JP2006261159A (ja) 強誘電体膜、金属酸化物、半導体装置、及びそれらの製造方法
JP2009266967A5 (enrdf_load_stackoverflow)
CN1060224C (zh) 钛酸镧铅薄膜的形成方法
JP2565288B2 (ja) 高誘電率薄膜の製造方法
JP2009267391A (ja) 窒化珪素膜の製造方法、窒化珪素膜積層体の製造方法、コンピュータ読み取り可能な記憶媒体およびプラズマcvd装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHMI, TADAHIRO;TAKAHASHI, ICHIRO;REEL/FRAME:022639/0434

Effective date: 20090421

Owner name: FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENC

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OHMI, TADAHIRO;TAKAHASHI, ICHIRO;REEL/FRAME:022639/0434

Effective date: 20090421

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION