US20090236680A1 - Semiconductor device with a semiconductor body and method for its production - Google Patents

Semiconductor device with a semiconductor body and method for its production Download PDF

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US20090236680A1
US20090236680A1 US12/052,019 US5201908A US2009236680A1 US 20090236680 A1 US20090236680 A1 US 20090236680A1 US 5201908 A US5201908 A US 5201908A US 2009236680 A1 US2009236680 A1 US 2009236680A1
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doping
zones
semiconductor
doping material
conduction type
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Armin Willmeroth
Franz Hirler
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Assigned to INFINEON TECHNOLOGIES AUSTRIA AG reassignment INFINEON TECHNOLOGIES AUSTRIA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIRLER, FRANZ, WILLMEROTH, ARMIN
Priority to DE102009010373.2A priority patent/DE102009010373B4/de
Publication of US20090236680A1 publication Critical patent/US20090236680A1/en
Priority to US13/085,196 priority patent/US8569150B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors

Definitions

  • the application relates to a semiconductor device with a semiconductor body and to a method for its production.
  • the semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type.
  • the semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones.
  • the charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material.
  • a minimum on resistance is desirable in charge compensation devices of this type.
  • the level of drift zone doping material has to be increased further.
  • the doping of the charge compensation zones has to be increased in the same way.
  • the geometrical period in the form of the step size of the charge compensation zones and possibly even of the drift zones has to be reduced further at the same time.
  • the concentration of doping material per unit of area as integrated in the horizontal direction must not be higher than twice the breakdown charge.
  • breakdown charge denotes the charge carrier quantity (doping material concentration quantity) per unit of area which, starting from a p-n junction, is depleted if the breakdown field strength is applied.
  • the requirement that the regions should be capable of being depleted is equivalent to the requirement that the concentration of doping material per unit of area as integrated in the horizontal direction should not be higher than twice the breakdown charge. These conditions have to be met both by the compensation regions and by the drift zones. Similar to the breakdown field strength, the breakdown charge is determined by the concentration of doping material; for silicon is lies between 1 ⁇ 10 12 cm ⁇ 2 at low doping and 3 ⁇ 10 12 cm ⁇ 2 at high doping.
  • the regions of a complementary conduction type for the charge compensation zones which are introduced by masked or selective ion implantation and typically doped with boron, have to diffuse together through the epitaxial growth phases of finite thickness. This however unavoidably involves major widening of the columns or strips of charge compensation zone material.
  • non-doped epitaxial layers can be grown in the epitaxial growth phase, whereupon both doping materials of the first conduction type and doping materials of the complementary second conduction type can be introduced in succession by ion implantation near the surface between individual epitaxial growth phases, so that the widening caused by lateral outdiffusion while the charge compensation zones diffuse together can be noticeably reduced by a relatively high adjacent n-doping of the drift zones.
  • n-doping in the middle of the epitaxial growth phase is relatively low can only be compensated by raising the general level of implanted doping material in order to reduce the on resistance.
  • a high level of doping material automatically complicates the manufacturing process, as breakdown voltage is highly dependent on wrong doping. The higher the level of doping material, the higher are its fluctuations and the more difficult is it to obtain the required breakdown voltage.
  • An embodiment of the invention relates to a semiconductor device with a semiconductor body.
  • the semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type.
  • the semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones.
  • the charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material.
  • the epitaxially grown semiconductor material contains 20 to 80 atomic % of the doping material of the drift zones and a doping material balance between 80 and 20 atomic % introduced by ion implantation and diffusion.
  • FIGS. 1-8 illustrate production processes for a semiconductor device of an embodiment of the invention.
  • FIG. 1 illustrates a diagrammatic cross-section through a semiconductor wafer.
  • FIG. 2 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 1 following the completion of a first epitaxial growth phase with homogeneous doping of the epitaxial layer.
  • FIG. 3 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 2 following the large-area unmasked ion implantation of a doping material balance for a first conduction type.
  • FIG. 4 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 3 following the masked selective ion implantation of a complementary second conduction type.
  • FIG. 5 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 4 following a second epitaxial growth phase and a large-area unmasked ion implantation of a doping material balance of the first conduction type.
  • FIG. 6 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 5 following the masked selective ion implantation of a doping material of a complementary second conduction type.
  • FIG. 7 illustrates a diagrammatic cross-section through a section of the semiconductor wafer following the completion of six epitaxial growth phases.
  • FIG. 8 illustrates a diagrammatic cross-section through the section according to FIG. 7 following the diffusing together of the implanted charge compensation zone doping to form a column- or strip-shaped charge compensation zone.
  • FIG. 9 illustrates a diagram of the concentration behaviour of the doping material of the first conduction type in a drift zone.
  • FIGS. 10-18 illustrate production processes for a semiconductor device of a further embodiment of the invention.
  • FIG. 10 illustrates a diagrammatic cross-section through a semiconductor wafer.
  • FIG. 11 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 10 following the completion of a first epitaxial growth phase with inhomogeneous doping of the epitaxial layer.
  • FIG. 12 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 11 following the large-area unmasked ion implantation of a doping material balance for a first conduction type.
  • FIG. 13 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 12 following the masked selective ion implantation of a doping material for a complementary second conduction type.
  • FIG. 14 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 13 following a second epitaxial growth phase and a large-area unmasked ion implantation of a doping material balance of a first conduction type.
  • FIG. 15 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 14 following the masked selective ion implantation of a doping material of a complementary second conduction type.
  • FIG. 16 illustrates a diagrammatic cross-section through a section of the semiconductor wafer following the completion of six epitaxial growth phases.
  • FIG. 17 illustrates a diagrammatic cross-section through the section according to FIG. 16 following the diffusing together of the implanted charge compensation zone doping to form a column- or strip-shaped charge compensation zone.
  • FIG. 18 is a diagram illustrating further reduced fluctuations of the charge carrier concentration in the drift zone.
  • FIG. 19 illustrates a diagrammatic cross-section through a semiconductor device according to an embodiment of the invention.
  • FIG. 1 illustrates a diagrammatic cross-section through a semiconductor wafer 16 , which can be used as a semiconductor substrate 17 for a variety of semiconductor devices.
  • This semiconductor wafer 16 may, for example, initially be highly doped with a doping material for a first conduction type, thus being n + -conducting, to produce MOSFET power transistors with a compensation structure.
  • doping materials arsenic or phosphorus may be introduced during the single crystal growing phase in concentrations between 5 ⁇ 10 18 cm ⁇ 3 and 5 ⁇ 10 20 cm ⁇ 3 or generated in the crystal by appropriate neutron bombardment.
  • a first epitaxial layer is deposited on the front side 20 , which has been polished mirror-bright in a chemical-mechanical process, in a first epitaxial growth phase.
  • FIG. 2 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 1 following the completion of a first epitaxial growth phase.
  • a thickness d of n-type silicon is grown in a monocrystalline manner; in this first embodiment of the invention, 20 to 80 atomic % of the doping material for drift zones are homogeneously distributed in this epitaxial layer.
  • the missing doping material quantity of 80 to 20 atomic % can be introduced near the surface by ion implantation to limit the widening of the compensation regions by the lateral diffusion of the complementary-type doping materials for charge compensation zones.
  • This homogeneous pre-doping which however only provides 20 to 80 atomic % of the doping materials of the drift zones, avoids the disadvantage of the relatively high resistance in the middle region of the epitaxial growth phase, which occurs in multiple epitaxial processes with non-doped epitaxial growth phases.
  • a non-doped epitaxial layer is often applied, followed by the doping of the drift zones and the charge compensation zones by ion implantation.
  • the pre-doping described above avoids such disadvantages of reduced conductivity in the middle of the epitaxial growth phase.
  • the missing doping material balance between 80 and 20 atomic % can then be introduced near the surface by ion implantation as illustrated in FIG. 3 , thereby limiting the lateral widening of the charge compensation columns.
  • the on resistance is affected both by wide compensation regions and by insufficiently high doping in the middle of the epitaxial growth phases. By using simulations, it can be shown that the on resistance can be minimized by the combination of two methods described above, i.e. the doping of the epitaxy and implantation between the epitaxial growth phases.
  • FIG. 3 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 2 following the ion implantation of a doping material balance ⁇ n for a first conduction type.
  • a charge carrier concentration of n+ ⁇ n is obtained near the surface of the first epitaxial layer 18 by an additional ion implantation of, for example, phosphorus or arsenic for a first conduction type 4 of the drift zones.
  • the near-surface zone with the doping material balance 9 of 80 to 20 atomic % of drift zone doping as illustrated in FIG. 3 will in the subsequent diffusion process be distributed in the illustrated epitaxial layer to a thickness d.
  • FIG. 4 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 3 following the selective ion implantation of a complementary conduction type 7 in windows 23 of a previously applied ion implantation mask 22 for the second complementary conduction type 7 .
  • Boron may be used as a doping material for the complementary conduction type 7 .
  • concentration of doping material increased by ⁇ n prevails near the surface in the drift zone regions 3 , the lateral expansion of the charge compensation zone doping 8 in the subsequent diffusion process to form charge compensation zone columns or strips is limited, allowing for a smaller step size between the charge compensation zones and thus permitting a higher doping of the drift zones.
  • FIG. 5 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 4 following a second epitaxial growth phase and an ion implantation of a doping material balance of the first conduction type, which is once again introduced into this second epitaxial layer 24 unmasked, over a large area and near the surface.
  • This ion implantation of the first conduction type 4 for the drift zone 3 does not require any diffusion mask for the near-surface introduction of the doping material balance 9 .
  • Only the next process illustrated in FIG. 6 requires a suitable ion implantation mask 22 for the selective introduction of a doping material of a complementary conduction type.
  • FIG. 6 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 5 following the selective ion implantation of a doping material of a complementary second conduction type. This creates a further doping material reservoir in the open windows 23 of the ion implantation mask 22 , but without any connection to the complementary-type regions of the charge compensation zones as illustrated in FIG. 4 .
  • FIG. 7 illustrates a diagrammatic cross-section through a section of the semiconductor wafer following the completion of six epitaxial growth phases, wherein 20 to 80 atomic % of homogeneously distributed doping material of the first conduction type 4 have been introduced and the missing doping material balance is introduced near the surface in the regions 9 by ion implantation after each epitaxial growth phase, resulting in the structure illustrated in FIG. 7 , wherein the selectively introduced charge compensation zone doping 8 does not yet form a coherent charge compensation zone column or strip. This requires a further diffusion process, wherein the doping material balance 9 for the drift zones 3 is distributed further in the semiconductor material.
  • FIG. 8 illustrates a diagrammatic cross-section through the section according to FIG. 7 following the diffusing together of the implanted charge compensation zone doping to form a column- or strip-shaped charge compensation zone 6 .
  • Whether column- or strip-shaped charge compensation zones 6 are generated depends on the ion implantation mask prepared for the semiconductor device.
  • the doping material balance ⁇ n has likewise been distributed further in the drift zones 3 by diffusion processes, so that relatively highly doped drift zones 3 of a small step size p in micrometers of p ⁇ 12 ⁇ m can be created, which reduces the on resistance of a semiconductor device with a drift zone structure of this type.
  • FIG. 9 illustrates a diagram with optimised concentration fluctuations of the doping material in a drift zone.
  • the doping material concentration N is plotted on the abscissa, while the penetration depth, which is a measure for the blocking capability of the semiconductor device, is plotted on the ordinate.
  • concentration fluctuations are noticeably minimized owing to the homogeneous pre-doping of the epitaxial layers in the range of 20 to 80 atomic %.
  • the homogeneously distributed proportion of doping material in the epitaxial growth phases can be limited to a third of the total concentration of doping material for the first conduction type, while two thirds subsequently have to be introduced near the surface by ion implantation.
  • the proportion of doping material introduced by ion implantation is significantly larger than the proportion introduced into the semiconductor crystal by homogeneous doping in the epitaxial growth phase.
  • Fluctuations in the concentration of doping material for the drift zones can be reduced further by using a technology and a manufacturing process described below with reference to FIGS. 10 to 18 and resulting in a semiconductor device illustrated in FIG. 19 .
  • This method is likewise based on a semiconductor wafer 16 as illustrated in FIG. 10 , which is highly doped with an n + -type doping material.
  • FIG. 11 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 10 following the completion of a first epitaxial growth phase.
  • the doping material is not introduced homogeneously, but rather inhomogeneously, i.e. the addition of doping material is reduced or stopped completely during the epitaxial growth process, resulting in a maximum of doping material approximately in the middle of the epitaxial growth phase.
  • the boundaries of the region with a maximum doping n max are indicated by dot-dash lines in the epitaxial layer 18 of FIG. 11 .
  • the relatively lightly doped, near-surface region is filled unmasked with the doping material balance over a large area by using ion implantation as illustrated in FIG. 12 .
  • FIG. 13 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 12 following the selective ion implantation of a doping material for a complementary second conduction type.
  • This FIG. 13 corresponds to FIG. 4 , and owing to the ion-implanted concentration of doping material, the lateral outdiffusion of the p-type material introduced by ion implantation is limited, allowing the production of compensated semiconductor devices with small step sizes of less than 12 ⁇ m.
  • FIG. 14 illustrates a diagrammatic cross-section through the semiconductor wafer according to FIG. 13 following a second epitaxial growth phase and an ion implantation of a doping material balance of a first conduction type, which is once again introduced unmasked and over a large area into the semiconductor wafer. Moreover, a maximum n max of doping material is introduced in the middle of the growth phase during the second epitaxial growth phase, in order to increase the doping in the drift zone further and to ensure that the on resistance for a compensated device of this type is further reduced.
  • n max of doping material is introduced in the middle of the growth phase during the second epitaxial growth phase, in order to increase the doping in the drift zone further and to ensure that the on resistance for a compensated device of this type is further reduced.
  • FIG. 15 illustrates a diagrammatic cross-section through the semiconductor wafer 16 according to FIG. 14 following the selective ion implantation of a doping material of a complementary second conduction type in windows 23 of an ion implantation mask 22 , generating further p-type islands which are diffused together on completion of all of the epitaxial growth phases; in this process, the concentration of doping material in the drift zones becomes uniform.
  • FIG. 16 illustrates a diagrammatic cross-section through a section of the semiconductor wafer following the completion of six epitaxial growth phases, wherein initially a maximum doping n max of the first conduction type 4 is generated in each epitaxial growth phase, followed by the introduction of a doping material balance in the region of the future drift zones by large-area ion implantation.
  • FIG. 17 illustrates a diagrammatic cross-section through the section according to FIG. 16 following the diffusing together of the implanted charge compensation zone doping 8 to form a column- or strip-shaped charge compensation zone 6 .
  • This column 10 illustrates a reduced lateral outdiffusion between individual epitaxial growth phases, allowing for a smaller step size in combination with higher doping of the drift zones 3 .
  • FIG. 18 illustrates further reduced fluctuations of the charge carrier concentration in the drift zone.
  • the doping material concentration N is plotted on the abscissa, while the thickness or depth in the direction z of the individual epitaxial growth phases is once again plotted on the ordinate.
  • the dot-dash line within each epitaxial growth phase indicates a maximum concentration of doping material introduced into each epitaxial layer, while ion implantation with a concentration of ⁇ n is carried out between the epitaxial growth phases, which in turn prevents the lateral outdiffusion of the complementary-conducting material for the charge compensation zones.
  • the distribution of the charge carrier concentration ⁇ n introduced by ion implantation is indicated by broken lines, while the fluctuation of the charge carrier concentration in the drift zones after diffusion is indicated by a continuous line. Any fluctuations which are still noticeable are so negligible that the charge compensation zones and the drift zones can come closer together, allowing for a higher drift zone doping.
  • FIG. 19 illustrates a diagrammatic cross-section through a semiconductor device 1 according to an embodiment wherein the lateral outdiffusion for the charge compensation zones 6 is significantly reduced by the methods described above, whereby the fluctuation of the doping material concentration in the drift zones is reduced in the vertical direction.
  • This embodiment is a vertical MOSFET with a lateral gate structure, but the teaching of the invention can also be applied to JFET or other compensated device structures, provided that a multiple epitaxial structure is provided for the drift zone.
  • the charge compensation zones are completed by the near-surface introduction of a p-type body zone 12 , which in turn accommodates a highly doped n + -type source zone 13 , wherein the highly doped n + -type source zone 13 and the body zone 12 are contacted by a metallic source electrode 14 , while a lateral gate structure insulated against the body zone 12 by a gate oxide 25 permits the control of this power transistor.
  • a step size 15 of less than 12 ⁇ m can be achieved between the charge compensation zones.
  • the substrate 17 or the original semiconductor wafer 16 can be ground thin, thus further minimising the on resistance of the semiconductor device 1 .

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CN103022123A (zh) * 2011-09-21 2013-04-03 上海华虹Nec电子有限公司 超级结半导体器件及其制造方法
CN103021863A (zh) * 2011-09-27 2013-04-03 万国半导体股份有限公司 精确校准及自平衡的超级结器件的制备方法
CN104009072A (zh) * 2013-02-25 2014-08-27 中国科学院微电子研究所 一种绝缘栅双极型晶体管及其制作方法
CN105225959A (zh) * 2014-07-01 2016-01-06 北大方正集团有限公司 沟槽型功率器件的制造方法和沟槽型功率器件
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WO2023216648A1 (zh) * 2022-05-09 2023-11-16 瑶芯微电子科技(上海)有限公司 提高超结结构外延生长稳定性及半导体器件制备的方法

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CN102800701A (zh) * 2011-05-25 2012-11-28 快捷韩国半导体有限公司 具有超结的半导体装置及其制造方法
US11133379B2 (en) * 2011-05-25 2021-09-28 Semiconductor Components Industries, Llc Semiconductor device having a super junction structure and method of manufacturing the same
US11588016B2 (en) 2011-05-25 2023-02-21 Semiconductor Components Industries, Llc Semiconductor device having a super junction structure and method of manufacturing the same
CN103022123A (zh) * 2011-09-21 2013-04-03 上海华虹Nec电子有限公司 超级结半导体器件及其制造方法
CN103021863A (zh) * 2011-09-27 2013-04-03 万国半导体股份有限公司 精确校准及自平衡的超级结器件的制备方法
US9647059B2 (en) 2011-09-27 2017-05-09 Alpha And Omega Semiconductor Incorporated Manufacturing methods for accurately aligned and self-balanced superjunction devices
CN104009072A (zh) * 2013-02-25 2014-08-27 中国科学院微电子研究所 一种绝缘栅双极型晶体管及其制作方法
CN105225959A (zh) * 2014-07-01 2016-01-06 北大方正集团有限公司 沟槽型功率器件的制造方法和沟槽型功率器件
CN112820628A (zh) * 2020-12-31 2021-05-18 广州粤芯半导体技术有限公司 外延层的制备方法
US20220271154A1 (en) * 2021-02-25 2022-08-25 Db Hitek Co., Ltd. Superjunction semiconductor device and method of manufacturing same
US12009419B2 (en) * 2021-02-25 2024-06-11 DB HiTek, Co., Ltd. Superjunction semiconductor device and method of manufacturing same
WO2023216648A1 (zh) * 2022-05-09 2023-11-16 瑶芯微电子科技(上海)有限公司 提高超结结构外延生长稳定性及半导体器件制备的方法

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US20110189839A1 (en) 2011-08-04

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