US20090144485A1 - Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like) - Google Patents

Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like) Download PDF

Info

Publication number
US20090144485A1
US20090144485A1 US12/367,055 US36705509A US2009144485A1 US 20090144485 A1 US20090144485 A1 US 20090144485A1 US 36705509 A US36705509 A US 36705509A US 2009144485 A1 US2009144485 A1 US 2009144485A1
Authority
US
United States
Prior art keywords
memory
configurable
elements
read
memory units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/367,055
Inventor
Martin Vorbach
Robert Munch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KRASS MAREN MS
RICHTER THOMAS MR
Original Assignee
Martin Vorbach
Robert Munch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DEDE19654846.2 priority Critical
Priority to DE1996154846 priority patent/DE19654846A1/en
Priority to US09/613,217 priority patent/US6477643B1/en
Priority to US10/265,846 priority patent/US7028107B2/en
Priority to US11/246,617 priority patent/US7822881B2/en
Application filed by Martin Vorbach, Robert Munch filed Critical Martin Vorbach
Priority to US12/367,055 priority patent/US20090144485A1/en
Publication of US20090144485A1 publication Critical patent/US20090144485A1/en
Assigned to KRASS, MAREN, MS., RICHTER, THOMAS, MR. reassignment KRASS, MAREN, MS. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PACT XPP TECHNOLOGIES AG
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17752Structural details of configuration resources for hot reconfiguration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17756Structural details of configuration resources for partial configuration or reconfiguration
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/1776Structural details of configuration resources for memories
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17776Structural details of configuration resources for speeding up configuration or reconfiguration

Abstract

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 10/265,846, filed Oct. 7, 2002, which is a continuation of U.S. patent application Ser. No. 09/613,217, filed Jul. 10, 2000, now U.S. Pat. No. 6,477,643, which is a continuation of U.S. patent application Ser. No. 08/947,002 filed on Oct. 8, 1997, now U.S. Pat. No. 6,088,795, expressly incorporated herein by reference in the entirety.
  • FIELD OF THE INVENTION
  • The present invention is directed to a process for automatic dynamic reloading of data flow processors.
  • BACKGROUND INFORMATION
  • Programmable units presently used (DFPs, FPGAs—Field Programmable Gate Arrays) can be programmed in two different ways:
  • one-time only, i.e., the configuration can no longer be changed after programming. All configured elements of the unit perform the same function over the entire period during which the application takes place.
  • on site, i.e., the configuration can be changed after the unit has been installed by loading a configuration file when the application is started. Most units (in particular FPGA units) cannot be reconfigured during operation. For reconfigurable units, data usually cannot be further processed while the unit is being reconfigured, and the time required is very long.
  • Configuration data is loaded into programmable units through a hardware interface. This process is slow and usually requires hundreds of milliseconds due to the limited band width accessing the external memory where the configuration data is stored, after which the programmable unit is available for the desired/programmed function as described in the configuration file.
  • A configuration is obtained by entering a special bit pattern of any desired length into the configurable elements of the unit. Configurable elements can be any type of RAM cells, multiplexers, interconnecting elements or ALUs. A configuration string is stored in such an element, so that the element preserves its configuration determined by the configuration string during the period of operation.
  • The existing methods and options present a series of problems, such as:
  • If a configuration in a DFP (see German Patent Application No. DE 44 16 881 A1) or an FPGA is to be modified, a complete configuration file must always be transmitted to the unit to be programmed, even if only a very small part of the configuration is to be modified.
  • As a new configuration is being loaded, the unit can only continue to process data to a limited extent or not at all.
  • With the increasing number of configurable elements in each unit (in particular in FPGA units), the configuration files of these units also become increasingly large (several hundred Kbytes on average). Therefore it takes a very long time to configure a large unit and often makes it impossible to do it during operation or affects the function of the unit.
  • When a unit is partially configured during operation, a central logic entity is always used, through which all reconfigurations are managed. This requires considerable communication and synchronization resources.
  • SUMMARY OF THE INVENTION
  • The present invention makes it possible to reconfigure a programmable unit considerably more rapidly. The present invention allows different configurations of a programmable unit to be used in a flexible manner during operation without affecting or stopping the operability of the programmable unit. Unit configuration changes are performed simultaneously, so they are rapidly available without need for additional configuration data to be occasionally transmitted. The method can be used with all types of configurable elements of a configurable unit and with all types of configuration data, regardless of the purpose for which they are provided within the unit.
  • The present invention makes it possible to overcome the static limitations of conventional units and to improve the utilization of existing configurable elements. By introducing a buffer storage device, a plurality of different functions can be performed on the same data.
  • In a programmable unit, there is a plurality of ring memories, i.e., memories with a dedicated address control, which, upon reaching the end of the memory, continues at the starting point, thus forming a ring. These ring memories have read-write access to configuration registers, i.e., the circuits that receive the configuration data, of the elements to be configured. Such a ring memory has a certain number of records, which are loaded with configuration data by a PLU as described in German Patent Application No. 44 16 881 A1. The architecture of the records is selected so that their data format corresponds to the configurable element(s) connected to the ring memory and allows a valid configuration to be set.
  • Furthermore, there is a read position pointer, which selects one of the ring memory records as the current read record. The read position pointer can be moved to any desired position/record within the ring memory using a controller. Furthermore there is a write position pointer, which selects one of the ring memory records as the current write record. The write position pointer can be moved to any desired position/record within the ring memory using a controller.
  • At run time, to perform reconfiguration, a configuration string can be transmitted into the element to be configured without the data requiring management by a central logic or transmission. By using a plurality of ring memories, several configurable elements can be configured simultaneously.
  • Since a ring memory with its complete controller can switch configurable cells between several configuration modes, it is referred to as a switching table.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a schematic architecture of a ring memory.
  • FIG. 2 illustrates the internal architecture of a ring memory.
  • FIG. 3 illustrates a ring memory with a selectable work area.
  • FIG. 4 illustrates a ring memory and a controller capable of working on different ring memory sections using several read and write position pointers.
  • FIG. 5 illustrates a ring memory where different controllers access different sections.
  • FIG. 6 illustrates a ring memory and its connection to the configurable elements.
  • FIG. 7 illustrates the controller with a logic for responding to different trigger signals; a) implementation of the trigger pulse mask.
  • FIG. 8 illustrates the clock generator for the controller.
  • FIG. 9 illustrates the wiring of the controller and the internal cells allowing the configurable elements to be configured.
  • FIG. 10 illustrates the processing by the controller of the commands stored in the ring memory.
  • FIG. 11 illustrates the processing of the data stored in the ring memory.
  • FIG. 12 illustrates the connection of a buffer comprising two memory arrays to a set of configurable elements.
  • FIG. 12 a shows a step in the data processing sequence.
  • FIG. 12 b shown another step in the data processing sequence.
  • FIG. 12 c shown another step in the data processing sequence.
  • FIG. 12 d shown another step in the data processing sequence.
  • FIG. 13 illustrates the connection of a buffer with separate read/write pointers to a set of configurable elements.
  • FIG. 14 illustrates the operation of a buffer with separate read/write pointers.
  • FIG. 15 illustrates the connection of two buffers each comprising two memory arrays to a set of configurable elements; Figures a-c show the data processing sequence.
  • DETAILED DESCRIPTION OF THE INVENTION
  • There is a plurality of ring memories in a programmable unit or connected externally to said unit. The one or more ring memories have one or more controllers controlling the one or more ring memories. These controllers are part of the PLU named in German Patent Application No. DE 44 16 881 A1. The ring memories contain configuration strings for the configurable elements of one or a plurality of configurable units; the configurable elements can also be expressly used for interconnecting function groups and they can be crossbar circuits or multiplexers for interconnecting bus architectures, which are conventional.
  • Ring memories and ring memory controllers can be either directly hardware-implemented or first obtained by configuring one or more configurable cells of a configurable unit (e.g., FPGA).
  • Conventional ring memories can be used as ring memories, in particular ring memories and/or controllers with the following properties:
      • where not all records are used, and which have the capability of providing a position where the read and/or write position pointer of the ring memory is set to the beginning or the end of the ring memory. This can be implemented, for example, by using command strings (STOP, GOTO, etc.), counters, or registers storing the start and stop positions;
      • which make it possible to divide the ring memory into independent sections, and the controller of the ring memory can be set, for example, via the events listed below as examples, so that it works on one of these sections;
      • which male it possible to divide the ring memory into independent sections and there is a plurality of controllers, each one working on one section; a plurality of controllers may work on the same section. This can be implemented via arbiter switching, in which case certain processing cycles are lost. Registers can also be used instead of RAMs;
      • each controller has one or more read position pointers and/or one or more write position pointers;
      • this position pointer can be moved forward and/or backward;
      • this position pointer can be set to the start, end, or a given position on the basis of one or more events;
      • the controller has a mask register with which a subset can be selected from the set of all possible events by entering a data string. Only this subset of results is relayed to the controller as an event and triggers the forwarding of the position pointer(s);
      • controllers working with a multiple of the actual system clock rate (oversampling) to allow the processing of several records within a system cycle.
  • The switching table controller is implemented using a regular state machine. In addition to simple controllers required by a conventional ring memory, controllers with the following properties are best suited for performing or possibly expanding the control of the switching tables of a programmable unit (in particular also of FPGAs and DPGAs (Dynamically Programmable Gate Arrays, a new subgroup of FPGAs)) according to the present invention:
      • controllers capable of recognizing specific command strings. A command string is distinguished by the fact that it has an identifier, which allows the controller to recognize the data of a ring memory record as a command string rather than a data string;
      • controllers capable of executing specific command strings; specifically commands that change the sequence of the state machine and/or modify records of the ring memory through a data processing function;
      • controllers capable of recognizing an identifier and of processing additional records of the ring memory through the internal, higher-speed cycle (oversampling) on the basis of this identifier, until an end identifier is reached, or the next cycle of the clock that controls the oversampling cycle is reached.
  • In particular the following commands or a subset of those commands can be used as command strings for the appropriate control of a switching table requiring command string control. The command strings concerning position pointers can be used on the read position pointer(s) or on the write position pointer(s). Possible command strings include:
      • a WAIT command.
      • The WAIT command causes the controller to wait until the next event or (possibly several) events occur. During this state, the read/write position pointer(s) is (are) not moved. If the event(s) occur(s), the read/write position pointer(s) is (are) positioned on the next record.
      • a SKIP command.
      • The SKIP command causes a given number of ring memory records to be skipped by one of the following two methods:
  • The SKIP1 command is executed fully in a single processing cycle. If, for example, SKIP 5 is issued, the pointer jumps to the record located five records before (after) the current read/write record in a processing cycle.
  • The SKIP2 command is only executed after a number of processing cycles. It is conceivable, for example, that the SKIP 5 command is executed only after five processing cycles. Here again five records are skipped counting from the current record. The parameter (in this case the 5) is thus used twice.
  • The indication of the direction of jump can end either in a forward movement or in a backward movement of the position pointer with the use of a positive or negative number.
      • A SWAP command.
      • The SWAP command swaps the data of two given records.
      • RESET command.
      • The RESET command sets the read/write position pointer(s) to the start and/or a given record position within the ring memory.
      • A WAIT-GOTO command.
      • The WAIT-GOTO command waits like the above-described WAIT command for one or more specific events and then positions the read/write position pointer to a specific start state within one or more processing cycles.
      • A NOP command.
      • The NOP command executes no action. No data is transmitted from the ring memory to the element(s) to be configured, neither are the position pointers modified. Thus the NOP command identifies a record as non-relevant. However, this record is addressed and evaluated by the ring memory controller it requires using one or more processing cycles.
      • A GOTO command.
      • The GOTO command positions the read/write position pointer(s) on the given record position.
      • A MASK command.
      • The MASK command writes a new data string into the multiplexer, which selects the different events. Therefore, this command allows the events to which the controller responds to be changed.
      • An LLBACK command.
      • The LLBACK command generates a feedback to the PLU (as described in German Patent Application No. DE 44 16 881 A1). The switching table can cause greater regions of the unit to be reloaded, in particular it can cause the switching table itself to be reloaded.
      • A command triggering a read/modify/write cycle. The command triggers the reading of commands or data in another record, for example, by the controller, the PLU or an element located outside the switching table. This data is then processed in any desired fashion and written into the same or another position of the switching table ring memory. This can take place during one processing cycle of the switching table. The sequence is then terminated before a position pointer is repositioned.
  • The ring memory record architecture has the following format:
  • Data/Command Run/Stop Data
  • The first bit identifies a record as a command or a data string. The controller of the switching table thus decides whether the bit string in the data portion of the record should be treated as a command or as configuration data.
  • The second bit identifies whether the controller should proceed immediately even without the occurrence of another event, should proceed with the next record, or wait for the next event. If an oversampling process is used and the RUN bit is set, the subsequent records will be processed with the help of this oversampling cycle. This continues until a record without a RUN bit set has been reached or the number or records that can be processed at the oversampling cycle rate within one system cycle has been reached.
  • If an oversampling process is used, the normal system cycle and the RUN bit set cause commutation to take place. Events occurring during the execution of a command sequence marked with the RUN bit are analyzed and the trigger signal is stored in a flip-flop. The controller then analyzes this flip-flop again when a record without a RUN bit set is reached.
  • The rest of a record contains, depending on the type (data or command), all the necessary information, so that the controller can fully perform its function.
  • The size of the ring memory can be implemented according to the application; this is true in particular for programmable units, where the ring memory is obtained by configuring one or more configurable cells.
  • A ring memory is connected to an element to be configured (or a group of elements to be configured), so that a selected configuration string (in the ring memory) is entered in the configuration register of the element to be configured or group of elements to be configured.
  • Thus a valid and operational configuration of the element or group to be configured is obtained.
  • Each ring memory has one controller or a plurality of controllers, which control the positioning of the read position pointer and/or the write position pointer.
  • Using the feedback channels described in German Patent Application DE 44 16 881 A1, the controller can respond to events of other elements of the unit or to external events that are transmitted into the unit (e.g., interrupt, IO protocols, etc.) and, in response to these internal or external events, moves the read position pointer and/or the write position pointer to another record.
  • The following events are conceivable, for example:
      • clock signal of a CPU,
      • internal or external interrupt signal,
      • trigger signal of other elements within the unit,
      • comparison of a data stream and/or a command stream with a value,
      • input/output events,
      • counter run, overrun, reset,
      • evaluation of a comparison.
  • If a unit has several ring memories, the controller of each ring memory can respond to different events.
  • After each time the pointer is moved to a new record, the configuration string in this record is transferred to the configurable element(s) connected to the ring memory.
  • This transfer takes place so that the operation of the unit parts that are not affected by the reconfiguration remains unchanged.
  • The ring memory(ies) may be located either in a unit or connected to the unit from the outside via an external interface.
  • Each unit may have a plurality of independent ring memories, which can be concentrated in a region of the unit, but can also be distributed in a reasonable manner on the surface of the unit.
  • The configuration data is loaded by a PLU, such as described in German Patent Application No. DE 44 16 881 A1, or by other internal cells of the unit into the memory of the switching table. The configuration data can also be simultaneously transferred by the PLU or other internal cells of the unit to several different switching tables in order to allow the switching tables to load simultaneously.
  • The configuration data can also be in the main memory of a data processing system and be transferred by known methods, such as DMA or other processor-controlled data transfer, instead of the PLU.
  • After the PLU has loaded the ring memory of the switching table, the controller of the switching table is set to a start status, which establishes a valid configuration of the complete unit or parts of the unit. The control of the switching table starts now with repositioning of the read position pointer and/or the write position pointer as a response to events taking place.
  • In order to cause new data to be loaded into the switching table or a number of switching tables, the controller can return a signal to the PLU, as described in German Patent Application No. DE 44 16 881 A1, or other parts of the unit that are responsible for loading new data into the ring memory of the switching table. Such a feedback can be triggered by the analysis of a special command, a counter status, or from the outside (the State-Back UNIT described in Patent Application PACT02).
  • The PLU or other internal cells of the unit analyze this signal, respond to the signal by executing a program possibly in a modified form, and transfer new or different configuration data to the ring memory(ies). Only the data of each ring memory that is involved in a data transfer as determined by the signal analysis, rather than the configuration data of a complete unit, must be transferred.
  • Buffer: A memory can be connected to individual configurable elements or groups thereof (hereinafter referred to as functional elements). Several known procedures can be used to configure this memory; FIFOs are well-known, in particular. The data generated by the functional elements are stored in the memory until a data packet with the same operation to be performed is processed or until the memory is full. Thereafter the configuration elements are reconfigured through switching tables, i.e., the functions of the elements are changed. FullFlag showing that the memory is full can be used as a trigger signal for the switching tables. In order to freely determine the amount of data, the position of the FullFlag is configurable, i.e., the memory can also be configured through the switching table. The data in the memory is sent to the input of the configuration elements, and a new operation is performed on the data; the data is the operand for the new computation. The data can be processed from the memory only, or additional data can be requested from the outside (outside the unit or other functional elements) for this purpose. As the data is processed, it (the result of the operation) can be forwarded to the next configuration elements or written into the memory again. In order to provide both read and write access to the memory, the memory can have two memory arrays, which are processed alternately, or separate read and write position pointers can exist in the same memory.
  • One particular configuration option is the connection of a plurality of memories as described above, which allows several results to be stored in separate memories; then, at a given time, several memory regions are sent to the input of a functional element and processed in order to execute a given function.
  • Architecture of a ring memory record: One possible structure of the records in a switching table ring memory, used in a data processing system as described in German Patent Application No. DE 44 16 881 A1 is described below. The following tables show the command architecture using the individual bits of a command string.
  • Bit Number Name Description
    0 Data/Command Identifies a record as a data
    or command string
    1 Run/Stop Identifies Run or Stop mode
  • Thus, if a record is a data record, bit number 0 has the value 0, so the bits from position two have the following meanings:
  • Bit Number Name Description
    2-6  Cell number Provides the cell numbers within a group
    using the same switching table
    7-11 Configuration Provides the function that the cell (e.g., an
    data EALU) should execute
  • If the record is a command, bit number 0 has the value 1, and the bits from position two have the following meanings:
  • Bit
    Number Name Description
    2-6 Command Provides the number of the command that is
    number executed by the switching table controller
    7 Read/Write Shows whether the command is to be applied
    position pointer to the read position pointer or the write
    position pointer. If the command does not
    change either position pointer, the bit status is
    undefined.
    8-n Data Depending on the command, the data needed
    for the command are stored starting with bit 8.
  • In the following table, bits 2-6 and 8-n are shown for each of the commands listed. The overall bit length of a data string depends on the unit where the switching table is used. The bit length must be chosen so as to code all data needed for the commands in the bits starting from position 8.
  • Command Bit 2-6 Description of bit 8-n
    WAIT 00 00 0 Number indicating how often an event is to be
    waited for
    SKIP1 00 00 1 Number with plus or minus sign showing how
    many records are to be skipped forward
    (backward if negative)
    SKIP2 00 01 0 See SKIP1
    SWAP 00 01 1 1st record position, 2nd record position
    RESET 00 10 0 Number of the record on which the position
    pointer is to be set
    WAIT-GOTO 00 10 1 Number indicating how often an event is to be
    waited for, followed by the number of the
    record on which the position pointer is to be
    positioned
    NOP 00 11 0 No function!
    GOTO 00 11 1 Number of the record on which the position
    pointer is to be positioned
    MASK 01 00 0 Bit pattern entered into the multiplexer to
    select the events
    LLBACK 01 00 1 A trigger signal is generated for the PLU
    (feedback)
  • Reconfiguring ALUs: One or more switching tables can be used for controlling an ALU. The present invention can be used, for example, to improve on Patent PACT02, where the switching table is connected to the M/F PLUREG registers or the M/F PLUREG registers are fully replaced by a switching table.
  • FIG. 1 shows the schematic architecture of a ring memory. It comprises a write position pointer 0101 and a read position pointer 0102, which access a memory 0103. This memory can be configured as a RAM or as a register. Using the read/write position pointer, an address of RAM 0104 is selected, where input data is written or data is read, depending on the type of access.
  • FIG. 2 shows the internal architecture of a simple ring memory. Read position pointer 0204 has a counter 0201 and write position pointer 0205 has a counter 0206. Each counter 0201, 0206 has a global reset input and an up/down input, through which the counting direction is defined. A multiplexer 0202, whose inputs are connected to the outputs of the counters, is used to switch between write 0205 and read 0204 position pointers, which point to an address of memory 0203. Read and write access is performed through signal 0207. The respective counter is incremented by one position for each read or write access. When the read 0204 or write 0205 position pointer points at the last position of the memory (last address for an upward counting counter or first address for a downward counting counter), the read or write position pointer 0204, 0205 is set to the first position of memory 0203 in the next access (first address for an upward counting counter or the last address for a downward counting counter). This provides the ring memory function.
  • FIG. 3 shows an extension of the normal ring memory. In this extension, counter 0303 of the write position pointer 0311 and counter 0309 of the read position pointer 0312 can be loaded with a value, so that each address of the memory can be set directly. This loading sequence takes place, as usual, through the data and load inputs of the counters. In addition, the work area of the ring memory can be limited to a certain section of internal memory 0306. This is accomplished using an internal logic controlled by counters 0303, 0309 of the write/read position pointers 0311, 0312. This logic is designed as follows: The output of one counter 0303, 0309 is connected to the input of the respective comparator 0302, 0308, where the value of the counter is compared with the value of the respective data register (0301, 0307) where the jump position, i.e., the end of the ring memory section, is stored. If the two values are the same, the comparator (0302, 0308) sends a signal to the counter (0303, 0309), which then loads the value from the data register for the target address of the jump (0304, 0310), i.e., the beginning of the ring memory section. The data register for the jump position (0301, 0307) and the data register for the target address (0304, 0310) are loaded by the PLU (see PACT01). With this extension, it is possible that the ring memory does not use the entire region of the internal memory, but only a selected portion. In addition, the memory can be subdivided into different sections when several such read/write position pointers (0312, 0311) are used.
  • FIG. 4 shows the architecture of a ring memory divided into several sections with controller 0401 working on one of said sections. The controller is described in more detail in FIG. 7. In order to allow the ring memory to be divided into several sections, several read/write position pointers (0408, 0402), whose architecture was shown in FIG. 3, are used. The controller selects the region where it operates through multiplexer 0407. Read or write access is selected via multiplexer 0403. Thus the selected read/write position pointer addresses an address of memory 0404.
  • FIG. 5 shows the case where each of a plurality of controllers 0501 operates in its own region of the ring memory via one read- and write-position pointer 0502, 0506 per controller. Each controller 0501 has a write position pointer 0506 and a read position pointer 0502. Using multiplexer 0503, which of the read and write position pointers 0502, 0506 accesses memory 0504 is selected. Either a read access or a write access is selected via multiplexer 0503. The read/write signal of controllers 0501 is sent to memory 0504 via multiplexer 0507. The control signal of multiplexers 0507, 0505, 0503 goes from controllers 0501 via an arbiter 0508 to the multiplexers. Arbiter 0508 prevents several controllers from accessing multiplexers 0507, 0505, 0503 simultaneously.
  • FIG. 6 shows a ring memory 0601 and its connection with configuration elements 0602. Ring memory 0601 is connected via lines 0604, 0605, 0606. The addresses of the addressed cells 0607 are transmitted via 0604. Line 0605 transmits the configuration data from the ring memory. Via line 0606, cells 0607 transmit the feedback whether reconfiguration is possible. The data stored in the ring memory is entered in configuration element 0602. This configuration element 0602 determines the configuration of configurable elements 0603. Configurable elements 0603 may comprise logical units, ALUs, for example.
  • FIG. 7 shows a controller that may respond to different triggering events. The individual triggering events can be masked, so that only one triggering event is accepted at any time. This is achieved using multiplexer 0701. The trigger signal is stored with flip-flop 0704. Multiplexer 0702, which can be configured as a mask via AND gates (see FIG. 7 a), is used to process low active and high active triggering signals. The triggering signal stored in the flip-flop is relayed via line 0705 to obtain a clock signal, which is described in FIG. 8. The state machine 0703 receives its clock signal from the logic that generates the clock signal and, depending on its input signals, delivers an output signal and a reset signal to reset flip-flop 0704 and stop processing until the next trigger signal. The advantage of this implementation is the power savings when the clock is turned off, since state machine 0703 is then idle. An implementation where the clock is permanently applied and the state machine is controlled by the status of the command decoder and the run bit is also conceivable.
  • FIG. 7 a shows the masking of the trigger signals. The trigger signals and lines from A are connected to the inputs of AND gate 0706. The outputs of AND gate 0706 are OR-linked with 0707 to generate the output signal.
  • FIG. 8 shows the logic for generating the clock signal for the state machine. Another clock signal is generated in 0801 with the help of a PLL. Using multiplexer 0802, the normal chip clock or the clock of PLL 0801 can be selected. Signals C and B are sent to OR gate 0804. Signal C is generated as a result of a trigger event in the controller (see FIG. 7, 0705). Signal B originates from bit 1 of the command string (see FIG. 10, 1012). This bit has the function of a run flag, so that the controller continues to operate, independently of a trigger pulse, if the run flag is set. The output of OR gate 0804 is AND-linked with the output of multiplexer 0802 to generate the clock signal for the state machine.
  • FIG. 9 shows the connection between controller 0907, PLU 0902 with memory 0901, ring memory 0906, configurable elements 0905, and configuration elements 0908, as well as the internal cells 0903 used for the configuration. The internal cell 0903 used for configuration is shown here as a normal cell with configurable elements 0905 and configuration elements 0908. Ring memory 0906 is connected to configuration elements 0908 and is in turn controlled by controller 0907. Controller 0907 responds to different trigger pulses, which may also originate from the internal cell 0903 used for configuration. Controller 0907 informs PLU 0902, via feedback channel 0909, if new data is to be loaded into ring memory 0906 due to a trigger event. In addition to sending this feedback, controller 0907 also sends a signal to multiplexer 0904 and selects whether data is sent from PLU 0902 or internal cell 0903 used for configuration to the ring memory.
  • In addition to the configuration of the ring memory by the PLU, the ring memory can also be set as follows: Configurable element 0903 is wired so that it generates, alone or as the last element of a group of elements, records for ring memory 0906. It generates a trigger pulse, which advances the write position pointer in the ring memory. In this mode, multiplexer 0904 switches the data from 0903 through to the ring memory, while with a configuration by the PLU the data are switched through by the PLU. It would, of course, be conceivable that additional permanently implemented functional units might serve as sources of the configuration signals.
  • FIG. 10 shows the processing by the controller of the commands stored in the ring memories. 1001 represents the memory of the ring memory with the following bit assignment. Bit 0 identifies the record as a data or command string. Bit 1 identifies the run and stop modes. Bits 2-6 identify the command number coding the commands. Bit 7 tells whether the command is to be applied to the read or write position pointer. If the command affects no position pointer, bit 7 is undefined. The data needed for a command is stored in bits 8-n. Counters 1004, 1005 form the write and read position pointers of the ring memory. If the controller receives a trigger pulse, the state machine sends a pulse to the read position pointer. The write position pointer is not needed to read a command, but is only used for entering data in the ring memory. The selected read position pointer moves forward one position, and a new command is selected (bit 0=0). Now bits 2-6 and bit 7 are sent to command decoder 1002, are decoded, and the result is relayed to the state machine (1024), which recognizes the type of command and switches accordingly.
  • If it is a SKIP command, state machine 1011 sends a pulse to adder/subtractor 1006 so it can add/subtract the bit 8-n command string data to/from the data sent by counters 1004, 1005 via multiplexer 1003. Depending on bit 7, multiplexer 1003 selects the counter of write position pointer 1004 or the counter of read position pointer 1005. After the data has been added/subtracted, state machine 1011 activates gate 1010 and sends a receive signal to counter 1004, 1005. Thus the selected position pointer points as many positions forward or backward as set forth in the data of the SKIP command.
  • Upon a GOTO command, gate 1007 is activated by state machine 1011 so that the data goes to read position pointer 1005 or write position pointer 1004 and is received there.
  • Upon a MASK command, the data is received in a latch 1008 and stored there. This data is then available to the controller described in FIGS. 7/7 a via line A (1013) where it masks all the trigger inputs which should receive no trigger pulse.
  • Upon a WAIT command, an event is waited for as often as set forth in the data bits. If this command is registered by state machine 1011, it sends a pulse to wait cycle counter 1009 which receives the data. The wait cycle counter then counts one position downward for each event relayed by state machine 1011. As soon as it has counted to zero, the carry flag is set and sent to state machine 1011 (1023). The state machine then continues to operate due to the carry flag.
  • Upon a WAIT-GOTO command, the data providing the number of wait events is received in the wait cycle counters. After receipt of the number of events given in the data, the state machine activates gate 1007 and relays the jump position data to the selected counter.
  • The SWAP command is used for swapping two records between two positions of the ring memory. The address of the first record to be swapped is stored in latch 1017; the address of the second record is stored in latch 1018. The addresses are sent to multiplexers 1015 and 1016 of the read/write pointer. Initially, record 1 is selected via 1016 and stored in latch 1019; then record 2 is selected via 1016 and stored in 1020. The write pointer is first positioned on the first record via 1015, and the data formerly of the second record is stored via gate 1022. Then the write pointer is positioned on the second record via 1015 and the data formerly of the first record is stored via gate 1021.
  • State machine 1011 sends feedback to the PLU via 1014 (e.g., via a State-Back UNIT, see PACT02). The state machine sends a signal via this connection as soon as an LLBack command is registered.
  • Bit 1, used as a run flag, is sent to the controller for generating a clock signal, which is described in FIG. 8.
  • The NOP command is registered in the state machine, but no operation is performed.
  • FIG. 11 shows the processing of a data string stored in the ring memory. 1101 corresponds to 1001 in FIG. 10. Since this is a data string, bit 0 is set to one. Command decoder 1107 recognizes the data string as such and sends a query 1106 to the cell addressed in bits 2-6 to verify if reconfiguration is possible. The query is sent at the same time gate 1102 is activated, which causes the address of the cell to be transmitted. The cell shows via 1105 whether reconfiguration is possible. If so, the configuration data is transmitted to the cell via gate 1103. If no reconfiguration is possible, processing continues, and reconfiguration is attempted again in the next cycle in the ring memory. Another possible sequence would be the following: The state machine activates gates 1102 and 1103 and transmits the data to the cell addressed. If the cell can be reconfigured, the cell acknowledges receipt of the data via 1105. If no configuration is possible, the cell does not send a receive signal, and reconfiguration is attempted again in the next cycle of the ring memory.
  • FIG. 12 shows a group (functional element) 1202 of configurable elements 1201. The data is sent to the functional element via input bus 1204, and the results are sent forth via output bus 1205. Output bus 1205 is also connected to two memory arrays 1203, which operate alternately as a read or write memory. Their outputs are connected to input bus 1204. The entire circuit can be configured via a bus leading to switching tables 1206; the trigger signals are transmitted to the switching table and the configuration data is transmitted from the switching table via this bus. In addition to the function of the functional element, the write/read memory active at that time and the depth of the respective memory are set.
  • FIG. 12 a shows how external data 1204, i.e., data of another functional unit or from outside the unit, is computed in the functional element 1202 and then written into write memory 1210.
  • FIG. 12 b shows the next step after FIG. 12 a. Functional element 1202 and memories 1220, 1221 are reconfigured upon a trigger generated by the functional element or the memories or another unit and transmitted over 1206. Write memory 1210 is now configured as a read memory 1220 and delivers the data for the functional element. The results are stored in write memory 1221.
  • FIG. 12 c shows the step following FIG. 12 b. Functional element 1202 and memories 1230, 1231 were reconfigured upon a trigger generated by the functional element or the memories or another unit and transmitted over 1206. Write memory 1221 is now configured as a read memory 1230 and delivers the data to the functional element. The results are stored in write memory 1231. In this example, additional external operands 1204, i.e., from another functional unit or from outside the unit, are also processed.
  • FIG. 12 d shows the next step after FIG. 12 c. Functional element 1202 and memories 1203, 1240 were reconfigured upon a trigger generated by the functional element or the memories or another unit and transmitted over 1206. Write memory 1231 is now configured as a read memory 1240 and delivers the data to the functional element. The results are forwarded via output bus 1205.
  • FIG. 13 shows a circuit according to FIG. 12, where a memory with separate read and write pointers 1301 is used instead of the two memory arrays.
  • FIG. 14 shows memory 1401 according to FIG. 13. The record in front of read pointer 1402 has already been read or is free 1405. The pointer points to a free record. Data 1406 still to be read are located behind the read position pointer. A free area 1404 and data already re-written 1407 follow. Write position pointer 1403 points at a free record, which is either empty or already has been read. The memory can be configured as a ring memory, as described previously.
  • FIG. 15 shows a circuit according to FIG. 12, where both memory banks 1203 are present in duplicate. This makes it possible to store and then simultaneously process a plurality of results.
  • FIG. 15 a shows how external data 1204, i.e., from another functional unit or from outside the unit, is computed in functional element 1202 and then written in write memory 1510 via bus 1511.
  • FIG. 15 b shows the next step after FIG. 15 a. Functional element 1202 and memories 1203, 1510, 1520 have been reconfigured following a trigger generated by the functional element or the memories or another unit and transmitted over 1206. External data 1204, i.e., from another functional unit or from outside the unit, is computed in functional element 1202 and then written in write memory 1520 via bus 1521.
  • FIG. 15 c shows the next step after FIG. 15 b. Functional element 1202 and memories 1203, 1530, 1531, 1532 have been reconfigured following a trigger generated by the functional element or the memories or another unit and transmitted over 1206. Write memories 1510, 1520 are now configured as read memories 1531, 1532 and deliver several operands simultaneously to functional elements 1202. Each read memory 1531, 1532 is connected to 1202 via an independent bus system 1534, 1535. The results are either stored in write memory 1530 via 1533 or forwarded via 1205.
  • Glossary
  • ALU Arithmetic Logic Unit. Basic unit for data processing. The unit can
    perform arithmetic operations such as addition, subtraction, and
    occasionally also multiplication, division, expansions of series, etc. The
    unit can be configured as an integer unit of a floating-point unit. The unit
    can also perform logic operations such as AND, OR, as well as
    comparisons.
    data string A data string is a series of bits, of any length. This series of bits represents
    a processing unit for a system. Both commands for processors or similar
    components and data can be coded in a data string.
    DFP Data flow processor according to German Patent No. DE 44 16 881.
    DPGA Dynamically Configurable FPGAs. Related art.
    D Flip-Flop Memory element, which stores a signal at the rising edge of a cycle.
    EALU Expanded Arithmetic Logic Unit, ALU which has been expanded to
    perform special functions needed or convenient for the operation of a data
    processing device according to German Patent Application No. DE
    441 16 881 A1. These are, in particular, counters.
    Elements Generic concept for all enclosed units used as a part in an electronic unit.
    Thus, the following are defined as elements:
    configurable cells of all types
    clusters
    RAM blocks
    logics
    arithmetic units
    registers
    multiplexers
    I/O pins of a chip
    Event An event can be analyzed by a hardware element in any manner suitable
    for the application and trigger an action as a response to this analysis.
    Thus, for example, the following are defined as events:
    clock pulse of a CPU
    internal or external interrupt signal
    trigger signal from other elements within the unit
    comparison of a data stream and/or a command stream with a value
    input/output events
    run, overrun, reset of a counter
    analysis of a comparison
    flag Status bit in a register showing a status.
    FPGA Programmable logic unit. Related art.
    gate Group of transistors that performs a basic logic function. Basic functions
    include NAND, NOR. Transmission gates.
    configurable A configurable element represents a component of a logic unit, which can
    element be set for a special function using a configuration string. Configurable
    elements are therefore all types of RAM cells, multiplexers, arithmetic
    logic units, registers, and all types of internal and external interconnecting
    units, etc.
    configure Setting the function and interconnections of a logic unit, an FPGA cell or a
    PAE (see reconfigure).
    configuration Any set of configuration strings.
    data
    configuration The configuration memory contains one or more configuration strings.
    memory
    configuration A configuration string consists of a series of bits, of any length. This bit
    string series represents a valid setting for the element to be configured, so that an
    operable unit is obtained.
    PLU Unit for configuring and reconfiguring the PAE. Constituted by a
    microcontroller designed specifically for this purpose.
    latch Memory element that usually relays a signal transparently during the H
    level and stores it during the L level. Latches where the level function is
    reversed are used in some PAEs. Here an inverter is normally connected
    before the cycle of a normal latch.
    read position Address of the current record for read access within a FIFO or a ring
    pointer memory.
    logic cells Cells used in DFPs, FPGAs, and DPGAs, performing simple logic and
    arithmetic functions, depending on their configuration.
    oversampling A clock runs with a frequency that is a multiple of the base clock,
    synchronously with the same. The faster clock is usually generated by a
    PLL.
    PLL Phase Locked Loop. Unit for generating a multiple of a clock frequency on
    the basis of a base clock.
    PLU Units for configuring and reconfiguring the PAE. Constituted by a
    microcontroller specifically designed for this purpose.
    ring memory Memory with its own read/write position pointer, which-upon reaching the
    end of the memory-is positioned at the beginning of the memory. An
    endless ring-shaped memory is thus obtained.
    RS flip-flop Reset/Set flip-flop. Memory element that can be switched by two signals.
    write position Address of the current record for write access within a FIFO or ring
    pointer memory.
    State-Back Unit that controls the feedback of status signals to the PLU, comprising a
    unit multiplexer and an open-collector bus driver element.
    switching A switching table is a ring memory, which is addressed by a controller.
    table The records of a switching table may contain any configuration strings.
    The controller can execute commands. The switching table responds to
    trigger signals and reconfigures configurable elements using a record in a
    ring memory.
    gate Switch that forwards or blocks a signal. Simple comparison: relay.
    reconfigure New configuration of any number of PAEs, while any remaining number
    of PAEs continue their functions (see configure).
    processing A processing cycle describes the time required by a unit to go from a
    cycle specific and/or valid state into the next specific and/or valid state.
    state machine Logic that can assume different states. The transition between the states
    depends on different input parameters. These machines are used for
    controlling complex functions and correspond to the related art.
  • Conventions
  • Naming Conventions
  • unit UNIT
    mode MODE
    multiplexer MUX
    negated signal not-
    register visible to PLU PLUREG
    internal register REG
    shift register sft
  • Function Conventions
  • shift registersft
  • AND function &
    A B Q
    0 0 0
    0 1 0
    1 0 0
    1 1 1
  • OR function#
    A B Q
    0 0 0
    0 1 1
    1 0 1
    1 1 1
  • NOT function!
    A Q
    0 1
    1 0
  • GATE functionG
    EN D Q
    0 0
    0 1
    1 0 0
    1 1 1

Claims (28)

1. A field programmable gate array (FPGA) device, comprising
configurable elements;
a unit for configuring the configurable elements; and
at least two memory units;
wherein:
at least some of the configurable elements are configurable logic elements;
at least some of the configurable elements are configurable ALU elements comprise an ALU unit;
the at least two memories store data processed by at least some of the configurable ALU elements.
2. The field programmable gate array according to claim 1, wherein each of the at least some of the configurable elements receives its configuration data during operation.
3. The field programmable gate array according to claim 1, wherein each of the at least some of the configurable elements receives its configuration data during operation from other configurable elements.
4. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units supports a FIFO mode.
5. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units supports simultaneous write and read access.
6. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units supports separate write pointers and read pointers.
7. The field programmable gate array according to claim 6, wherein at least one of the memory units supports simultaneous write and read access.
8. The field programmable gate array according to claim 6, wherein at least one of the memory units is configurable as read memory.
9. The field programmable gate array according to claim 6, wherein at least one of the memory units is configurable as write memory.
10. The field programmable gate array according to claim 6, wherein at least one of the memory units is alternatively configured as read or write memory.
11. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units supports double buffering.
12. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units is configurable as read memory.
13. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units is configurable as write memory.
14. The field programmable gate array according to any one of claims 1, 2, and 3, wherein at least one of the memory units is alternatively configured as read or write memory.
15. A runtime programmable data processing device, comprising:
configurable elements;
a unit for configuring the configurable elements; and
at least two memory units;
wherein:
at least some of the configurable elements are configurable ALU elements comprising an ALU unit;
the at least two memory units store data processed by at least some of the configurable ALU elements; and
at least some of the configurable elements receive configuration data during operation from other configurable elements.
16. The runtime programmable data processing device according to claim 15, wherein at least one of the configurable elements is configured as a controller providing configuration data during the operation to at least some others of the configurable elements.
17. The runtime programmable data processing device according to claim 15, wherein at least one of the configurable elements is configured as a sequencer providing configuration data during operation to at least some others of the configurable elements.
18. The runtime programmable data processing device according to claim 15, wherein a configurable memory integrated in the runtime programmable data processing device is configured to provide configuration data during the operation to at least some others of the configurable elements.
19. The runtime programmable data processing device according to claim 18, wherein the configurable memory is addressable.
20. The runtime programmable data processing device according to claim 19, wherein the configurable memory is cyclically addressed.
21. The runtime programmable data processing device according to any one of claims 15, 16, 17, 18, 19, and 20, wherein the runtime programmable processing device is a Field Programmable Gate Array (FPGA).
22. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units supports a FIFO mode.
23. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units supports separate write pointers and read pointers.
24. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units supports simultaneous write and read access.
25. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units supports double buffering.
26. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units is configurable as read memory.
27. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units is configurable as write memory.
28. The runtime programmable data processing device according to claim 15, wherein at least one of the memory units is alternatively configured as read or write memory.
US12/367,055 1996-12-27 2009-02-06 Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like) Abandoned US20090144485A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DEDE19654846.2 1996-12-27
DE1996154846 DE19654846A1 (en) 1996-12-27 1996-12-27 A method for automatic dynamic reloading of Datenflußprozessoren (DFP) and modules having a two- or multi-dimensional programmable cell structure (FPGAs, DPGAs, o. The like).
US09/613,217 US6477643B1 (en) 1996-12-27 2000-07-10 Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US10/265,846 US7028107B2 (en) 1996-12-27 2002-10-07 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US11/246,617 US7822881B2 (en) 1996-12-27 2005-10-07 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US12/367,055 US20090144485A1 (en) 1996-12-27 2009-02-06 Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/367,055 US20090144485A1 (en) 1996-12-27 2009-02-06 Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/246,617 Continuation US7822881B2 (en) 1996-12-27 2005-10-07 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)

Publications (1)

Publication Number Publication Date
US20090144485A1 true US20090144485A1 (en) 2009-06-04

Family

ID=7816473

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/246,617 Expired - Fee Related US7822881B2 (en) 1996-12-27 2005-10-07 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US12/367,055 Abandoned US20090144485A1 (en) 1996-12-27 2009-02-06 Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/246,617 Expired - Fee Related US7822881B2 (en) 1996-12-27 2005-10-07 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)

Country Status (4)

Country Link
US (2) US7822881B2 (en)
EP (1) EP1329816B1 (en)
JP (2) JP3961028B2 (en)
AT (1) AT243390T (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT243390T (en) * 1996-12-27 2003-07-15 Pact Inf Tech Gmbh A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
EP1676208A2 (en) * 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
TWI233053B (en) * 2003-11-06 2005-05-21 Via Tech Inc Apparatus and method for initializing an elastic buffer
JP2007235082A (en) 2006-02-02 2007-09-13 E I Du Pont De Nemours & Co Paste for solar battery electrode
US8046727B2 (en) * 2007-09-12 2011-10-25 Neal Solomon IP cores in reconfigurable three dimensional integrated circuits
JP5294304B2 (en) * 2008-06-18 2013-09-18 日本電気株式会社 Reconfigurable electronic circuit device
US7949980B1 (en) * 2008-07-31 2011-05-24 Altera Corporation Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities
WO2011123151A1 (en) * 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US8650514B2 (en) 2010-06-23 2014-02-11 Tabula, Inc. Rescaling
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US9203397B1 (en) 2011-12-16 2015-12-01 Altera Corporation Delaying start of user design execution
US9000801B1 (en) 2013-02-27 2015-04-07 Tabula, Inc. Implementation of related clocks
JP6310260B2 (en) * 2014-01-20 2018-04-11 株式会社荏原製作所 Adjusting device for adjusting the plurality of processing units in the substrate processing apparatus, and a substrate processing apparatus having the adjustment device
US9460007B1 (en) * 2014-09-24 2016-10-04 Xilinx, Inc. Programmable hardware blocks for time-sharing arithmetic units using memory mapping of periodic functions

Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US489810A (en) * 1893-01-10 Pedal attachment for organs or pianos
US2067477A (en) * 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
US3242998A (en) * 1962-05-28 1966-03-29 Wolf Electric Tools Ltd Electrically driven equipment
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US4151611A (en) * 1976-03-26 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Power supply control system for memory systems
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) * 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US4910665A (en) * 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5010401A (en) * 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5099447A (en) * 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5103311A (en) * 1988-01-11 1992-04-07 U.S. Philips Corporation Data processing module and video processing system incorporating same
US5109503A (en) * 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5204935A (en) * 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5287532A (en) * 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5294119A (en) * 1991-09-27 1994-03-15 Taylor Made Golf Company, Inc. Vibration-damping device for a golf club
US5301344A (en) * 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US5301284A (en) * 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5303172A (en) * 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
US5379444A (en) * 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5408643A (en) * 1991-02-01 1995-04-18 Nec Corporation Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared
US5410723A (en) * 1989-11-21 1995-04-25 Deutsche Itt Industries Gmbh Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5485104A (en) * 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5491353A (en) * 1989-03-17 1996-02-13 Xilinx, Inc. Configurable cellular array
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5502838A (en) * 1994-04-28 1996-03-26 Consilium Overseas Limited Temperature management for integrated circuits
US5504439A (en) * 1994-04-01 1996-04-02 Xilinx, Inc. I/O interface cell for use with optional pad
US5506998A (en) * 1991-03-20 1996-04-09 Fujitsu Limited Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data
US5510730A (en) * 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US5600597A (en) * 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5602999A (en) * 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US5606698A (en) * 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5608342A (en) * 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5617577A (en) * 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5619720A (en) * 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
US5706482A (en) * 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5705938A (en) * 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5717890A (en) * 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5734869A (en) * 1995-09-06 1998-03-31 Chen; Duan-Ping High speed logic circuit simulator
US5745734A (en) * 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US5870620A (en) * 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5895487A (en) * 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US5898602A (en) * 1996-01-25 1999-04-27 Xilinx, Inc. Carry chain circuit with flexible carry function for implementing arithmetic and logical functions
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6049866A (en) * 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6173419B1 (en) * 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US6188650B1 (en) * 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US20020010853A1 (en) * 1995-08-18 2002-01-24 Xilinx, Inc. Method of time multiplexing a programmable logic device
US20020013861A1 (en) * 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US6353479B1 (en) * 1999-06-29 2002-03-05 Hewlett-Packard Company Media-type encoding and print mode selection
US6507898B1 (en) * 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6512804B1 (en) * 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US20030056062A1 (en) * 2001-09-14 2003-03-20 Prabhu Manohar K. Preemptive write back controller
US6538470B1 (en) * 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US20030070059A1 (en) * 2001-05-30 2003-04-10 Dally William J. System and method for performing efficient conditional vector operations for data parallel architectures
US6681388B1 (en) * 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US20040039880A1 (en) * 2002-08-23 2004-02-26 Vladimir Pentkovski Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US6725334B2 (en) * 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US20040078548A1 (en) * 2000-12-19 2004-04-22 Claydon Anthony Peter John Processor architecture
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US20050091468A1 (en) * 2003-10-28 2005-04-28 Renesas Technology America, Inc. Processor for virtual machines and method therefor
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7028107B2 (en) * 1996-12-27 2006-04-11 Pact Xpp Technologies Ag Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US7036114B2 (en) * 2001-08-17 2006-04-25 Sun Microsystems, Inc. Method and apparatus for cycle-based computation
US7346644B1 (en) * 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US7650448B2 (en) * 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7657877B2 (en) * 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data

Family Cites Families (439)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1253309A (en) 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
DE2057312A1 (en) 1970-11-21 1972-05-25 Bhs Bayerische Berg Planetary gear with load pressure compensation
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US4233667A (en) 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4578771A (en) * 1980-12-29 1986-03-25 International Business Machines Corporation Dynamically reprogrammable array logic system
US4442508A (en) 1981-08-05 1984-04-10 General Instrument Corporation Storage cells for use in two conductor data column storage logic arrays
US4590583A (en) 1982-07-16 1986-05-20 At&T Bell Laboratories Coin telephone measurement circuitry
US4667190A (en) * 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
JPH0222423B2 (en) 1982-08-25 1990-05-18 Nippon Electric Co
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US5123109A (en) 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4870302A (en) 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
JPS60198618A (en) 1984-03-21 1985-10-08 Oki Electric Ind Co Ltd Dynamic logical circuit
US4761755A (en) 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4623997A (en) 1984-12-13 1986-11-18 United Technologies Corporation Coherent interface with wraparound receive and transmit memories
EP0190813B1 (en) 1985-01-29 1991-09-18 Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Processing cell for fault tolerant arrays
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5247689A (en) 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5015884A (en) 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4972314A (en) 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4967340A (en) 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
GB8517376D0 (en) 1985-07-09 1985-08-14 Jesshope C R Processor array
EP0211360B1 (en) 1985-07-27 1993-09-29 Dai Nippon Insatsu Kabushiki Kaisha Ic card
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US5021947A (en) 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US4882687A (en) 1986-03-31 1989-11-21 Schlumberger Technology Corporation Pixel processor
US5034914A (en) * 1986-05-15 1991-07-23 Aquidneck Systems International, Inc. Optical disk data storage method and apparatus with buffered interface
GB8612396D0 (en) 1986-05-21 1986-06-25 Hewlett Packard Ltd Chain-configured interface bus system
US4791603A (en) 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
US4860201A (en) 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US4884231A (en) 1986-09-26 1989-11-28 Performance Semiconductor Corporation Microprocessor system with extended arithmetic logic unit
FR2606184B1 (en) 1986-10-31 1991-11-29 Thomson Csf Computing device reconfigurable
US5226122A (en) 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
CA1299757C (en) 1987-08-28 1992-04-28 Brent Cameron Beardsley Device initiated partial system quiescing
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
US4918690A (en) 1987-11-10 1990-04-17 Echelon Systems Corp. Network and intelligent cell for providing sensing, bidirectional communications and control
USRE34444E (en) 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
NL8800071A (en) 1988-01-13 1989-08-01 Philips Nv Data processor system and video processor system, provided with such a data processor system.
DE68917326D1 (en) 1988-01-20 1994-09-15 Advanced Micro Devices Inc Organizing an integrated cache for flexible application to support multi-processor operations.
US4959781A (en) 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
JPH06101043B2 (en) 1988-06-30 1994-12-12 三菱電機株式会社 Micro computer
WO1990001192A1 (en) 1988-07-22 1990-02-08 United States Department Of Energy Data flow machine for data driven computing
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
ES2047629T3 (en) 1988-09-22 1994-03-01 Siemens Ag Circuit arrangement for telecommunications switching installations, especially telephone switching facilities temporary-pcm multiplexing with central field coupling and coupling fields partially connected.
AT131643T (en) 1988-10-05 1995-12-15 Quickturn Systems Inc A method of using an electronically reconfigurable gate array logic and device manufactured thereby
DE68926783D1 (en) 1988-10-07 1996-08-08 Martin Marietta Corp Parallel data processor
US5014193A (en) 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5136717A (en) 1988-11-23 1992-08-04 Flavors Technology Inc. Realtime systolic, multiple-instruction, single-data parallel computer system
US5041924A (en) * 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
US5237686A (en) * 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
JP2584673B2 (en) 1989-06-09 1997-02-26 株式会社日立製作所 Logic tester having a test data changing circuit
US5343406A (en) 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5212652A (en) 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5128559A (en) 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
JP2968289B2 (en) 1989-11-08 1999-10-25 株式会社リコー Central processing unit
GB8925721D0 (en) 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
US5212777A (en) 1989-11-17 1993-05-18 Texas Instruments Incorporated Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
US5125801A (en) 1990-02-02 1992-06-30 Isco, Inc. Pumping system
US5142469A (en) 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5555201A (en) 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
EP0463721A3 (en) 1990-04-30 1993-06-16 Gennum Corporation Digital signal processing device
WO1991017507A1 (en) 1990-05-07 1991-11-14 Mitsubishi Denki Kabushiki Kaisha Parallel data processing system
US5198705A (en) 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
US5111079A (en) 1990-06-29 1992-05-05 Sgs-Thomson Microelectronics, Inc. Power reduction circuit for programmable logic device
SE9002558D0 (en) 1990-08-02 1990-08-02 Carlstedt Elektronik Ab processor
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
EP0485690B1 (en) 1990-11-13 1999-05-26 International Business Machines Corporation Parallel associative processor system
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5708836A (en) 1990-11-13 1998-01-13 International Business Machines Corporation SIMD/MIMD inter-processor communication
US5588152A (en) 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5590345A (en) 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5794059A (en) 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
CA2051222C (en) 1990-11-30 1998-05-05 Pradeep S. Sindhu Consistent packet switched memory bus for shared memory multiprocessors
US5613128A (en) 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
US5212716A (en) 1991-02-05 1993-05-18 International Business Machines Corporation Data edge phase sorting circuits
US5218302A (en) 1991-02-06 1993-06-08 Sun Electric Corporation Interface for coupling an analyzer to a distributorless ignition system
JPH07168610A (en) 1991-02-22 1995-07-04 Siemens Ag Memory programmable controller and operation method therefor
JPH04290155A (en) 1991-03-19 1992-10-14 Fujitsu Ltd Parallel data processing system
US5617547A (en) 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
WO1992018935A1 (en) 1991-04-09 1992-10-29 Fujitsu Limited Data processor and data processing method
US5551033A (en) 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
AU2158692A (en) 1991-05-24 1993-01-08 British Technology Group Usa, Inc. Optimizing compiler for computers
US5659797A (en) 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
JP3259969B2 (en) 1991-07-09 2002-02-25 株式会社東芝 Cache memory controller
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5317209A (en) 1991-08-29 1994-05-31 National Semiconductor Corporation Dynamic three-state bussing capability in a configurable logic array
US5581731A (en) 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
FR2686175B1 (en) 1992-01-14 1996-12-20 Andre Thepaut multiprocessor data processing system.
US5412795A (en) 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
JP2791243B2 (en) 1992-03-13 1998-08-27 株式会社東芝 Large-scale integrated circuit using inter-hierarchy synchronizing system and this
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
JP2647327B2 (en) 1992-04-06 1997-08-27 インターナショナル・ビジネス・マシーンズ・コーポレイション Massively parallel computing system device
US5611049A (en) 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
WO1993024895A2 (en) 1992-06-04 1993-12-09 Xilinx, Inc. Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
DE4221278C2 (en) 1992-06-29 1996-02-29 Martin Vorbach Busgekoppeltes multicomputer system
US5475803A (en) 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
JP3032382B2 (en) 1992-07-13 2000-04-17 シャープ株式会社 Sampling frequency converting apparatus of the digital signal
US5365125A (en) 1992-07-23 1994-11-15 Xilinx, Inc. Logic cell for field programmable gate array having optional internal feedback and optional cascade
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5802290A (en) 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5581778A (en) 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
AT237861T (en) 1992-09-03 2003-05-15 Sony Corp Data recording apparatus and method
US5572710A (en) 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
JPH06180653A (en) 1992-10-02 1994-06-28 Hudson Soft Co Ltd Interruption processing method and device therefor
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5311079A (en) 1992-12-17 1994-05-10 Ditlow Gary S Low power, high performance PLA
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
GB9303084D0 (en) 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH06276086A (en) 1993-03-18 1994-09-30 Fuji Xerox Co Ltd Field programmable gate array
US5548773A (en) 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5596742A (en) 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5418953A (en) 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US5473266A (en) 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh A method of operating a data processing device
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
IT1260848B (en) 1993-06-11 1996-04-23 Finmeccanica Spa Multiprocessor System
US5444394A (en) 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
JPH0736858A (en) 1993-07-21 1995-02-07 Hitachi Ltd Signal processor
CA2129882A1 (en) 1993-08-12 1995-02-13 Soheil Shams Dynamically reconfigurable interprocessor communication network for simd multiprocessors and apparatus implementing same
US5457644A (en) * 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
US5440538A (en) 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
GB2282244B (en) 1993-09-23 1998-01-14 Advanced Risc Mach Ltd Integrated circuit
US6219688B1 (en) 1993-11-30 2001-04-17 Texas Instruments Incorporated Method, apparatus and system for sum of plural absolute differences
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5535406A (en) * 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
DE69519426D1 (en) 1994-03-22 2000-12-21 Hyperchip Inc Cell-based fault-tolerant architecture with advantageous use of the non-allocated redundant cells
US5561738A (en) 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5430687A (en) 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5781756A (en) 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5896551A (en) 1994-04-15 1999-04-20 Micron Technology, Inc. Initializing and reprogramming circuitry for state independent memory array burst operations control
US5426378A (en) * 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
JP2671804B2 (en) 1994-05-27 1997-11-05 日本電気株式会社 Hierarchical resource management method
US5532693A (en) 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
EP0690378A1 (en) 1994-06-30 1996-01-03 Tandem Computers Incorporated Tool and method for diagnosing and correcting errors in a computer programm
JP3308770B2 (en) 1994-07-22 2002-07-29 三菱電機株式会社 The calculation method in an information processing apparatus and an information processing apparatus
US5600845A (en) 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
JP3365581B2 (en) 1994-07-29 2003-01-14 富士通株式会社 Self-repair function with an information processing apparatus
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
US5513366A (en) 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
US5450022A (en) 1994-10-07 1995-09-12 Xilinx Inc. Structure and method for configuration of a field programmable gate array
EP0707269A1 (en) 1994-10-11 1996-04-17 International Business Machines Corporation Cache coherence network for a multiprocessor data processing system
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5815726A (en) 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
JPH08137824A (en) 1994-11-15 1996-05-31 Mitsubishi Electric Corp Single-chip microcomputer with built-in self-test function
EP0721157A1 (en) 1994-12-12 1996-07-10 Advanced Micro Devices Inc. Microprocessor with selectable clock frequency
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5696791A (en) 1995-01-17 1997-12-09 Vtech Industries, Inc. Apparatus and method for decoding a sequence of digitally encoded data
US5532957A (en) 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5862403A (en) * 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5675743A (en) 1995-02-22 1997-10-07 Callisto Media Systems Inc. Multi-media server
JP3351452B2 (en) * 1995-03-08 2002-11-25 日本電信電話株式会社 Programmable gate array
US5757207A (en) 1995-03-22 1998-05-26 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5570040A (en) 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
JP3313007B2 (en) 1995-04-14 2002-08-12 三菱電機システムエル・エス・アイ・デザイン株式会社 Micro computer
US5794062A (en) 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6077315A (en) 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
US5933642A (en) 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
EP0823091A1 (en) 1995-04-28 1998-02-11 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US5701091A (en) 1995-05-02 1997-12-23 Xilinx, Inc. Routing resources for hierarchical FPGA
US5541530A (en) 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5649179A (en) 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5821774A (en) 1995-05-26 1998-10-13 Xilinx, Inc. Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
US5671432A (en) 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US5652529A (en) 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
US5646544A (en) * 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5815715A (en) 1995-06-05 1998-09-29 Motorola, Inc. Method for designing a product having hardware and software components and product therefor
US5889982A (en) 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5559450A (en) 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
US5978583A (en) 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
US5649176A (en) 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
GB2304438A (en) 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
US5778439A (en) 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5583450A (en) 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
US5737565A (en) 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US5737516A (en) 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
US6430309B1 (en) 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US5652894A (en) 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5754827A (en) 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5815004A (en) 1995-10-16 1998-09-29 Xilinx, Inc. Multi-buffered configurable logic block output lines in a field programmable gate array
US5642058A (en) 1995-10-16 1997-06-24 Xilinx , Inc. Periphery input/output interconnect structure
US5656950A (en) 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5675262A (en) 1995-10-26 1997-10-07 Xilinx, Inc. Fast carry-out scheme in a field programmable gate array
US5633830A (en) 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5732209A (en) 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US5773994A (en) 1995-12-15 1998-06-30 Cypress Semiconductor Corp. Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
JPH09231788A (en) 1995-12-19 1997-09-05 Fujitsu Ltd Shift register and programmable logic circuit and programmable logic circuit system
US5804986A (en) 1995-12-29 1998-09-08 Cypress Semiconductor Corp. Memory in a programmable logic device
JP3247043B2 (en) 1996-01-12 2002-01-15 株式会社日立製作所 The information processing system and logic lsi performing fault detection in internal signal
US5760602A (en) 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
JP2795244B2 (en) 1996-01-17 1998-09-10 日本電気株式会社 Program debugging system
US5854918A (en) 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5936424A (en) 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5635851A (en) 1996-02-02 1997-06-03 Xilinx, Inc. Read and writable data bus particularly for programmable logic devices
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
KR0165515B1 (en) 1996-02-17 1999-01-15 김광호 Fifo method and apparatus of graphic data
GB9604496D0 (en) 1996-03-01 1996-05-01 Xilinx Inc Embedded memory for field programmable gate array
US6020758A (en) 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US5841973A (en) 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US6279077B1 (en) 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6311265B1 (en) 1996-03-25 2001-10-30 Torrent Systems, Inc. Apparatuses and methods for programming parallel computers
US5687325A (en) 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US6173434B1 (en) 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5960200A (en) 1996-05-03 1999-09-28 I-Cube System to transition an enterprise to a distributed infrastructure
US5784636A (en) 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5892370A (en) 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
EP0978051A1 (en) 1996-06-21 2000-02-09 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US6785826B1 (en) 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6023742A (en) 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
CN1129078C (en) 1996-08-19 2003-11-26 三星电子株式会社 Integrated digital signal processor
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US6624658B2 (en) 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US5694602A (en) 1996-10-01 1997-12-02 The United States Of America As Represented By The Secretary Of The Air Force Weighted system and method for spatial allocation of a parallel load
SG125044A1 (en) 1996-10-14 2006-09-29 Mitsubishi Gas Chemical Co Oxygen absorption composition
US5901279A (en) 1996-10-18 1999-05-04 Hughes Electronics Corporation Connection of spares between multiple programmable devices
US6247147B1 (en) 1997-10-27 2001-06-12 Altera Corporation Enhanced embedded logic analyzer
US5892962A (en) 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US5844422A (en) 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US6005410A (en) 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations used in processors (CPU's), multiprocessor systems, Datenflußprozessoren (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration method for programmable devices at runtime
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
AT243390T (en) * 1996-12-27 2003-07-15 Pact Inf Tech Gmbh A method for automatic dynamic reloading of data flow processors (dfps) and modules having a two- or multi-dimensional programmable cell structure (FPGAs DPGAs, or the like.)
US6427156B1 (en) 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
EP0858167A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor device
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US5865239A (en) 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh A method for self-synchronization of configurable elements of a programmable block
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (en) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internal bus system for DFPs, and modules having a two- or multi-dimensional programmable cell structure, to cope with large amounts of data with high connectivity expenses
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5927423A (en) 1997-03-05 1999-07-27 Massachusetts Institute Of Technology Reconfigurable footprint mechanism for omnidirectional vehicles
US5857097A (en) 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US6125408A (en) 1997-03-10 2000-09-26 Compaq Computer Corporation Resource type prioritization in generating a device configuration
US5884075A (en) 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US6011407A (en) 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US6240502B1 (en) 1997-06-25 2001-05-29 Sun Microsystems, Inc. Apparatus for dynamically reconfiguring a processor
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US5966534A (en) 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6437441B1 (en) 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6038656A (en) 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US6020760A (en) 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6282701B1 (en) 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US6170051B1 (en) 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6085317A (en) 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US7152027B2 (en) 1998-02-17 2006-12-19 National Instruments Corporation Reconfigurable test system
JP3612186B2 (en) 1997-09-19 2005-01-19 株式会社ルネサステクノロジ Data processing equipment
US6539415B1 (en) 1997-09-24 2003-03-25 Sony Corporation Method and apparatus for the allocation of audio/video tasks in a network system
US5966143A (en) 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
JP4128251B2 (en) 1997-10-23 2008-07-30 富士通株式会社 Wiring density predicting method and cell placement device
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6108760A (en) 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
JP4197755B2 (en) 1997-11-19 2008-12-17 富士通株式会社 Signal transmission system, the receiver circuit of the signal transmission system, and a semiconductor memory device the signal transmission system is applied
US6212650B1 (en) 1997-11-24 2001-04-03 Xilinx, Inc. Interactive dubug tool for programmable circuits
US6091263A (en) 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
DE69827589T2 (en) 1997-12-17 2005-11-03 Elixent Ltd. Configurable processing arrangement and method for use of this arrangement is to establish a central unit
DE69841256D1 (en) 1997-12-17 2009-12-10 Panasonic Corp Masking command to command streams forwarded to a processor
DE69737750T2 (en) 1997-12-17 2008-03-06 Hewlett-Packard Development Co., L.P., Houston First and second processors used method
DE69834942T2 (en) 1997-12-17 2007-06-06 Panasonic Europe Ltd., Uxbridge Means for multiplying
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6049222A (en) 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6301706B1 (en) 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6105106A (en) 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6130551A (en) 1998-01-19 2000-10-10 Vantis Corporation Synthesis-friendly FPGA architecture with variable length and variable timing interconnect
US6034538A (en) 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
AU2562899A (en) 1998-01-26 1999-08-09 Chameleon Systems, Inc. Reconfigurable logic for table lookup
KR100572945B1 (en) 1998-02-04 2006-04-24 텍사스 인스트루먼츠 인코포레이티드 Digital signal processor with efficiently connectable hardware co-processor
US6086628A (en) 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6198304B1 (en) 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
US6088800A (en) 1998-02-27 2000-07-11 Mosaid Technologies, Incorporated Encryption processor with shared memory interconnect
US6154049A (en) 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
US6374286B1 (en) 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6421808B1 (en) 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6084429A (en) 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6092174A (en) 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
JP3123977B2 (en) 1998-06-04 2001-01-15 技術研究組合新情報処理開発機構 Programmable function block
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
DE69803373T2 (en) 1998-07-06 2002-08-14 Hewlett Packard Co Wiring of cells in logical fields
US6421809B1 (en) 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
DE19835189C2 (en) 1998-08-04 2001-02-08 Unicor Rohrsysteme Gmbh An apparatus for continuously producing seamless plastic pipes
US6205458B1 (en) 1998-09-21 2001-03-20 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
DE69910826T2 (en) 1998-11-20 2004-06-17 Altera Corp., San Jose Computer system having a reconfigurable programmable logic device
US6977649B1 (en) 1998-11-23 2005-12-20 3Dlabs, Inc. Ltd 3D graphics rendering with selective read suspend
US6044030A (en) 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6434695B1 (en) 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6757847B1 (en) 1998-12-29 2004-06-29 International Business Machines Corporation Synchronization for system analysis
JP3585800B2 (en) 1999-01-13 2004-11-04 株式会社東芝 The information processing apparatus
US6539438B1 (en) 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6490695B1 (en) 1999-01-22 2002-12-03 Sun Microsystems, Inc. Platform independent memory image analysis architecture for debugging a computer program
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6286134B1 (en) 1999-04-23 2001-09-04 Sun Microsystems, Inc. Instruction selection in a multi-platform environment
US6381624B1 (en) 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
US6298472B1 (en) 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US7007096B1 (en) 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US6748440B1 (en) 1999-05-12 2004-06-08 Microsoft Corporation Flow of streaming data through multiple processing modules
US6211697B1 (en) 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6757892B1 (en) 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
JP3420121B2 (en) 1999-06-30 2003-06-23 Necエレクトロニクス株式会社 Nonvolatile semiconductor memory device
US6347346B1 (en) 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
GB2352548B (en) 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US6745317B1 (en) 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
US6341318B1 (en) 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6204687B1 (en) 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6507947B1 (en) 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6438747B1 (en) 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6349346B1 (en) 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
DE19946752A1 (en) 1999-09-29 2001-04-12 Infineon Technologies Ag Reconfigurable gate array
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6665758B1 (en) 1999-10-04 2003-12-16 Ncr Corporation Software sanity monitor
US6434642B1 (en) 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
JP2001167066A (en) 1999-12-08 2001-06-22 Nec Corp Inter-processor communication method and multiprocessor system
US6633181B1 (en) 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
EP1115204B1 (en) 2000-01-07 2009-04-22 Nippon Telegraph and Telephone Corporation Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
JP2001202236A (en) 2000-01-20 2001-07-27 Fuji Xerox Co Ltd Data processing method for programmable logic circuit device and the same device and information processing system and circuit reconstituting method for the same device
US20020031166A1 (en) 2000-01-28 2002-03-14 Ravi Subramanian Wireless spread spectrum communication platform using dynamically reconfigurable logic
US6496971B1 (en) 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6487709B1 (en) 2000-02-09 2002-11-26 Xilinx, Inc. Run-time routing for programmable logic devices
US6519674B1 (en) 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
WO2001063434A1 (en) 2000-02-24 2001-08-30 Bops, Incorporated Methods and apparatus for dual-use coprocessing/debug interface
JP3674515B2 (en) 2000-02-25 2005-07-20 日本電気株式会社 Array-type processor
US6539477B1 (en) 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
US6657457B1 (en) 2000-03-15 2003-12-02 Intel Corporation Data transfer on reconfigurable chip
US6871341B1 (en) 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US6362650B1 (en) 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6373779B1 (en) 2000-05-19 2002-04-16 Xilinx, Inc. Block RAM having multiple configurable write modes for use in a field programmable gate array
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
DE50115584D1 (en) 2000-06-13 2010-09-16 Krass Maren Pipeline ct protocols and communication
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
US6285624B1 (en) 2000-07-08 2001-09-04 Han-Ping Chen Multilevel memory access method
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
JP2002041489A (en) 2000-07-25 2002-02-08 Mitsubishi Electric Corp Synchronizing signal generation circuit, processor system using the same and synchronizing signal generating method
US6538468B1 (en) 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US6542844B1 (en) 2000-08-02 2003-04-01 International Business Machines Corporation Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits
US6754805B1 (en) 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
AU8116401A (en) 2000-08-07 2002-02-18 Altera Corp Inter-device communication interface
US7249351B1 (en) 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
US6829697B1 (en) 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US20040015899A1 (en) 2000-10-06 2004-01-22 Frank May Method for processing data
US6525678B1 (en) 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US7595659B2 (en) 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
DE10129237A1 (en) 2000-10-09 2002-04-18 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20020045952A1 (en) 2000-10-12 2002-04-18 Blemel Kenneth G. High performance hybrid micro-computer
US6398383B1 (en) 2000-10-30 2002-06-04 Yu-Hwei Huang Flashlight carriable on one's person
JP3636986B2 (en) 2000-12-06 2005-04-06 松下電器産業株式会社 The semiconductor integrated circuit
EP1346280A1 (en) 2000-12-20 2003-09-24 Philips Electronics N.V. Data processing device with a configurable functional unit
US6426649B1 (en) 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US6483343B1 (en) 2000-12-29 2002-11-19 Quicklogic Corporation Configurable computational unit embedded in a programmable device
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US7020673B2 (en) 2001-01-19 2006-03-28 Sony Corporation Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US6847370B2 (en) 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6792588B2 (en) 2001-04-02 2004-09-14 Intel Corporation Faster scalable floorplan which enables easier data control flow
US20020143505A1 (en) 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US20030086300A1 (en) 2001-04-06 2003-05-08 Gareth Noyes FPGA coprocessing system
US6999984B2 (en) 2001-05-02 2006-02-14 Intel Corporation Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US6802026B1 (en) 2001-05-15 2004-10-05 Xilinx, Inc. Parameterizable and reconfigurable debugger core generators
JP3580785B2 (en) 2001-06-29 2004-10-27 株式会社半導体理工学研究センター Lookup tables, programmable logic device comprising a look-up table, and, configuring the look-up table
US7043416B1 (en) 2001-07-27 2006-05-09 Lsi Logic Corporation System and method for state restoration in a diagnostic module for a high-speed microprocessor
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US6874108B1 (en) 2001-08-27 2005-03-29 Agere Systems Inc. Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US20030056091A1 (en) 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US20030055861A1 (en) 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
US6854073B2 (en) 2001-09-25 2005-02-08 International Business Machines Corporation Debugger program time monitor
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US7000161B1 (en) 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US20060264508A1 (en) 2001-10-16 2006-11-23 Stone Richard A Modulation of ocular growth and myopia by gaba drugs
AU2002357739A1 (en) 2001-11-16 2003-06-10 Morpho Technologies Viterbi convolutional coding method and apparatus
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
DE20221985U1 (en) 2002-02-01 2010-03-04 Tridonicatco Gmbh & Co. Kg Electronic ballast for gas discharge lamp
US6961924B2 (en) 2002-05-21 2005-11-01 International Business Machines Corporation Displaying variable usage while debugging
US6803787B1 (en) 2002-09-25 2004-10-12 Lattice Semiconductor Corp. State machine in a programmable logic device
US6802206B2 (en) 2002-10-11 2004-10-12 American Axle & Manufacturing, Inc. Torsional actuation NVH test method
US7383421B2 (en) 2002-12-05 2008-06-03 Brightscale, Inc. Cellular engine for a data processing system
US7567997B2 (en) 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US8495122B2 (en) 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7038952B1 (en) 2004-05-04 2006-05-02 Xilinx, Inc. Block RAM with embedded FIFO buffer
US7971051B2 (en) 2007-09-27 2011-06-28 Fujitsu Limited FPGA configuration protection and control using hardware watchdog timer

Patent Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US489810A (en) * 1893-01-10 Pedal attachment for organs or pianos
US2067477A (en) * 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
US3242998A (en) * 1962-05-28 1966-03-29 Wolf Electric Tools Ltd Electrically driven equipment
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US5602999A (en) * 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US4151611A (en) * 1976-03-26 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Power supply control system for memory systems
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) * 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US5485104A (en) * 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4910665A (en) * 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US5510730A (en) * 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US4918440A (en) * 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5103311A (en) * 1988-01-11 1992-04-07 U.S. Philips Corporation Data processing module and video processing system incorporating same
US5303172A (en) * 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5010401A (en) * 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US5204935A (en) * 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5491353A (en) * 1989-03-17 1996-02-13 Xilinx, Inc. Configurable cellular array
US5287472A (en) * 1989-05-02 1994-02-15 Tandem Computers Incorporated Memory system using linear array wafer scale integration architecture
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
US5109503A (en) * 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
US5379444A (en) * 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
US5287532A (en) * 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5410723A (en) * 1989-11-21 1995-04-25 Deutsche Itt Industries Gmbh Wavefront array processor for blocking the issuance of first handshake signal (req) by the presence of second handshake signal (ack) which indicates the readyness of the receiving cell
US5099447A (en) * 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5617577A (en) * 1990-11-13 1997-04-01 International Business Machines Corporation Advanced parallel array processor I/O connection
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5301284A (en) * 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5301344A (en) * 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US5408643A (en) * 1991-02-01 1995-04-18 Nec Corporation Watchdog timer with a non-masked interrupt masked only when a watchdog timer has been cleared
US5506998A (en) * 1991-03-20 1996-04-09 Fujitsu Limited Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data
US5717890A (en) * 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5294119A (en) * 1991-09-27 1994-03-15 Taylor Made Golf Company, Inc. Vibration-damping device for a golf club
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5606698A (en) * 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5504439A (en) * 1994-04-01 1996-04-02 Xilinx, Inc. I/O interface cell for use with optional pad
US5502838A (en) * 1994-04-28 1996-03-26 Consilium Overseas Limited Temperature management for integrated circuits
US5619720A (en) * 1994-10-04 1997-04-08 Analog Devices, Inc. Digital signal processor having link ports for point-to-point communication
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5705938A (en) * 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5600597A (en) * 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
US5706482A (en) * 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5870620A (en) * 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
US20020010853A1 (en) * 1995-08-18 2002-01-24 Xilinx, Inc. Method of time multiplexing a programmable logic device
US5734869A (en) * 1995-09-06 1998-03-31 Chen; Duan-Ping High speed logic circuit simulator
US5745734A (en) * 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5608342A (en) * 1995-10-23 1997-03-04 Xilinx, Inc. Hierarchical programming of electrically configurable integrated circuits
US5898602A (en) * 1996-01-25 1999-04-27 Xilinx, Inc. Carry chain circuit with flexible carry function for implementing arithmetic and logical functions
US5727229A (en) * 1996-02-05 1998-03-10 Motorola, Inc. Method and apparatus for moving data in a parallel processor
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US6049866A (en) * 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US5895487A (en) * 1996-11-13 1999-04-20 International Business Machines Corporation Integrated processing and L2 DRAM cache
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US7650448B2 (en) * 1996-12-20 2010-01-19 Pact Xpp Technologies Ag I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7028107B2 (en) * 1996-12-27 2006-04-11 Pact Xpp Technologies Ag Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6507898B1 (en) * 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6188650B1 (en) * 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6212544B1 (en) * 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6173419B1 (en) * 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6681388B1 (en) * 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US6512804B1 (en) * 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6353479B1 (en) * 1999-06-29 2002-03-05 Hewlett-Packard Company Media-type encoding and print mode selection
US20020013861A1 (en) * 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US6725334B2 (en) * 2000-06-09 2004-04-20 Hewlett-Packard Development Company, L.P. Method and system for exclusive two-level caching in a chip-multiprocessor
US7346644B1 (en) * 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6538470B1 (en) * 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US20040078548A1 (en) * 2000-12-19 2004-04-22 Claydon Anthony Peter John Processor architecture
US20030070059A1 (en) * 2001-05-30 2003-04-10 Dally William J. System and method for performing efficient conditional vector operations for data parallel architectures
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7657877B2 (en) * 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7036114B2 (en) * 2001-08-17 2006-04-25 Sun Microsystems, Inc. Method and apparatus for cycle-based computation
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US20030056062A1 (en) * 2001-09-14 2003-03-20 Prabhu Manohar K. Preemptive write back controller
US20040039880A1 (en) * 2002-08-23 2004-02-26 Vladimir Pentkovski Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US20050091468A1 (en) * 2003-10-28 2005-04-28 Renesas Technology America, Inc. Processor for virtual machines and method therefor

Also Published As

Publication number Publication date
US20060031595A1 (en) 2006-02-09
AT243390T (en) 2003-07-15
EP1329816B1 (en) 2011-06-22
JP4637123B2 (en) 2011-02-23
JP2001510650A (en) 2001-07-31
EP1329816A3 (en) 2005-03-02
EP1329816A2 (en) 2003-07-23
US7822881B2 (en) 2010-10-26
JP2007215203A (en) 2007-08-23
JP3961028B2 (en) 2007-08-15

Similar Documents

Publication Publication Date Title
US3623017A (en) Dual clocking arrangement for a digital computer
US9075605B2 (en) Methods and devices for treating and processing data
US6092174A (en) Dynamically reconfigurable distributed integrated circuit processor and method
US7602214B2 (en) Reconfigurable sequencer structure
US6697957B1 (en) Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
JP4146519B2 (en) Method for establishing a self-synchronization of each possible configuration elements in programmable components
US3781810A (en) Scheme for saving and restoring register contents in a data processor
US6687788B2 (en) Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US5151986A (en) Microcomputer with on-board chip selects and programmable bus stretching
EP0241946B1 (en) Information processing system
US5434995A (en) Barrier synchronization for distributed memory massively parallel processing systems
US3629854A (en) Modular multiprocessor system with recirculating priority
US7200735B2 (en) High-performance hybrid processor with configurable execution units
US5583450A (en) Sequencer for a time multiplexed programmable logic device
EP1234277B1 (en) Programmable event counter system
US4745544A (en) Master/slave sequencing processor with forced I/O
US6066961A (en) Individually accessible macrocell
US7873811B1 (en) Polymorphous computing fabric
US4112490A (en) Data transfer control apparatus and method
US5825662A (en) Computer-implemented method of optimizing a time multiplexed programmable logic device
EP0724221A2 (en) Method and apparatus for executing dissimilar seq. of instructions in the processor of a single-instruction-multiple data (SIMD) computer
US5511207A (en) Program control circuit determining the designated number of times a sequence of instructions is repetitively executed to prevent further execution of a jump instruction
US6349346B1 (en) Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
AU2001245761B2 (en) Enhanced memory algorithmic processor architecture for multiprocessor computer systems
US6263430B1 (en) Method of time multiplexing a programmable logic device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RICHTER, THOMAS, MR.,GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACT XPP TECHNOLOGIES AG;REEL/FRAME:023882/0403

Effective date: 20090626

Owner name: KRASS, MAREN, MS.,SWITZERLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACT XPP TECHNOLOGIES AG;REEL/FRAME:023882/0403

Effective date: 20090626

Owner name: RICHTER, THOMAS, MR., GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACT XPP TECHNOLOGIES AG;REEL/FRAME:023882/0403

Effective date: 20090626

Owner name: KRASS, MAREN, MS., SWITZERLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACT XPP TECHNOLOGIES AG;REEL/FRAME:023882/0403

Effective date: 20090626

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION