US20040078548A1 - Processor architecture - Google Patents

Processor architecture Download PDF

Info

Publication number
US20040078548A1
US20040078548A1 US10/450,618 US45061803A US2004078548A1 US 20040078548 A1 US20040078548 A1 US 20040078548A1 US 45061803 A US45061803 A US 45061803A US 2004078548 A1 US2004078548 A1 US 2004078548A1
Authority
US
United States
Prior art keywords
bus
array
data
respective
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/450,618
Inventor
Anthony Claydon
Anne Claydon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
PicoChip Designs Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB0030993A priority Critical patent/GB2370380B/en
Priority to GB00390993.0 priority
Application filed by PicoChip Designs Ltd filed Critical PicoChip Designs Ltd
Priority to PCT/GB2001/004665 priority patent/WO2002050624A2/en
Assigned to PICOCHIP DESIGNS LIMITED reassignment PICOCHIP DESIGNS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CLAYDON, ANNE PATRICIA, CLAYDON, ANTHONY PETER JOHN
Publication of US20040078548A1 publication Critical patent/US20040078548A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MINDSPEED TECHNOLOGIES, INC., MINDSPEED TECHNOLOGIES U.K., LIMITED, PICOCHIP (BEIJING) TECHNOLOGY COMPANY LIMITED, MINDSPEED TELECOMMUNICATIONS TECHNOLOGIES DEVELOPMENT (SHENSHEN) CO. LTD.
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023Two dimensional arrays, e.g. mesh, torus

Abstract

There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs,each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array.

Description

  • This invention relates to a processor architecture, and in particular to an architecture which can be used in a wide range of devices, such as communications devices operating under different standards. [0001]
  • In the field of digital communications, there has been a trend to move as many functions as possible from the analogue domain into the digital domain. This has been driven by the benefits of increased reliability, ease of manufacture and better performance achievable from digital circuits, as well as the ever decreasing cost of CMOS integrated circuits. Today, the Analogue-Digital and Digital-Analogue Converters (ADC's and DAC's) have been pushed almost as near to the antenna as possible, with digital processing now accounting for parts of the Intermediate Frequency (IF) processing as well as baseband processing. [0002]
  • At the same time, there has been a vast improvement in the capability of microprocessors, and much of the processing for many narrowband communications systems is now performed in software, an example being the prevalence of software modems in PC's and consumer electronics equipment, partly because a general purpose processor with sufficient processing power is already present in the system. In the field of wireless communications there is extensive research in the field of software radio, the physical layers of broadband communications systems require vast amounts of processing power, and the ability to implement a true software radio for third generation (3G) mobile communications, for example, is beyond the capability of today's DSP processors, even when they are dedicated to the task. [0003]
  • Despite this, there has never been a time when there has been more need for software radio. When second generation (2G) mobile phones were introduced, their operation was limited to a particular country or region. Also, the major market was business users and a premium could be commanded for handsets. Today, despite diverse 2G standards in the USA and different frequency bands, regional and international roaming is available and handset manufacturers are selling dual and triple band phones which are manufactured in their tens of millions. After years of attempts to make an international standard for 3G mobile, the situation has now arisen where there are three different air interfaces, with the one due to replace GSM (UMTS) having both Frequency and Time Division Duplex (FDD and TDD) options. Additionally, particularly in the USA, 3G systems must be capable of supporting a number of legacy 2G systems. [0004]
  • Although a number of DSP processors are currently being developed that may be able to address the computational requirements of a 3G air interface, none of these show promise of being able to meet the requirements of a handset without the use of a number of hardware peripherals. The reasons for this are power and cost and size. All three are interrelated and controlled by the following factors: [0005]
  • 1. The need for memory. Classical processor architectures require memory to store both the program and data which is being processed. Even in parallel Very Long Instruction Word (VLIW) or Single Instruction Multiple Data (SIMD) architectures, the entire processor is devoted to one task at a time (eg: a filter, FFT or Viterbi decoding), with memory required to hold intermediate results between the tasks. In addition, fast local instruction and data caches are required. Altogether, this increases the size and cost of the solution, as well as dissipating power. In hardwired architectures, data is usually transferred directly from one functional block to another, with each block performing DSP functions on the data as it passes through, thus minimising the amount of memory required. [0006]
  • 2. Data bandwidth. In hard-wired solutions, all data is held locally, if necessary in small local RAM's within functional blocks. Some transceivers may contains several dozen small RAM's, and although the data bandwidth required by each RAM may be relatively small, the overall data bandwidth can be vast. When the same functions are implemented in software running on a processor, the same global memories are used for all data and the required data bandwidth is enormous. Solutions to this problem usually involve the introduction of local memories in a multi-processor array, but the duplication of data on different processors and the task of transferring data between processors via Direct Memory Access (DMA) mean that the power dissipation is, if anything, increased, as is silicon area and consequently cost. [0007]
  • 3. The need for raw processing power. In today's DSP processors, improvements in processing throughput are achieved by a combination of smaller manufacturing process geometries, pipelining and the addition of more execution units (e.g. arithmetic logic units and multiplier-accumulators). Improvements in manufacturing processes are open to all solutions, and so are not a particular advantage for conventional DSP processors. The other two methods both come with considerable overheads in increased area and power, not merely because of the extra hardware which provides the performance improvement, but because of the consequential increases in control complexity. [0008]
  • The processor architecture of the present invention falls under the broad category of what are sometimes referred to as dataflow architectures, but with some key differences which address the needs of software. In fact, the invention provides a solution which is more akin to a hard-wired architecture than a DSP processor, with consequential size and power advantages. It consists of an array of processor and memory elements connected by switch matrices. [0009]
  • According to the present invention, there is provided a processor architecture, comprising: [0010]
  • a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction is opposite to the first direction (for example right to left); [0011]
  • a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; [0012]
  • a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; [0013]
  • a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. [0014]
  • Preferably, the elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. [0015]
  • Preferably, the processing elements include Arithmetic Logic Units and/or Multiplier Accumulators. [0016]
  • Preferably, the elements in the array further include interface elements for receiving input data from outside the processor, and transferring output data outside the processor. [0017]
  • Preferably, each element of the array is connected between a first bus of one first bus pair and a second bus of an adjacent first bus pair, and has: a first input for receiving data from the first bus of the one first bus pair; a first output for transferring data to the first bus of the one first bus pair; a second input for receiving data from a second bus of the adjacent first bus pair; and a second output for transferring data to the second bus of the adjacent first bus pair. [0018]
  • Preferably, each switch matrix allows data on a bus of a first bus pair to be switched onto the other bus of said first bus pair and/or onto either bus or both buses of the respective intersecting second bus pair, and allows data on a bus of a second bus pair to be switched onto either bus or both buses of the respective intersecting first bus pair, but not onto the other bus of said second bus pair. [0019]
  • Preferably, there are a plurality of array elements (most preferably, four) connected to each bus of a first bus pair between each pair of adjacent switch matrices. [0020]
  • The architecture according to the preferred embodiment of the invention has the advantage that no global memory is required, which provides a major benefit in terms of power consumption. [0021]
  • The architecture allows flexible data routing between array elements using a switch matrix. This means that the device is able to run the many diverse algorithms required by a software radio concurrently, without having to reconfigure the array. [0022]
  • Further, data is passed from one array element to another directly, without having to be written to memory. This means that memory requirements are close to being as low as those of a hardwired architecture. [0023]
  • Moreover, because there are a large number of simple array elements, each performing a limited number of operations, there is a low control overhead, reducing size and power dissipation.[0024]
  • Reference will now be made, by way of example, to the accompanying drawings, in which: [0025]
  • FIG. 1 is a schematic representation of a section of a processor, illustrating the architecture in accordance with the invention; [0026]
  • FIG. 2 is an enlarged representation of a part of the architecture of FIG. 1; [0027]
  • FIG. 3 is an enlarged representation of another part of the architecture of FIG. 1; [0028]
  • FIG. 4 is an enlarged representation of another part of the architecture of FIG. 1; [0029]
  • FIG. 5 shows the distribution of elements in a typical array in accordance with the invention; [0030]
  • FIG. 6 shows a first array element in the architecture of FIG. 1; [0031]
  • FIG. 7 shows a second array element in the architecture of FIG. 1; [0032]
  • FIG. 8 shows a first connection of the array element of FIG. 7 in the array according to the invention; [0033]
  • FIG. 9 shows a second connection of the array element of FIG. 7 in the array according to the invention; [0034]
  • FIG. 10 shows a third array element in the architecture of FIG. 1; [0035]
  • FIG. 11 shows a fourth array element in the architecture of FIG. 1; [0036]
  • FIG. 12 shows the format of data transferred between array elements; and [0037]
  • FIG. 13 is a timing diagram illustrating the flow of data between array elements. [0038]
  • FIG. 1 shows a part of the structure of a processor architecture [0039] 10. The device is made up of an array of elements 20, which are connected by buses and switches.
  • The architecture includes first bus pairs [0040] 30, shown running horizontally in FIG. 1, each pair including a respective first bus 32 carrying data from left to right in FIG. 1 and a respective second bus 36 carrying data from right to left.
  • The architecture also includes second bus pairs [0041] 40, shown running vertically in FIG. 1, each pair including a respective third bus 42 shown carrying data upwards in FIG. 1 and a respective fourth bus 46 shown carrying data downwards in FIG. 1.
  • In FIG. 1, each diamond connection [0042] 50 represents a switch, which connects an array element 20 to a respective bus 32, 36. The array further includes a switch matrix 55 at each intersection of a first and second bus pair 30, 40.
  • The data buses are described herein as 64-bit buses, but for some application areas it is likely that 32-bit buses will suffice. Each array element can be designed to be any one of the following: [0043]
  • an execution array element, which contains an Arithmetic Logic Unit (ALU) or Multiplier Accumulator (MAC); [0044]
  • a memory array element, containing a RAM; [0045]
  • an interface array element, which connects the processor to an external device; or [0046]
  • a switch control array element, which controls the operation of at least one switch matrix [0047] 55.
  • Each of these will be described in more detail below. [0048]
  • FIG. 2 is an enlarged view of a part of the architecture of FIG. 1, showing six array elements, [0049] 20A-20F. Each array element is connected onto two 64-bit buses, 32, 36, which carry data in opposite directions. After every four array elements (as shown in FIG. 1), the horizontal buses are connected to two vertical buses, 42, 46, one running up and the other down. The choice of bit-width and vertical bus pitch is not fundamental to the architecture, but these dimensions are presently preferred.
  • Each switch element [0050] 50 is a 2:1 multiplexer, controllable such that either of its two inputs can be made to appear on its output. Thus, output data from an array element can be transferred onto a bus, and/or data already on the bus can be allowed to pass.
  • The switch matrix [0051] 55 includes four 4:1 multiplexers 501, 502, 503 and 504 which are each controllable such that any one of their inputs can appear at their output.
  • The inputs of multiplexer [0052] 501 are connected to input connections 32 a, 36 a and 42 a on buses 32, 36, 42 respectively, and to ground. The output of multiplexer 501 is connected to bus 42.
  • The inputs of multiplexer [0053] 502 are connected to input connections 32 a, 36 a and 46 a on buses 32, 36, 46 respectively, and to ground. The output of multiplexer 502 is connected to bus 46.
  • The inputs of multiplexer [0054] 503 are connected to input connections 32 a, 36 a, 42 a and 46 a on buses 32, 36, 42 and 46 respectively. The output of multiplexer 503 is connected to bus 36.
  • The inputs of multiplexer [0055] 504 are connected to input connections 32 a, 36 a, 42 a and 46 a on buses 32, 36, 42 and 46 respectively. The output of multiplexer 504 is connected to bus 32.
  • Thus, in the switch matrix [0056] 55, the input of any bus can be used as the source for data on the output of any bus, except that it is not possible to select the down bus (i.e. the one entering from the top of the diagram in FIG. 2, namely the fourth bus 46) as the source for the up bus (that is, the third bus 42), and, similarly, it is not possible to select the up bus (the third bus 42) as the source of the down bus (the fourth bus 46).
  • These exceptions represent scenarios which are not useful in practice. Conversely, however, it is useful to have the left bus as a potential source for the right bus, and vice versa, for example when routing data from array element [0057] 20B to array element 20E.
  • As mentioned above, one of the inputs of each of the multiplexers [0058] 501, 502 is connected to ground. That is, each of the 64 bus lines is connected to the value 0. This is used as part of a power reduction method, which will be described further below.
  • Each of the multiplexers [0059] 501, 502, 503, 504 can be controlled by signals on two control lines. That is, a two-bit control signal can determine which of the four inputs to a multiplexer appears on its output.
  • FIG. 3 is a view of the top-left hand corner of the array of FIG. 1, showing the structure of a switch matrix [0060] 56 which is used when there is no input connection to a left-right bus 32, and of a switch matrix 57 which is used when there is no input connection to a left-right bus 32 or to a bus 46 running down.
  • The switch matrix [0061] 56 includes three 4:1 multiplexers 505, 506, 507, while the switch matrix 57 includes three 4:1 multiplexers 508, 509, 510. Compared to a switch matrix in the middle of the array, the number of input buses to multiplexers 505, 508 and 509 is reduced by one, because there is no input bus entering from the left. Similarly, there is no input bus entering from the left as an input to multiplexer 510, but in this case the input bus which has been released has been connected to 0. This is also the case for multiplexer 507, but in this case there is no input bus entering from the top of the switch matrix either, so this multiplexer has only three input buses.
  • Being in the corner of the array, no input buses from the top or the left are available for multiplexer [0062] 506, which only has two inputs. Equivalent arrangements will be apparent for the bottom-left, top-right and bottom-right corners of the array.
  • FIG. 4 is a view of part of the top edge of the array of FIG. 1, showing the structure of a switch matrix [0063] 58 which is used when there is no input connection to a bus 46 running down.
  • The switch matrix [0064] 58 includes two 4:1 multiplexers 511, 512. The number of available input buses to multiplexers 511 and 512 is reduced by two, but, in the case of multiplexer 511, one of the input buses has been replaced by the value zero. An equivalent structure for multiplexers on the bottom edge of the array is apparent.
  • Data transfer can be regarded as having three stages. Firstly, an array element puts the data on the appropriate output. [0065]
  • Secondly, multiplexers in the appropriate switch matrix, or switch matrices, are switched to make the necessary connections. [0066]
  • Thirdly, the destination array element loads the data. [0067]
  • Each of these aspects is controlled by a separate array element: the first and third by the source and destination array elements respectively, and the second by special switch control array elements. These are embedded into the array at regular intervals and are connected by control lines to all the multiplexers in the switch matrices which they control. Each array element controls the multiplexers immediately adjacent to its outputs, with the control being performed separately on individual 16-bit fields. This allows several array elements to source data onto a bus at the same time, provided they are using different fields of the bus. This is particularly useful for functions such as Add-Compare-Select (ACS) in the Viterbi Algorithm. Switching at intersection nodes of the horizontal and vertical buses is performed on the entire 64-bit bus and its associated control signals. [0068]
  • Clearly, the three operations of source, switching and loading, although controlled independently, need to be synchronised. This is achieved by restricting all data transfer operations to a series of predetermined cycles, which are fixed at the time when the program is compiled and mapped onto the array. In a general purpose processor, this restriction would be onerous, but it is actually helpful for many applications of the present invention. [0069]
  • As mentioned previously, there are a number of types of array element, but they all must conform to three basic rules. [0070]
  • Firstly, they must have input and output ports which connect to the left and right buses of the array. [0071]
  • Secondly, they must run a program which is synchronised to the transfer cycles on the buses to which they are connected. In practice, this usually means that each array element must run a program loop which accesses the buses in a regular pattern which has a duration in clock cycles which is a power of two (e.g. 4, 8, 16 or 32 clock cycles). [0072]
  • Thirdly, they must interpret information which appears on the buses during special control cycles, known as the Array Control Protocol. [0073]
  • A consequence of these rules is that, in the normal course of events, the entire program which an array element executes will be contained in local memory within the array element. In fact, more often than not, the program will contain just one loop. It is possible to reload an array element with new instructions, but this involves stopping executing and reloading the instruction store of the array element using the control cycles outlined above. An array element has no means of fetching external instructions autonomously. [0074]
  • All array elements are data driven. That is to say, array elements only execute instructions of their programs when data arrives. [0075]
  • There are two types of execution array elements: Multiplier Accumulator (MAC) array elements and Arithmetic Logic Unit (ALU) array elements. These must be included in the array along with other array elements in approximately the correct proportions for the target applications. Fortunately, many array applications require approximately the same proportions, and FIG. 5 shows an example of an array containing 256 array elements in proportions optimised for a communications transceiver. FIG. 5 does not show the horizontal buses in the array and the positions of pairs of vertical buses [0076] 40 are shown as single lines.
  • As well as MAC, ALU, Memory and Switch Control array elements, the example array of FIG. 5 contains three interface array elements, [0077] 80, 81 and 82. Array elements 80 and 81 are used for data input and output to the analogue portions of the transceiver and array element 82 is the interface to a microprocessor. Each of the four Switch Control array elements 83 a to 83 d controls the switch matrices of one quarter of the array. For example, Switch Control array element 83 a controls the switch matrices along the horizontal buses connected to the top four rows of array elements, 84.
  • FIG. 6 shows the preferred embodiment of a Switch Control array element. This consists of controller [0078] 94 and RAM 95, together with means of loading the RAM using the Array Control Protocol described below and sequencing data out of the RAM. Data is loaded into the RAM from either the left bus 32 or right bus 36 to which the Switch Control array element is connected by means of multiplexers 92 and 64-bit register 93.
  • When the Switch Control array element is set into its normal operating mode by means of Enable signal [0079] 98, the address of RAM 95 is first set to zero and the first 160-bit word is read out and loaded into register 96. On each subsequent clock cycle, the RAM address is incremented and a new 160-bit word is loaded into register 96, until the address reaches 127, at which point it is reset to zero again and the process is repeated. The outputs of register 96 are routed directly to the select inputs of the multiplexers in the switch matrices 55 (FIGS. 1 and 2), so in this way all the switch matrices are controlled in a cyclical pattern lasting for 128 clock cycles. As previously noted, most areas of the array transfer data in cyclical patterns of a duration less than 128 clock cycles, but these are accommodated by repeating them within the 128 cycle pattern.
  • ALU and MAC array elements have the same interfaces to the array, differing only in the type of execution unit and associated instructions. FIG. 7 shows an ALU array element, which will be used to describe these interfaces to the array. [0080]
  • Referring to FIG. 7, three 64-bit registers, each formed from four 16-bit sub-registers [0081] 121 a-121 d, 121 e-121 h and 121 i-121 l, can be connected to either of left bus 32 or right bus 36 through multiplexers 120, thus allowing them to be loaded from either bus. In response to instructions taken from instruction store 122 and decoded in instruction decode unit 123, any one 64-bit register can be connected to the left or right bus during one clock cycle and any combination of sub-registers loaded. For example, an instruction may cause 16-bit sub-registers 121 a and 121 b of 64-bit register 121 a-121 d to be loaded with the data in bits 31:0 of left bus 32. Further instructions may cause data in the registers to be manipulated in ALU 125 and stored back into the same or different registers 121, and still further instructions may enable the contents of these registers onto the left and right buses via multiplexer 126 and switch boxes 51. In the preferred embodiment, during the same clock cycle one 64-bit register may be used to load data from an array bus, data from another may be enabled back onto an array bus and ALU operations may be performed on the contents of registers, these tasks being accomplished by using separate fields in the instruction words.
  • FIG. 8 shows the contents of a switch box [0082] 51 in FIG. 7. BUSIN 132 and BUSOUT 133 are each segments of a left bus 36 or a right bus 32. Control signals EN[3:0] 130 and SEL[3:0] 131 are both sourced by instruction decode block 123 in FIG. 7. Using these signals, any 16-bit field of BUSOUT may be set to be equal to BUSIN, the output bus of the array element or zero.
  • FIG. 9 illustrates how, likewise, the BDVAL signal (described below) associated with the data on the bus can be allowed to pass along the bus or be set by the array element. [0083]
  • FIG. 10 shows the preferred embodiment of a Memory array element. This has many of the same features of the ALU array element described above, but in addition has RAMs [0084] 143 connected to registers 140, 141 and 142 via multiplexers. 16-bit sub-registers R0 to R3 of 64-bit register 140 are used for data input to the RAMs, 16-bit sub-registers R4 to R7 of 64-bit register 141 are used for the address input to the RAMs and 16-bit sub-registers R8 to R11 of 64-bit register 142 are used for the data output from the RAMs. Both address and data may be manipulated using the ALU under the control of the instruction decode unit as in the case of the ALU array element and the processes of loading data from the left and right buses 32 and 36 is also performed in exactly the same manner. The instructions stored in instruction store 144 and decoded in instruction decode unit 145 have an additional field compared to the equivalent units of the ALU array element. This additional field is used to control the reading of data from the RAMs and writing of data to them, these operations being performed in the same cycles as array accesses and ALU operations.
  • Referring to FIG. 10, it can be seen that the addresses for the RAMs may be calculated within the Memory array element using its internal ALU and loaded into the sub-registers of 64-bit register [0085] 141. Alternatively, addresses may be provided over the array buses from another array element and loaded directly into register 141.
  • In the example array of FIG. 5, Memory array elements hold all the data which is processed by the execution array elements and there is no external global memory. However, it will be clear that if a given application requires a large amount of storage, access to external memory can be provided using appropriate Interface array elements. Furthermore, instructions which form the programs which the array elements run are not generally stored in Memory array elements, but reside entirely in the instruction stores of the array elements. Instructions are loaded into the instruction stores of the array elements using the Array Control Protocol, which is described below. [0086]
  • FIG. 11 shows how an Analogue to Digital Converter (ADC) [0087] 153 can be connected to the processor architecture as an Interface array element.
  • Because an ADC solely sources data, the only need to supply data to this array element is for the purposes of configuration and control, such as putting the ADC into test or low power standby modes, and to control the times at which the array element transfers sampled data onto the output bus. The array element controller [0088] 152 can therefore be simpler than the instruction store and decode unit in Execution and Memory array elements, but nevertheless is capable of being programmed to cause ADC 153 to sample input analogue signal 156, load the sampled data into register 155 and enable this data onto bus 32 or 36 at configurable points in a sequence.
  • Other common sorts of Interface array element are the Digital to Analogue Converters (DAC) array element, which performs the opposite role of the ADC array element, and the host interface array element. The latter transfers data from the array to the bus of a general purpose host processor and from the host processor to the array. [0089]
  • The basic elements of the array architecture according to the present invention have now been described. However, much of the power of the architecture comes from the details of operation, and in particular how it has been optimised to support common computation-intensive DSP algorithms found in physical layer protocols. More details of these aspects will now be provided, together with the methods used to minimise power dissipation, which allow the architecture to be used in power-sensitive devices, such as handheld terminals. [0090]
  • A number of control signals are multiplexed with the 64-bit data buses in the array, namely: [0091]
  • ARRCTL—ARRay ConTroL—This signifies that the data on the bus is array control information. All array elements must interpret this and act accordingly. [0092]
  • BDVAL—Bus Data VALid—This signifies that there is valid data on the bus. This is a key signal in the control of power dissipation. [0093]
  • A major objective of the architecture is to keep the size of array elements down by eliminating the need for complex control overheads. The Array Control Protocol (ACP) is used for the following:—[0094]
  • Loading the program code into all array elements when the array is booted. [0095]
  • Starting, stopping and synchronising array elements. [0096]
  • Selectively reloading new program code into array elements during operation. [0097]
  • Each array element has a Unique Identifier (UID), which is used to address it, and the ACP uses Array Control Words (ACW's) to communicate information between array elements. When the ARRCTL line of a section of a bus is high, it indicates that the data on the bus is an ACW. FIG. 12 shows the structure of the 64-bit ACW. [0098]
  • When an ACW is put on the section of the bus to which an array element is connected, the array element must examine the word, even if it was formerly in low-power sleep mode. If the address field of the ACW matches the UID of the array element, or is equal to a designated broadcast address, the array element must interpret the FUNCTION field of the ACW and perform the required action. In one presently preferred embodiment of the invention, the following FUNCTION fields are defined: [0099]
    Value Function Description
    0 Reset Causes the array element to halt
    operation and resets its internal
    state
    1 Load The DATA field contains a program
    Program 0 word which must be placed in the
    first location in the program store
    of the array element
    11 Load The DATA field contains a program
    Program word which must be placed in the next
    location in the program store of the
    array element
    100 Start The array element must start
    executing program in program store
    101 Stop The array element must stop executing
    program in program store
    110 Test Enter test mode
    111 Dump Place data from next location in the
    program store on the bus
  • ACWs may be generated by any array element, but the array will normally include one element which is defined as the master controller, and the master controller will generate all ACWs. The major function of the Array Control Protocol is to load the program stores of the array elements when the device is booted. Therefore, a host interface array element, which loads the program supplied by a host processor, is most likely to be the source of ACWs. [0100]
  • Unlike most processors, which are instruction driven, the processor of the present invention, and its component array elements, are data driven. That is, instead of processing data as the result of fetching an instruction, array elements execute instructions as a result of receiving data. [0101]
  • Once a program has been loaded into an array element and it has been started using the START Array Control Word it will begin to execute its instruction sequence. When it reaches an instruction which requires it to load data, then, if no data is present on the bus (signified by the control signal BDVAL being low) it must stop and wait until data is available. During the time it is stopped it puts itself into a low power sleep mode. Whilst in sleep mode, the array element will examine the bus at time intervals specified by a field in the load instruction which was stalled to check if the data has arrived. [0102]
  • For example, consider a demodulator. In a demodulator using the architecture described herein, the demodulator will contain an ADC which samples at a fixed rate which generally will be somewhat above the actual required rate. The front end of the demodulator will contain an interpolator, which resamples the incoming data. This removes the need for an analogue VCO to synchronise the ADC sample clock to the data, but the resampled data will be irregular with respect to the processor system clock and data transfer sequences, creating “gaps” where data would have been expected. (In fact the ADC sample clock need not be synchronised to the processor system clock at all, with synchronisation to the system clock being performed in the ADC interface array element). Using the data driven processor architecture of the present invention, where there is a “gap” in the incoming data, the array elements which are affected merely “go to sleep” until data is available. [0103]
  • It should be noted that, because all data transfers are synchronised to sequences which are defined at the time the program is compiled and mapped to the processor, array elements will sleep for at least one of the sequences to which they are synchronised. [0104]
  • This is illustrated in FIG. 13. In this timing diagram, all transfers to two array elements (A and B) are synchronised to a four cycle sequence. Successive transfer sequences are labelled [0105] 0 to 5 (TRANSFER SEQ). In the sequence, array element A loads data on the fourth clock cycle and array element B on the second (as shown in the DATA bus), the points at which they load being shown for convenience as the signals LOADREQA and LOADREQB. Signals BDVALA and BDVALB are the BDVAL signals associated with the data loaded by array elements A and B. It can be seen that, where no data is available when it is expected, that is the BDVAL signal is low, as is the case in sequence 1 in which there is no data for array element A and in sequence 4 in which there is no data for array element B. the respective array element goes into sleep mode until the data is available. Also, the fact that no data is available for one of the array elements does not affect transfer operations to the other.
  • Clearly, if an array element does not receive any data, there will be a corresponding gap when it does not source data, so gaps will ripple through the array. However, the approximate gap rate at any particular point in the algorithm will be known at the time the program is written, so careful use of FIFO's (which tend to occur naturally at points in an algorithm where data needs to be stored, for example where a block of data has to be accumulated before it is processed) means that the entire array is not locked to gaps which occur at the front end of the processing chain. [0106]
  • In some cases, when a particular array element does not receive data, a small group of array elements must be stalled. For example, if an array element multiplies data with coefficients which are loaded from a memory array element, then, if the data does not arrive, the memory array element must be prevented from sending data. This is achieved by routing the data past the memory array element and allowing the memory array element to sample the BDVAL signal. If BDVAL is low, then the memory array element will also go into sleep mode. [0107]
  • In more detail, the method by which the BDVAL signal is controlled and array elements respond to it is as follows. [0108]
  • Consider the ALU array element of FIG. 7. Every time this array element executes a STORE instruction, which causes it to enable data onto an array bus, it sets the LOCAL_VALID, VALID_ENABLE and SELECT signals ([0109] 128 a in FIG. 9) for one of switch boxes 52 such that BDVAL_OUT (129 in FIG. 9) is set to 1 for one clock cycle. During the same clock cycle, EN[3:0] 130 and SEL[3:0] 131 in FIG. 8 are set so as to set BUSOUT[63:0] to the required value. For example, if data is to be transferred on all 64 bits of the bus, then all of EN[3] to EN[0] and SEL[3] to SEL[0] are set to 1. If, however, data is only to be transferred on bits [15:0] of the bus, then EN[0] and SEL[0] are set to 1, but EN[3:1] are set to 0. SEL[3:1] are set to 1 if no other array element is transferring data on the other bits of the bus segment during the same clock cycle. Otherwise, they are set to 0. As an example of multiple array elements using the same bus segment to transfer data in the same clock cycle, referring to FIG. 2, using the above method, it can be seen that array element 20B could transfer data onto bits [31:0] of bus 36, whilst array element 20C transfers data on bits [63:32], with all 64 bits being routed to array element 20F, say.
  • During the clock cycle referred to above, the Switch Control array elements cause multiplexers in switch matrices [0110] 55 (FIGS. 1 and 2) to switch so that the bus data and the associated BDVAL signal are routed to the destination array element. Referring again to FIG. 7, during the same clock cycle, the destination array element (or array elements) executes a LOAD instruction which causes multiplexers 120 to select the bus on the inputs of the required register 121, which is loaded at the end of the clock cycle if the BDVAL signal is 1. If the BDVAL signal is 0, no load takes place and the array element waits for a number of clock cycles specified as part of the LOAD instruction field. During the time that the destination array element is waiting, the only active circuitry in the array element is the execution control block 124, which loads the wait period into a counter and counts down. When the count reaches zero, the execution control unit re-examines the BDVAL signal and, if it is now 1, causes execution to proceed from the point it left off. Because the circuitry in the execution control unit is very small compared to the rest of the array element, very little power is consumed while an array element is waiting.
  • As well as the LOAD instruction described above, all array elements which can be destinations for data transfers also have a WAIT instruction. This instruction causes the execution control unit to examine the BDVAL signal for either left bus [0111] 32 or right bus 36 and wait for the specified number of clock cycles if selected BDVAL signal is 0. However, no data is loaded.
  • Throughout the above descriptions, reference has been made to methods of reducing power dissipation in the array. These methods are now described in more detail. [0112]
  • In order to minimise power dissipation during data transfers on the array, it is important that bus lines and other signals are not charged and discharged unless necessary. In order to achieve this, the default state of all bus lines has been chosen to be 0, and the Switch Control array elements are programmed to select the value of 0 onto all bus segments that are not being used via the “0” inputs of multiplexers [0113] 501 and 502 in FIG. 2 and additional multiplexer inputs at the edges and corners of the array as shown in FIGS. 3 and 4.
  • When data is transferred on the bus, often not all 64 bits are used. Therefore a method is provided, as described above, whereby the array element which is loading data onto the bus sets any unused bits to 0. If the bus had previously been inactive, these bits would have been 0 before the start of the transfer, so their values will not change. [0114]
  • Referring to FIG. 2, it will be seen that, if data is being transferred from array element [0115] 20B to array element 20E, say, then, unless any further measures were provided, the data would propagate along right bus 32 which is connected to array element 20E, past array element 20E and on to array element 20F and beyond, thus unnecessarily charging or discharging further segments of bus 32. To prevent this from occurring, all array elements which can be destinations for data can cause the signals for their output switch boxes 51 to be set so that data further along the bus is set to 0 (and hence remains at zero). This is achieved by setting signals EN[3:0] (130 in FIG. 8) to 0 and signals SEL[3:0) (131 in FIG. 8) to 1. A field is provided in the LOAD instruction which is executed on an array element which selects whether data is allowed to propagate further along the bus or is stopped as just described, thus allowing multiple array elements to load the same-data (or different fields of the bus which are transferred during the same clock cycle).
  • There is therefore described a processor architecture which can be reprogrammed to provide a required functionality, while being efficient in terms of its power consumption and occupied silicon area. [0116]

Claims (18)

1. A processor architecture, comprising:
a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction and a respective second bus running in a second direction opposite to the first direction;
a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction and a respective fourth bus running in a fourth direction opposite to the third direction, the third and fourth buses intersecting the first and second buses;
a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses;
a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.
2. A processor architecture as claimed in claim 1, wherein the elements in the array include processing elements, for operating on received data.
3. A processor architecture as claimed in claim 1, wherein the elements in the array include memory elements, for storing received data.
4. A processor architecture as claimed in claim 1, wherein the elements in the array include processing elements, for operating on received data, and memory elements, for storing received data.
5. A processor architecture as claimed in claim 2 or 4, wherein the processing elements include Arithmetic Logic Units.
6. A processor architecture as claimed in claim 2, 4 or 5, wherein the processing elements include Multiplier Accumulators.
7. A processor architecture as claimed in any preceding claim, wherein the elements in the array further include interface elements for receiving input data from outside the processor, and transferring output data outside the processor.
8. A processor architecture as claimed in any preceding claim, wherein each element of the array is connected between a first bus of one first bus pair and a second bus of an adjacent first bus pair.
9. A processor architecture as claimed in any preceding claim, each element of the array having:
a first input for receiving data from the first bus of the one first bus pair;
a first output for transferring data to the first bus of the one first bus pair;
a second input for receiving data from a second bus of the adjacent first bus pair;
a second output for transferring data to the second bus of the adjacent first bus pair.
10. A processor architecture as claimed in any preceding claim, further comprising:
a first switch connected to the first output of each element of the array, the first switch allowing either data on the first bus or data at the first output of the element of the array to pass along the first bus; and
a second switch connected to the second output of each element of the array, the second switch allowing either data on the second bus or data at the second output of the element of the array to pass along the second bus.
11. A processor architecture as claimed in claim 10, wherein each first switch, connected to the first output of a respective element of the array, and each second switch, connected to the second output of the respective element of the array, are controlled by the respective element of the array.
12. A processor architecture as claimed in any preceding claim, wherein each switch matrix allows data on a bus of a first bus pair to be switched onto the other bus of said first bus pair and/or onto either bus or both buses of the respective intersecting second bus pair, and allows data on a bus of a second bus pair to be switched onto either bus or both buses of the respective intersecting first bus pair, but not onto the other bus of said second bus pair.
13. A processor architecture as claimed in claim 12, further comprising means for controlling each switch matrix.
14. A processor architecture as claimed in claim 11, wherein the means for controlling each switch matrix comprises an array element.
15. A processor architecture as claimed in any preceding claim, having a plurality of array elements connected to each bus of a first bus pair between each pair of adjacent switch matrices.
16. A processor architecture as claimed in claim 15, having four array elements connected to each bus of a first bus pair between each pair of adjacent switch matrices.
17. A processor architecture as claimed in any preceding claim, wherein each switch matrix comprises:
input and output connections for the respective first, second, third and fourth buses; and
four multiplexers, which are each controllable such that any one of their inputs can appear at their output, wherein
a first multiplexer (501) has inputs connected to input connections on first, second and third buses and an output connected to the third bus,
a second multiplexer (502) has inputs connected to input connections on first, second and fourth buses and an output connected to the fourth bus,
a third multiplexer (503) has inputs connected to input connections on first, second, third and fourth buses and an output connected to the first bus, and
a fourth multiplexer (504) has inputs connected to input connections on first, second, third and fourth buses and an output connected to the second bus.
18. A processor architecture as claimed in claim 17, wherein the first, second, third and fourth multiplexers are 4:1 multiplexers, and the first and second multiplexers each have respective inputs which are held at zero.
US10/450,618 2000-12-19 2001-10-19 Processor architecture Abandoned US20040078548A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0030993A GB2370380B (en) 2000-12-19 2000-12-19 Processor architecture
GB00390993.0 2000-12-19
PCT/GB2001/004665 WO2002050624A2 (en) 2000-12-19 2001-10-19 Processor architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/070,790 US7996652B2 (en) 2000-12-19 2008-02-21 Processor architecture with switch matrices for transferring data along buses
US13/176,381 US8904148B2 (en) 2000-12-19 2011-07-05 Processor architecture with switch matrices for transferring data along buses

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/070,790 Continuation US7996652B2 (en) 2000-12-19 2008-02-21 Processor architecture with switch matrices for transferring data along buses

Publications (1)

Publication Number Publication Date
US20040078548A1 true US20040078548A1 (en) 2004-04-22

Family

ID=9905410

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/450,618 Abandoned US20040078548A1 (en) 2000-12-19 2001-10-19 Processor architecture
US12/070,790 Active 2029-04-07 US7996652B2 (en) 2000-12-19 2008-02-21 Processor architecture with switch matrices for transferring data along buses
US13/176,381 Expired - Fee Related US8904148B2 (en) 2000-12-19 2011-07-05 Processor architecture with switch matrices for transferring data along buses

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12/070,790 Active 2029-04-07 US7996652B2 (en) 2000-12-19 2008-02-21 Processor architecture with switch matrices for transferring data along buses
US13/176,381 Expired - Fee Related US8904148B2 (en) 2000-12-19 2011-07-05 Processor architecture with switch matrices for transferring data along buses

Country Status (7)

Country Link
US (3) US20040078548A1 (en)
EP (1) EP1368744A2 (en)
JP (2) JP4386636B2 (en)
CN (1) CN1262944C (en)
AU (1) AU9407301A (en)
GB (1) GB2370380B (en)
WO (1) WO2002050624A2 (en)

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050005250A1 (en) * 2003-06-18 2005-01-06 Jones Anthony Mark Data interface for hardware objects
US20060073804A1 (en) * 2004-10-04 2006-04-06 Hiroshi Tanaka Semiconductor integrated circuit and a software radio device
US20070044064A1 (en) * 2003-02-21 2007-02-22 Andrew Duller Processor network
US20070083791A1 (en) * 2003-02-12 2007-04-12 Gajinder Panesar Communications in a processor array
US20070186076A1 (en) * 2003-06-18 2007-08-09 Jones Anthony M Data pipeline transport system
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
US20080168256A1 (en) * 2007-01-08 2008-07-10 Integrated Device Technology, Inc. Modular Distributive Arithmetic Logic Unit
US20080301413A1 (en) * 2006-08-23 2008-12-04 Xiaolin Wang Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US20090132747A1 (en) * 2007-11-19 2009-05-21 International Business Machines Corporation Structure for universal peripheral processor system for soc environments on an integrated circuit
US20090144485A1 (en) * 1996-12-27 2009-06-04 Martin Vorbach Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
US20090149211A1 (en) * 2007-11-05 2009-06-11 Picochip Designs Limited Power control
US20090199167A1 (en) * 2006-01-18 2009-08-06 Martin Vorbach Hardware Definition Method
US20090300336A1 (en) * 2008-05-29 2009-12-03 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US20090300337A1 (en) * 2008-05-29 2009-12-03 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cases and the like
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US20110002426A1 (en) * 2009-01-05 2011-01-06 Picochip Designs Limited Rake Receiver
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US8131909B1 (en) * 2007-09-19 2012-03-06 Agate Logic, Inc. System and method of signal processing engines with programmable logic fabric
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8463312B2 (en) 2009-06-05 2013-06-11 Mindspeed Technologies U.K., Limited Method and device in a communication network
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
US20130227190A1 (en) * 2012-02-27 2013-08-29 Raytheon Company High Data-Rate Processing System
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8712469B2 (en) 2011-05-16 2014-04-29 Mindspeed Technologies U.K., Limited Accessing a base station
US8798630B2 (en) 2009-10-05 2014-08-05 Intel Corporation Femtocell base station
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US8849340B2 (en) 2009-05-07 2014-09-30 Intel Corporation Methods and devices for reducing interference in an uplink
US8862076B2 (en) 2009-06-05 2014-10-14 Intel Corporation Method and device in a communication network
US8904148B2 (en) 2000-12-19 2014-12-02 Intel Corporation Processor architecture with switch matrices for transferring data along buses
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9042434B2 (en) 2011-04-05 2015-05-26 Intel Corporation Filter
US9107136B2 (en) 2010-08-16 2015-08-11 Intel Corporation Femtocell access control

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370381B (en) * 2000-12-19 2003-12-24 Picochip Designs Ltd Processor architecture
GB2391083B (en) 2002-07-19 2006-03-01 Picochip Designs Ltd Processor array
GB2396446B (en) 2002-12-20 2005-11-16 Picochip Designs Ltd Array synchronization
GB2397668B (en) * 2003-01-27 2005-12-07 Picochip Designs Ltd Processor array
JP5013326B2 (en) * 2004-11-30 2012-08-29 独立行政法人理化学研究所 The composition for the plant environmental stress tolerance
GB2420884B (en) * 2004-12-03 2009-04-15 Picochip Designs Ltd Processor architecture
US8301905B2 (en) * 2006-09-08 2012-10-30 Inside Secure System and method for encrypting data
GB2457309A (en) 2008-02-11 2009-08-12 Picochip Designs Ltd Process allocation in a processor array using a simulated annealing method
GB2457310B (en) 2008-02-11 2012-03-21 Picochip Designs Ltd Signal routing in processor arrays
GB2459674A (en) 2008-04-29 2009-11-04 Picochip Designs Ltd Allocating communication bandwidth in a heterogeneous multicore environment
JP5365639B2 (en) * 2008-09-16 2013-12-11 日本電気株式会社 Signal transmission method in the semiconductor programmable device and semiconductor programmable device
WO2010032865A1 (en) * 2008-09-16 2010-03-25 日本電気株式会社 Semiconductor programmable device and signal transferring method in semiconductor programmable device
WO2010032861A1 (en) * 2008-09-16 2010-03-25 日本電気株式会社 Semiconductor programmable device and control method therefor
GB2471067B (en) * 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
US9330040B2 (en) * 2013-09-12 2016-05-03 Qualcomm Incorporated Serial configuration of a reconfigurable instruction cell array
NL2015114B1 (en) * 2015-07-07 2017-02-01 Univ Delft Tech Scalable computation architecture in a memristor-based array.

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974190A (en) * 1988-12-05 1990-11-27 Digital Equipment Corporation Pass-through and isolation switch
US5241491A (en) * 1990-08-02 1993-08-31 Carlstedt Elektronik Ab Method for performing arithmetic, logical and related operations and a numerical arithmetic unit
US5408676A (en) * 1992-01-07 1995-04-18 Hitachi, Ltd. Parallel data processing system with plural-system bus configuration capable of fast data communication between processors by using common buses

Family Cites Families (225)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380046A (en) 1979-05-21 1983-04-12 Nasa Massively parallel processor computer
US4389715A (en) 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4574345A (en) 1981-04-01 1986-03-04 Advanced Parallel Systems, Inc. Multiprocessor computer system utilizing a tapped delay line instruction bus
JPS58137192A (en) 1981-12-29 1983-08-15 Fujitsu Ltd Semiconductor storage device
US4622632A (en) 1982-08-18 1986-11-11 Board Of Regents, University Of Washington Data processing system having a pyramidal array of processors
GB2129585B (en) 1982-10-29 1986-03-05 Inmos Ltd Memory system including a faulty rom array
US4724517A (en) 1982-11-26 1988-02-09 Inmos Limited Microcomputer with prefixing functions
JPH036545B2 (en) 1983-01-18 1991-01-30 Mitsubishi Electric Corp
US4698746A (en) 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US5152000A (en) 1983-05-31 1992-09-29 Thinking Machines Corporation Array communications arrangement for parallel processor
US4589066A (en) 1984-05-31 1986-05-13 General Electric Company Fault tolerant, frame synchronization for multiple processor systems
JPS61123968U (en) 1985-01-21 1986-08-04
EP0190813B1 (en) 1985-01-29 1991-09-18 Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Processing cell for fault tolerant arrays
US4720780A (en) 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4736291A (en) 1985-11-22 1988-04-05 Texas Instruments Incorporated General-purpose array processor
US5036453A (en) 1985-12-12 1991-07-30 Texas Instruments Incorporated Master/slave sequencing processor
IT1184015B (en) 1985-12-13 1987-10-22 Elsag multiprocessor system more hierarchical levels
GB8612454D0 (en) 1986-05-22 1986-07-02 Inmos Ltd Redundancy scheme for multi-stage apparatus
US5038386A (en) * 1986-08-29 1991-08-06 International Business Machines Corporation Polymorphic mesh network image processing system
US4914653A (en) 1986-12-22 1990-04-03 American Telephone And Telegraph Company Inter-processor communication protocol
US5109329A (en) 1987-02-06 1992-04-28 At&T Bell Laboratories Multiprocessing method and arrangement
US4943912A (en) 1987-10-13 1990-07-24 Hitachi, Ltd. Parallel processor system having control processor and array control apparatus for selectively activating different processors
GB2211638A (en) 1987-10-27 1989-07-05 Ibm Simd array processor
AU616213B2 (en) 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US5692139A (en) 1988-01-11 1997-11-25 North American Philips Corporation, Signetics Div. VLIW processing device including improved memory for avoiding collisions without an excessive number of ports
US4937741A (en) 1988-04-28 1990-06-26 The Charles Stark Draper Laboratory, Inc. Synchronization of fault-tolerant parallel processing systems
US4974146A (en) 1988-05-06 1990-11-27 Science Applications International Corporation Array processor
US4890279A (en) 1988-09-26 1989-12-26 Pacific Bell Multiplexer and computer network using the same
DE68926783D1 (en) * 1988-10-07 1996-08-08 Martin Marietta Corp Parallel data processor
US4965717B1 (en) 1988-12-09 1993-05-25 Tandem Computers Inc
US5253308A (en) 1989-06-21 1993-10-12 Amber Engineering, Inc. Massively parallel digital image data processor using pixel-mapped input/output and relative indexed addressing
EP0424618A3 (en) 1989-10-24 1992-11-19 International Business Machines Corporation Input/output system
DE58908974D1 (en) 1989-11-21 1995-03-16 Itt Ind Gmbh Deutsche Data-controlled array processor.
EP0428771B1 (en) 1989-11-21 1995-02-01 Deutsche ITT Industries GmbH Bidirectional data transfer device
JP2810231B2 (en) 1990-01-30 1998-10-15 ジヨンソン・サービス・カンパニー Positioning method for data in the distributed network system having a node
HU900629D0 (en) * 1990-02-01 1990-04-28 Cellware Mikroelektronikai Kut Cicuit arrangement for inhomogen operating processors with homogen structure and cellular building
US5247694A (en) 1990-06-14 1993-09-21 Thinking Machines Corporation System and method for generating communications arrangements for routing data in a massively parallel processing system
US6928500B1 (en) 1990-06-29 2005-08-09 Hewlett-Packard Development Company, L.P. High speed bus system that incorporates uni-directional point-to-point buses
US5265207A (en) 1990-10-03 1993-11-23 Thinking Machines Corporation Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses
US5708836A (en) 1990-11-13 1998-01-13 International Business Machines Corporation SIMD/MIMD inter-processor communication
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
GB2251320A (en) * 1990-12-20 1992-07-01 Motorola Ltd Parallel processor
US5233615A (en) 1991-06-06 1993-08-03 Honeywell Inc. Interrupt driven, separately clocked, fault tolerant processor synchronization
JP3679813B2 (en) * 1991-07-22 2005-08-03 株式会社日立製作所 Parallel computer
JP2601591B2 (en) 1991-11-26 1997-04-16 富士通株式会社 Parallel computer and the entire-all communication method
JPH06188850A (en) 1992-10-23 1994-07-08 Fujitsu Ltd System and equipment for data transfer
GB9223226D0 (en) * 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
DE69325785D1 (en) 1992-12-29 1999-09-02 Koninkl Philips Electronics Nv Improved architecture for a very long instruction word processor with
US5386495A (en) 1993-02-01 1995-01-31 Motorola, Inc. Method and apparatus for determining the signal quality of a digital signal
JPH0773059A (en) 1993-03-02 1995-03-17 Tandem Comput Inc Fault-tolerant type computer system
US5473731A (en) 1993-07-20 1995-12-05 Intel Corporation Lattice based dynamic programming classification system
EP0652509B1 (en) 1993-11-05 2000-05-10 Intergraph Corporation Instruction cache associative cross-bar switch
DE69435090D1 (en) 1993-12-01 2008-05-29 Marathon Techn Corp A computer system with control units and computer elements
EP0665502B1 (en) 1994-01-27 2002-06-12 Sun Microsystems, Inc. Asynchronous serial communication circuit
US5790879A (en) 1994-06-15 1998-08-04 Wu; Chen-Mie Pipelined-systolic single-instruction stream multiple-data stream (SIMD) array processing with broadcasting control, and method of operating same
US6408402B1 (en) 1994-03-22 2002-06-18 Hyperchip Inc. Efficient direct replacement cell fault tolerant architecture
DE69424304T2 (en) 1994-09-13 2000-11-30 Teranex Orlando Parallel data processor
JP3345626B2 (en) 1994-09-29 2002-11-18 富士通株式会社 Processor abnormality countermeasure method in a processor abnormality countermeasure device and multi-processor systems in the multiprocessor system
US5570045A (en) 1995-06-07 1996-10-29 Lsi Logic Corporation Hierarchical clock distribution system and method
US6199093B1 (en) 1995-07-21 2001-03-06 Nec Corporation Processor allocating method/apparatus in multiprocessor system, and medium for storing processor allocating program
GB2304495B (en) 1995-08-15 1999-12-29 Nokia Mobile Phones Ltd Radio resource sharing
JPH0954761A (en) 1995-08-15 1997-02-25 Sony Corp Digital signal processor and information processing system
US5795797A (en) 1995-08-18 1998-08-18 Teradyne, Inc. Method of making memory chips using memory tester providing fast repair
US5761514A (en) 1995-08-31 1998-06-02 International Business Machines Corporation Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system
US5754807A (en) 1995-11-20 1998-05-19 Advanced Micro Devices, Inc. Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles
KR100197407B1 (en) 1995-12-28 1999-06-15 유기범 Communication bus architecture between process in the full electronic switching system
US5903771A (en) 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
JP3623840B2 (en) 1996-01-31 2005-02-23 株式会社ルネサステクノロジ Data processing apparatus and a microprocessor
US5860008A (en) 1996-02-02 1999-01-12 Apple Computer, Inc. Method and apparatus for decompiling a compiled interpretive code
JP3715991B2 (en) 1996-02-09 2005-11-16 株式会社日立製作所 Parallel processor
JP2791764B2 (en) * 1996-02-19 1998-08-27 有限会社サングラフィックス Computing device
JPH09223011A (en) * 1996-02-19 1997-08-26 San Graphics:Kk Arithmetic unit
US5959995A (en) 1996-02-22 1999-09-28 Fujitsu, Ltd. Asynchronous packet switching
US5963609A (en) 1996-04-03 1999-10-05 United Microelectronics Corp. Apparatus and method for serial data communication between plurality of chips in a chip set
US6381293B1 (en) 1996-04-03 2002-04-30 United Microelectronics Corp. Apparatus and method for serial data communication between plurality of chips in a chip set
JPH09307428A (en) * 1996-05-14 1997-11-28 Hitachi Ltd Variable logic integrated circuit
US5826054A (en) 1996-05-15 1998-10-20 Philips Electronics North America Corporation Compressed Instruction format for use in a VLIW processor
US5802561A (en) 1996-06-28 1998-09-01 Digital Equipment Corporation Simultaneous, mirror write cache
US5805839A (en) 1996-07-02 1998-09-08 Advanced Micro Devices, Inc. Efficient technique for implementing broadcasts on a system of hierarchical buses
US6236365B1 (en) 1996-09-09 2001-05-22 Tracbeam, Llc Location of a mobile station using a plurality of commercial wireless infrastructures
US6683876B1 (en) * 1996-09-23 2004-01-27 Silicon Graphics, Inc. Packet switched router architecture for providing multiple simultaneous communications
US5926640A (en) 1996-11-01 1999-07-20 Digital Equipment Corporation Skipping clock interrupts during system inactivity to reduce power consumption
US5719445A (en) 1996-12-23 1998-02-17 Sgs-Thomson Microelectronics, Inc. Input delay control
FI107982B (en) 1997-05-06 2001-10-31 Nokia Mobile Phones Ltd Selection of the cell based on the usage profile of a cellular radio system
US5946484A (en) 1997-05-08 1999-08-31 The Source Recovery Company, Llc Method of recovering source code from object code
JP2976932B2 (en) 1997-06-09 1999-11-10 日本電気株式会社 Image matching circuit and an image matching integrated circuits
US6167502A (en) 1997-10-10 2000-12-26 Billions Of Operations Per Second, Inc. Method and apparatus for manifold array processing
DE19746894C2 (en) 1997-10-23 1999-10-28 Siemens Ag A method and wireless communication system for data transmission
US6055285A (en) 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6069490A (en) 1997-12-02 2000-05-30 Xilinx, Inc. Routing architecture using a direct connect routing mesh
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6122677A (en) 1998-03-20 2000-09-19 Micron Technology, Inc. Method of shortening boot uptime in a computer system
JP3738128B2 (en) 1998-03-25 2006-01-25 シャープ株式会社 Data driven information processor
JP3611714B2 (en) * 1998-04-08 2005-01-19 株式会社ルネサステクノロジ Processor
US5923615A (en) 1998-04-17 1999-07-13 Motorlola Synchronous pipelined burst memory and method for operating same
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6101599A (en) 1998-06-29 2000-08-08 Cisco Technology, Inc. System for context switching between processing elements in a pipeline of processing elements
US6356606B1 (en) 1998-07-31 2002-03-12 Lucent Technologies Inc. Device and method for limiting peaks of a signal
US6393026B1 (en) 1998-09-17 2002-05-21 Nortel Networks Limited Data packet processing system and method for a router
JP3031354B1 (en) 1998-09-30 2000-04-10 日本電気株式会社 Cdma receiver and its multipath finger assignment method and recording medium recording the control program
US6360259B1 (en) 1998-10-09 2002-03-19 United Technologies Corporation Method for optimizing communication speed between processors
EP1054523A4 (en) 1998-11-19 2006-07-19 Mitsubishi Electric Corp Receiver and demodulator applied to mobile communication system
US6249861B1 (en) 1998-12-03 2001-06-19 Sun Microsystems, Inc. Instruction fetch unit aligner for a non-power of two size VLIW instruction
US6173386B1 (en) 1998-12-14 2001-01-09 Cisco Technology, Inc. Parallel processor with debug capability
EP1181648A1 (en) 1999-04-09 2002-02-27 Pixelfusion Limited Parallel data processing apparatus
JP2000305781A (en) 1999-04-21 2000-11-02 Mitsubishi Electric Corp Vliw system processor, code compressing device, code compressing method and medium for recording code compression program
FR2795839B1 (en) 1999-07-02 2001-09-07 Commissariat Energie Atomique Reconfiguration Method applicable to an identical functional elements network
JP2001034471A (en) 1999-07-19 2001-02-09 Mitsubishi Electric Corp Vliw system processor
US6681341B1 (en) 1999-11-03 2004-01-20 Cisco Technology, Inc. Processor isolation method for integrated multi-processor systems
JP3468189B2 (en) 2000-02-02 2003-11-17 日本電気株式会社 Pattern generating circuit and the multi-path detection circuit as well as multi-path detection method using the same
JP3674515B2 (en) * 2000-02-25 2005-07-20 日本電気株式会社 Array-type processor
US7184457B2 (en) 2000-02-28 2007-02-27 Texas Instruments Incorporated Spread spectrum path estimation
JP2003526157A (en) 2000-03-08 2003-09-02 サン・マイクロシステムズ・インコーポレイテッド vliw computer processing architecture with on-chip dynamic ram
US6961782B1 (en) 2000-03-14 2005-11-01 International Business Machines Corporation Methods for routing packets on a linear array of processors
FI20001289A (en) 2000-05-30 2001-12-01 Nokia Mobile Phones Ltd Method and arrangement for reducing frequency offset in a radio receiver
DE60126533T2 (en) 2000-06-19 2007-11-22 Broadcom Corp., Irvine Exchange with a memory management unit to improve Flusssteurung
AUPQ820000A0 (en) 2000-06-20 2000-07-13 Berangi, R. Peak power reduction schemes for multi-code cdma and critically sampled complex gaussian signals
US6693456B2 (en) 2000-08-04 2004-02-17 Leopard Logic Inc. Interconnection network for a field programmable gate array
US6829296B1 (en) 2000-09-20 2004-12-07 Mindspeed Technologies, Inc. Spectrally flat time domain equalizer and methods
US7127588B2 (en) 2000-12-05 2006-10-24 Mindspeed Technologies, Inc. Apparatus and method for an improved performance VLIW processor
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
GB2370381B (en) 2000-12-19 2003-12-24 Picochip Designs Ltd Processor architecture
US6448910B1 (en) 2001-03-26 2002-09-10 Morpho Technologies Method and apparatus for convolution encoding and viterbi decoding of data that utilize a configurable processor to configure a plurality of re-configurable processing elements
US7266354B2 (en) 2001-06-25 2007-09-04 Telefonaktiebolaget Lm Ericsson (Publ) Reducing the peak-to-average power ratio of a communication signal
JP2003005958A (en) 2001-06-25 2003-01-10 Pacific Design Kk Data processor and method for controlling the same
AU2002345190A1 (en) 2001-06-28 2003-03-03 King's College London Electronic data communication system
US20030195989A1 (en) 2001-07-02 2003-10-16 Globespan Virata Incorporated Communications system using rings architecture
US7161978B2 (en) 2001-08-29 2007-01-09 Texas Instruments Incorporated Transmit and receive window synchronization
US20040198386A1 (en) 2002-01-16 2004-10-07 Dupray Dennis J. Applications for a wireless location gateway
AU2003207767A1 (en) 2002-02-01 2003-09-02 California Institute Of Technology Hardware-assisted fast router
KR100464406B1 (en) 2002-02-08 2005-01-03 삼성전자주식회사 Apparatus and method for dispatching very long instruction word with variable length
JP3879595B2 (en) 2002-06-19 2007-02-14 日本電気株式会社 Cdma demodulation circuit and cdma mobile communication demodulation method used therefor
GB2391083B (en) 2002-07-19 2006-03-01 Picochip Designs Ltd Processor array
US7340017B1 (en) 2002-07-30 2008-03-04 National Semiconductor Corporation System and method for finger management in a rake receiver
AU2003253159A1 (en) 2002-09-24 2004-04-19 Koninklijke Philips Electronics N.V. Apparatus, method ,and compiler enabling processing of load immediate instructions in a very long instruction word processor
CN100336016C (en) 2002-10-11 2007-09-05 皇家飞利浦电子股份有限公司 VLIW processor with power saving
US7277678B2 (en) 2002-10-28 2007-10-02 Skyworks Solutions, Inc. Fast closed-loop power control for non-constant envelope modulation
US7277474B2 (en) 2002-11-05 2007-10-02 Analog Devices, Inc. Finger allocation for a path searcher in a multipath receiver
CN1503486A (en) 2002-11-07 2004-06-09 三星电子株式会社 Frequency reuse method in an orthogonal frequency division multiplex mobile communication system
US7215126B2 (en) 2002-11-19 2007-05-08 University Of Utah Research Foundation Apparatus and method for testing a signal path from an injection point
GB2398651A (en) 2003-02-21 2004-08-25 Picochip Designs Ltd Automatical task allocation in a processor array
US7613900B2 (en) 2003-03-31 2009-11-03 Stretch, Inc. Systems and methods for selecting input/output configuration in an integrated circuit
WO2004102989A1 (en) 2003-05-14 2004-11-25 Koninklijke Philips Electronics N.V. Time-division multiplexing circuit-switching router
JP4178552B2 (en) 2003-07-24 2008-11-12 株式会社安川電機 Master-slave synchronization communication system
US7103024B2 (en) 2003-10-17 2006-09-05 Motorola, Inc. Wireless local area network future service quality determination method
US7237055B1 (en) 2003-10-22 2007-06-26 Stretch, Inc. System, apparatus and method for data path routing configurable to perform dynamic bit permutations
CN1617479A (en) 2003-11-14 2005-05-18 北京三星通信技术研究有限公司 Method for supporting pilot frequency enhancement in up line special channel enhancement in broad band CDMA
US7047009B2 (en) 2003-12-05 2006-05-16 Flarion Technologies, Inc. Base station based methods and apparatus for supporting break before make handoffs in a multi-carrier system
WO2005076492A1 (en) 2004-02-03 2005-08-18 Matsushita Electric Industrial Co., Ltd. Rake reception device and rake reception method
US7207020B1 (en) 2004-02-09 2007-04-17 Altera Corporation Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool
JP4283131B2 (en) 2004-02-12 2009-06-24 パナソニック株式会社 Processor and compilation method
WO2005109916A2 (en) 2004-04-15 2005-11-17 Flarion Technologies, Inc. Multi-carrier communications methods and apparatus
US7801029B2 (en) 2004-04-30 2010-09-21 Hewlett-Packard Development Company, L.P. System for selecting routes for retransmission in a network
GB2414308B (en) 2004-05-17 2007-08-15 Advanced Risc Mach Ltd Program instruction compression
GB2414896A (en) 2004-06-01 2005-12-07 Toshiba Res Europ Ltd WLAN load balancing
US7773950B2 (en) 2004-06-16 2010-08-10 Telefonaktiebolaget Lm Ericsson (Publ) Benign interference suppression for received signal quality estimation
KR100590561B1 (en) 2004-10-12 2006-06-19 삼성전자주식회사 Method and apparatus for pitch estimation
US7233800B2 (en) 2004-10-14 2007-06-19 Qualcomm, Incorporated Wireless terminal location using apparatus and methods employing carrier diversity
WO2006059172A1 (en) 2004-12-01 2006-06-08 Nokia Corporation Method, device and system for power control in wireless communication systems using cdma-based technologies
US7428721B2 (en) 2004-12-01 2008-09-23 Tabula, Inc. Operational cycle assignment in a configurable IC
US8964912B2 (en) 2005-05-31 2015-02-24 Telefonaktiebolaget Lm Ericsson (Publ) Adaptive timing recovery via generalized RAKE reception
US7804719B1 (en) 2005-06-14 2010-09-28 Xilinx, Inc. Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode
DE102005038122B4 (en) 2005-08-11 2009-01-29 Nokia Siemens Networks Gmbh & Co.Kg Method and arrangement for pre-distorting a base-band input signal
US8116780B2 (en) 2005-08-19 2012-02-14 Electronics And Telecommunications Research Institute Dynamic resource allocation method based on frequency reuse partitioning for OFMDA/FDD system, and frame transmission method therefor
EP1941764B1 (en) 2005-10-04 2016-04-20 Telefonaktiebolaget LM Ericsson (publ) Automatic building of neighbor lists in mobile system
US8014476B2 (en) 2005-11-07 2011-09-06 Qualcomm, Incorporated Wireless device with a non-compensated crystal oscillator
DE602005019799D1 (en) 2005-11-10 2010-04-15 Ericsson Telefon Ab L M Arrangements in a mobile telecommunications network
US7925292B2 (en) 2006-01-26 2011-04-12 Qualcomm Incorporated Methods, devices and systems relating to reselecting cells in a cellular wireless communications system
US20070220586A1 (en) 2006-03-01 2007-09-20 Norman Salazar Computing resource assignment method and apparatus using genetic algorithms
US7904848B2 (en) 2006-03-14 2011-03-08 Imec System and method for runtime placement and routing of a processing array
US20070248191A1 (en) 2006-04-25 2007-10-25 Telefonaktiebolaget Lm Ericsson (Publ) Baseband sample selection
US7613444B2 (en) 2006-04-28 2009-11-03 Telefonaktiebolaget Lm Ericsson (Publ) Dynamic building of monitored set
JP4734539B2 (en) 2006-05-15 2011-07-27 学校法人慶應義塾 System and method for searching for a shortest path between the nodes included in the network
US8369859B2 (en) 2006-05-22 2013-02-05 Alcatel Lucent Controlling transmit power of picocell base units
KR100964546B1 (en) 2006-07-04 2010-06-21 삼성전자주식회사 Method and system for controlling in a communication system
US8160629B2 (en) 2006-09-07 2012-04-17 Airvana, Corp. Controlling reverse link interference in private access points for wireless networking
US9629096B2 (en) 2006-12-15 2017-04-18 Alcatel-Lucent Usa Inc. Controlling uplink power for picocell communications within a macrocell
JP2008160380A (en) 2006-12-22 2008-07-10 Nec Corp Inter-cell interference suppression method, radio base station, and user terminal
GB2445989A (en) 2007-01-23 2008-07-30 Siemens Ag Controlling interference between first and second communication systems
GB2447439B (en) 2007-02-02 2012-01-25 Ubiquisys Ltd Access point power control
WO2008099340A1 (en) 2007-02-12 2008-08-21 Nokia Corporation Apparatus, method and computer program product providing inter-node b signalling of cell status information
WO2008155732A2 (en) 2007-06-19 2008-12-24 Nokia Corporation Resource-block-cluster-based load indication
US7724707B2 (en) 2007-06-26 2010-05-25 Motorola, Inc. Network for a cellular communication system and a method of operation therefor
US8700083B2 (en) 2007-08-10 2014-04-15 Qualcomm Incorporated Adaptation of transmit power based on maximum received signal strength
EP2187698A4 (en) 2007-08-13 2015-03-18 Ntt Docomo Inc Mobile communication system, general base station device, base station device, and base station status control method
US8537774B2 (en) 2007-08-16 2013-09-17 Apple Inc. Capacity optimisation in a cellular wireless network
JP4994168B2 (en) 2007-09-25 2012-08-08 株式会社日立国際電気 Communication equipment
US20100195525A1 (en) 2007-09-27 2010-08-05 Nokia Corporation Preliminary Neighbor Cell Suitability Check
US8213391B2 (en) 2007-10-05 2012-07-03 Via Telecom, Inc. Time synchronization of femtocell
US20090097452A1 (en) 2007-10-12 2009-04-16 Qualcomm Incorporated Femto cell synchronization and pilot search methodology
US9198122B2 (en) 2007-10-12 2015-11-24 Qualcomm Incorporated Method and system for service redirection background
JP5482203B2 (en) 2007-10-22 2014-05-07 日本電気株式会社 Wireless communication system, a base station, a radio resource management method, and a base station control program
US8150443B2 (en) 2007-10-31 2012-04-03 Nokia Siemens Networks Oy Overload indicator for adjusting open loop power control parameters
GB2454263A (en) 2007-11-05 2009-05-06 Picochip Designs Ltd Generating debug information from low level program code
EP2071738B1 (en) 2007-12-13 2016-09-07 Alcatel-Lucent USA Inc. A picocell base station and method of adjusting transmission power of pilot signals therefrom
US8355727B2 (en) 2007-12-19 2013-01-15 Airvana, Corp. Proximity detection in a network
US8130702B2 (en) 2007-12-31 2012-03-06 Intel Corporation OFDMA based communication system
US8379550B2 (en) 2008-01-31 2013-02-19 Samsung Electronics Co., Ltd. Location based femtocell device configuration and handoff
KR101295122B1 (en) 2008-02-25 2013-08-09 삼성전자주식회사 Method and apparatus for estmating echo cancellation filter using a scheme to predict channel coefficients in multi-carrier system
US8260206B2 (en) 2008-04-16 2012-09-04 Qualcomm Incorporated Methods and apparatus for uplink and downlink inter-cell interference coordination
US8169931B2 (en) 2008-05-21 2012-05-01 Airhop Communications, Inc. Method and apparatus for base stations and their provisioning, management, and networking
US8401479B2 (en) 2008-08-08 2013-03-19 Motorola Mobility Llc Managing interference from femtocells
US8274903B2 (en) 2008-08-20 2012-09-25 Qualcomm Incorporated Methods and apparatus for switching between a base channel and a 60 GHz channel
GB2463074B (en) 2008-09-02 2010-12-22 Ip Access Ltd Communication unit and method for selective frequency synchronisation in a cellular communication network
US20100054237A1 (en) 2008-09-04 2010-03-04 Motorola, Inc. Synchronization for femto-cell base stations
KR100967657B1 (en) 2008-09-19 2010-07-07 연세대학교 산학협력단 Method and apparatus for synchronization of femtocell base station
WO2010039908A1 (en) 2008-09-30 2010-04-08 Spridercloud Wireless Methods and apparatus for generating, reporting and/or using interference cancellation information
US8160528B2 (en) 2008-10-24 2012-04-17 Motorola Solutions, Inc. Method and device for detecting presence of a carrier signal in a received signal
US8396050B2 (en) 2008-10-31 2013-03-12 Intel Corporation Techniques for femto cell synchronization in wireless networks
US20100111070A1 (en) 2008-11-01 2010-05-06 Broadband Wireless Technology Corp. Apparatus, Method, And Tangible Machine-Readable Medium Thereof For Time Synchronization Procedure In A Cellular Network
CN101754351B (en) 2008-12-05 2013-09-25 电信科学技术研究院 Method, system and apparatus for synchronization of home base station
CN101442348B (en) 2008-12-22 2013-08-07 华为技术有限公司 Method, apparatus, system for clipping signal and signal radiation system
GB2466661B (en) 2009-01-05 2014-11-26 Intel Corp Rake receiver
US9397876B2 (en) 2009-02-20 2016-07-19 Broadcom Corporation Synchronization and frame structure determination of a base station
WO2010098934A2 (en) 2009-02-24 2010-09-02 Jeffrey Harrang Optimizing short-range wireless communications within a larger wireless network
WO2010098970A2 (en) 2009-02-24 2010-09-02 Elliott Hoole Usage-based output power level adjustments for self-optimizing radio access nodes
US8886205B2 (en) 2009-03-02 2014-11-11 Qualcomm Incorporated Timing adjustment for synchronous operation in a wireless network
US8660600B2 (en) 2009-03-12 2014-02-25 Qualcomm Incorporated Over-the-air overload indicator
JP5226586B2 (en) 2009-03-31 2013-07-03 Kddi株式会社 Wireless communication terminal and communication method selection method
CN101873688B (en) 2009-04-22 2013-05-08 鼎桥通信技术有限公司 Synchronization method of femtocell and macrocell and access method of user equipment
US8761753B2 (en) 2009-04-23 2014-06-24 Qualcomm Incorporated Communication of an interference condition in wireless communications systems
GB2471988A (en) 2009-04-27 2011-01-26 Nec Corp Communication System comprising Home Base Station and associated Closed Subscriber Group
US8825051B2 (en) 2009-05-01 2014-09-02 Qualcomm Incorporated Idle handoff to hybrid femto cell based on system selection database
EP2326118B1 (en) 2009-11-20 2014-10-22 Alcatel Lucent A femtocell base station, and a method of controlling a femtocell base station
US9331800B2 (en) 2009-11-24 2016-05-03 Qualcomm Incorporated Virtual home channel for mobile broadcast networks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974190A (en) * 1988-12-05 1990-11-27 Digital Equipment Corporation Pass-through and isolation switch
US5241491A (en) * 1990-08-02 1993-08-31 Carlstedt Elektronik Ab Method for performing arithmetic, logical and related operations and a numerical arithmetic unit
US5408676A (en) * 1992-01-07 1995-04-18 Hitachi, Ltd. Parallel data processing system with plural-system bus configuration capable of fast data communication between processors by using common buses

Cited By (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8156312B2 (en) 1996-12-09 2012-04-10 Martin Vorbach Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
US7822968B2 (en) 1996-12-09 2010-10-26 Martin Vorbach Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
US7899962B2 (en) 1996-12-20 2011-03-01 Martin Vorbach I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US8195856B2 (en) 1996-12-20 2012-06-05 Martin Vorbach I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US20090144485A1 (en) * 1996-12-27 2009-06-04 Martin Vorbach Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
USRE45109E1 (en) 1997-02-08 2014-09-02 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
USRE44383E1 (en) 1997-02-08 2013-07-16 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE44365E1 (en) 1997-02-08 2013-07-09 Martin Vorbach Method of self-synchronization of configurable elements of a programmable module
USRE45223E1 (en) 1997-02-08 2014-10-28 Pact Xpp Technologies Ag Method of self-synchronization of configurable elements of a programmable module
US8819505B2 (en) 1997-12-22 2014-08-26 Pact Xpp Technologies Ag Data processor having disabled cores
US8468329B2 (en) 1999-02-25 2013-06-18 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8726250B2 (en) 1999-06-10 2014-05-13 Pact Xpp Technologies Ag Configurable logic integrated circuit having a multidimensional structure of configurable elements
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US8312200B2 (en) 1999-06-10 2012-11-13 Martin Vorbach Processor chip including a plurality of cache elements connected to a plurality of processor cores
US8301872B2 (en) 2000-06-13 2012-10-30 Martin Vorbach Pipeline configuration protocol and configuration unit communication
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9047440B2 (en) 2000-10-06 2015-06-02 Pact Xpp Technologies Ag Logical cell array and bus system
US8471593B2 (en) 2000-10-06 2013-06-25 Martin Vorbach Logic cell array and bus system
US8904148B2 (en) 2000-12-19 2014-12-02 Intel Corporation Processor architecture with switch matrices for transferring data along buses
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8312301B2 (en) 2001-03-05 2012-11-13 Martin Vorbach Methods and devices for treating and processing data
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
US8099618B2 (en) 2001-03-05 2012-01-17 Martin Vorbach Methods and devices for treating and processing data
US8145881B2 (en) 2001-03-05 2012-03-27 Martin Vorbach Data processing device and method
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US8869121B2 (en) 2001-08-16 2014-10-21 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8069373B2 (en) 2001-09-03 2011-11-29 Martin Vorbach Method for debugging reconfigurable architectures
US7840842B2 (en) 2001-09-03 2010-11-23 Martin Vorbach Method for debugging reconfigurable architectures
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US8209653B2 (en) 2001-09-03 2012-06-26 Martin Vorbach Router
US8407525B2 (en) 2001-09-03 2013-03-26 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US8429385B2 (en) 2001-09-03 2013-04-23 Martin Vorbach Device including a field having function cells and information providing cells controlled by the function cells
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US8156284B2 (en) 2002-08-07 2012-04-10 Martin Vorbach Data processing method and device
US8281265B2 (en) 2002-08-07 2012-10-02 Martin Vorbach Method and device for processing data
US7928763B2 (en) 2002-09-06 2011-04-19 Martin Vorbach Multi-core processing system
US8803552B2 (en) 2002-09-06 2014-08-12 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7782087B2 (en) 2002-09-06 2010-08-24 Martin Vorbach Reconfigurable sequencer structure
US20160170925A1 (en) * 2002-09-06 2016-06-16 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units
US8310274B2 (en) 2002-09-06 2012-11-13 Martin Vorbach Reconfigurable sequencer structure
US9817790B2 (en) * 2002-09-06 2017-11-14 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units
US20070083791A1 (en) * 2003-02-12 2007-04-12 Gajinder Panesar Communications in a processor array
US20070044064A1 (en) * 2003-02-21 2007-02-22 Andrew Duller Processor network
US7987340B2 (en) * 2003-02-21 2011-07-26 Gajinder Panesar Communications in a processor array
US7409533B2 (en) 2003-06-18 2008-08-05 Ambric, Inc. Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information
US20050015733A1 (en) * 2003-06-18 2005-01-20 Ambric, Inc. System of hardware objects
US20050055657A1 (en) * 2003-06-18 2005-03-10 Jones Anthony Mark Integrated circuit development system
US7673275B2 (en) 2003-06-18 2010-03-02 Nethra Imaging, Inc. Development system for an integrated circuit having standardized hardware objects
US7139985B2 (en) 2003-06-18 2006-11-21 Ambric, Inc. Development system for an integrated circuit having standardized hardware objects
US7865637B2 (en) 2003-06-18 2011-01-04 Nethra Imaging, Inc. System of hardware objects
US20060282813A1 (en) * 2003-06-18 2006-12-14 Jones Anthony M Development system for an integrated circuit having standardized hardware objects
US20050005250A1 (en) * 2003-06-18 2005-01-06 Jones Anthony Mark Data interface for hardware objects
US7206870B2 (en) 2003-06-18 2007-04-17 Ambric, Inc. Data interface register structure with registers for data, validity, group membership indicator, and ready to accept next member signal
US20070186076A1 (en) * 2003-06-18 2007-08-09 Jones Anthony M Data pipeline transport system
US7406584B2 (en) 2003-06-18 2008-07-29 Ambric, Inc. IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability
US8812820B2 (en) 2003-08-28 2014-08-19 Pact Xpp Technologies Ag Data processing device and method
US7756505B2 (en) * 2004-10-04 2010-07-13 Hitachi, Ltd. Semiconductor integrated circuit and a software radio device
US20060073804A1 (en) * 2004-10-04 2006-04-06 Hiroshi Tanaka Semiconductor integrated circuit and a software radio device
US20090199167A1 (en) * 2006-01-18 2009-08-06 Martin Vorbach Hardware Definition Method
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US20080301413A1 (en) * 2006-08-23 2008-12-04 Xiaolin Wang Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US7571300B2 (en) * 2007-01-08 2009-08-04 Integrated Device Technologies, Inc. Modular distributive arithmetic logic unit
US20080168256A1 (en) * 2007-01-08 2008-07-10 Integrated Device Technology, Inc. Modular Distributive Arithmetic Logic Unit
US8131909B1 (en) * 2007-09-19 2012-03-06 Agate Logic, Inc. System and method of signal processing engines with programmable logic fabric
AU2008306613B2 (en) * 2007-10-06 2013-07-18 Axis Semiconductor Inc. Method and apparatus for real time signal processing
US20090149211A1 (en) * 2007-11-05 2009-06-11 Picochip Designs Limited Power control
US8559998B2 (en) 2007-11-05 2013-10-15 Mindspeed Technologies U.K., Limited Power control
US20090132747A1 (en) * 2007-11-19 2009-05-21 International Business Machines Corporation Structure for universal peripheral processor system for soc environments on an integrated circuit
US8181003B2 (en) 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8078833B2 (en) 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US20090300336A1 (en) * 2008-05-29 2009-12-03 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US20090300337A1 (en) * 2008-05-29 2009-12-03 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cases and the like
US20110002426A1 (en) * 2009-01-05 2011-01-06 Picochip Designs Limited Rake Receiver
US8849340B2 (en) 2009-05-07 2014-09-30 Intel Corporation Methods and devices for reducing interference in an uplink
US8463312B2 (en) 2009-06-05 2013-06-11 Mindspeed Technologies U.K., Limited Method and device in a communication network
US8892154B2 (en) 2009-06-05 2014-11-18 Intel Corporation Method and device in a communication network
US8862076B2 (en) 2009-06-05 2014-10-14 Intel Corporation Method and device in a communication network
US9807771B2 (en) 2009-06-05 2017-10-31 Intel Corporation Method and device in a communication network
US8798630B2 (en) 2009-10-05 2014-08-05 Intel Corporation Femtocell base station
US9107136B2 (en) 2010-08-16 2015-08-11 Intel Corporation Femtocell access control
US9042434B2 (en) 2011-04-05 2015-05-26 Intel Corporation Filter
US8712469B2 (en) 2011-05-16 2014-04-29 Mindspeed Technologies U.K., Limited Accessing a base station
US20130227190A1 (en) * 2012-02-27 2013-08-29 Raytheon Company High Data-Rate Processing System

Also Published As

Publication number Publication date
JP4386636B2 (en) 2009-12-16
WO2002050624A3 (en) 2003-10-16
GB0030993D0 (en) 2001-01-31
CN1489733A (en) 2004-04-14
WO2002050624A2 (en) 2002-06-27
GB2370380B (en) 2003-12-31
US20120191945A1 (en) 2012-07-26
US7996652B2 (en) 2011-08-09
AU9407301A (en) 2002-07-01
EP1368744A2 (en) 2003-12-10
US8904148B2 (en) 2014-12-02
CN1262944C (en) 2006-07-05
GB2370380A (en) 2002-06-26
US20080222339A1 (en) 2008-09-11
JP2008226275A (en) 2008-09-25
JP2004525439A (en) 2004-08-19

Similar Documents

Publication Publication Date Title
Baumgarte et al. PACT XPP—A self-reconfigurable data processing architecture
Hauser et al. Garp: A MIPS processor with a reconfigurable coprocessor
US6594713B1 (en) Hub interface unit and application unit interfaces for expanded direct memory access processor
US6732203B2 (en) Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
US7210139B2 (en) Processor cluster architecture and associated parallel processing methods
US5604915A (en) Data processing system having load dependent bus timing
US5664214A (en) Parallel processing computer containing a multiple instruction stream processing architecture
US10296488B2 (en) Multi-processor with selectively interconnected memory units
US6986021B2 (en) Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US4967326A (en) Microcomputer building block
US6775766B2 (en) Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US7117346B2 (en) Data processing system having multiple register contexts and method therefor
US5774703A (en) Data processing system having a register controllable speed
US7401333B2 (en) Array of parallel programmable processing engines and deterministic method of operating the same
US7020673B2 (en) Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US6526430B1 (en) Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
US20080040574A1 (en) Super-reconfigurable fabric architecture (surfa): a multi-fpga parallel processing architecture for cots hybrid computing framework
US5581778A (en) Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
US20130238878A1 (en) Low power, high performance, heterogeneous, scalable processor architecture
US6804815B1 (en) Sequence control mechanism for enabling out of order context processing
US6496918B1 (en) Intermediate-grain reconfigurable processing device
US5790817A (en) Configurable digital wireless and wired communications system architecture for implementing baseband functionality
US6829696B1 (en) Data processing system with register store/load utilizing data packing/unpacking
CA2313462C (en) Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
KR100910777B1 (en) Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

Legal Events

Date Code Title Description
AS Assignment

Owner name: PICOCHIP DESIGNS LIMITED, GREAT BRITAIN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CLAYDON, ANTHONY PETER JOHN;CLAYDON, ANNE PATRICIA;REEL/FRAME:014776/0680;SIGNING DATES FROM 20031031 TO 20031101

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MINDSPEED TECHNOLOGIES, INC.;MINDSPEED TECHNOLOGIES U.K., LIMITED;MINDSPEED TELECOMMUNICATIONS TECHNOLOGIES DEVELOPMENT (SHENSHEN) CO. LTD.;AND OTHERS;SIGNING DATES FROM 20140204 TO 20140214;REEL/FRAME:032372/0154