US20080163035A1 - Method for Data Distribution and Data Distribution Unit in a Multiprocessor System - Google Patents
Method for Data Distribution and Data Distribution Unit in a Multiprocessor System Download PDFInfo
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- US20080163035A1 US20080163035A1 US11/666,406 US66640605A US2008163035A1 US 20080163035 A1 US20080163035 A1 US 20080163035A1 US 66640605 A US66640605 A US 66640605A US 2008163035 A1 US2008163035 A1 US 2008163035A1
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000015654 memory Effects 0.000 claims description 56
- 238000012545 processing Methods 0.000 claims description 34
- 238000001514 detection method Methods 0.000 claims description 18
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 claims description 6
- 230000001934 delay Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 5
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 4
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000011089 mechanical engineering Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
Definitions
- the present invention relates to a device and a method for data distribution from at least one data source in a multiprocessor system.
- Dual computer systems or dual processor systems are nowadays widely used computer systems for applications critical with regard to safety, in particular in vehicles, such as antilock systems, electronic stability programs (ESP), X-by-wire systems such as drive-by-wire or steer-by-wire or brake-by-wire, etc. or also in other networked systems.
- ESP electronic stability programs
- X-by-wire systems such as drive-by-wire or steer-by-wire or brake-by-wire, etc. or also in other networked systems.
- powerful error detection mechanisms and error handling mechanisms are needed, in particular to counteract transient errors arising, for example, when the size of semiconductor structures of computer systems is reduced. It is relatively difficult to protect the core itself, i.e., the processor.
- One approach is the use of a dual-core system for error detection.
- Such processor units having at least two integrated execution units are known as dual core or multicore architectures.
- Such dual core or multicore architectures are currently proposed mainly for two reasons:
- the two execution units or cores may contribute to an enhanced performance in that the two execution units or cores are considered and treated as two processing units on a single semiconductor module.
- the two execution units or cores process different programs or tasks. This allows enhanced performance; for this reason, this configuration is referred to as performance mode.
- the second reason for using a dual-core or multicore architecture is enhanced reliability in that the two execution units redundantly process the same program.
- the results of the two execution units or CPUs, i.e., cores, are compared, and an error may be detected from the comparison for agreement.
- this configuration is referred to as safety mode or error detection mode.
- both dual processor and multiprocessor systems that work redundantly to recognize hardware errors (see dual core or master checker systems), and dual processor and multiprocessor systems that process different data on their processors. If these two operating modes are combined according to an embodiment of the present invention in a dual processor or multiprocessor system (for the sake of simplicity we shall only refer to dual processor systems; however, the present invention is also applicable to multiprocessor systems), both processors must contain different data in performance mode and the same data in error detection mode.
- An object of the present invention is to provide a unit and a method which delivers the instructions/data to the at least two processors redundantly or differently, depending on the mode, and divides up the memory access rights, in particular in the performance mode.
- processors which, however, also includes the concept of cores or execution units.
- the present invention provides a unit for data distribution from at least one data source in a system having at least two execution units and contains switchover means (ModeSwitch) which make switchover between at least two operating modes of the system possible, the unit being designed in such a way that the data distribution and/or the data source depends on the operating mode.
- Switch switchover means
- the present invention also presents a corresponding data distribution method from at least one data source in a system having at least two execution units, which has switchover means which make switchover between at least two operating modes of the system possible, the data distribution and/or a selection of a data source (instruction memory, data memory, cache in particular) depending on the operating mode.
- the first operating mode corresponds to a safety mode in which the two processing units process the same programs and/or data, and comparison means are provided, which compare the states resulting from the processing of the same programs for agreement.
- the unit according to the present invention and the method according to the present invention make optimized implementation of both modes possible in a dual-processor system.
- the two processors operate in error detection mode (F mode)
- the two processors receive the same data/instructions; if they operate in performance mode (P mode), each processor may access the memory. In that case, this unit manages the accesses to the single memory or peripheral present.
- the unit receives the data/addresses of a processor (here referred to as “master”) and relays them to the components such as memories, bus, etc.
- the second processor here “slave” intends to access the same device.
- the data distribution unit receives this request at a second port, but does not relay it to the other components.
- the data distribution unit transmits the same data to both slave and master and compares the data of the two processors. If they are different, the data distribution unit (here DDU) indicates this via an error signal. Therefore, only the master operates the bus/memory and the slave receives the same data (operating mode as in the case of a dual-core system).
- both processors process different program portions.
- the memory accesses are therefore also different.
- the DDU therefore receives the request of the processors and returns the results/requested data to the processor that requested them. If both processors intend to access the same component at the same time, one processor is set to a wait state until the other one has been served.
- Switchover between the two modes and thus between the different types of operation of the data distribution unit takes place via a control signal, which may be generated by one of the two processors or externally.
- Switchover is advantageously triggered and/or indicated by a control signal, a mode signal in particular, which refers to the operating mode of at least one processing unit, the control signal being generated externally in particular with reference to the processing units.
- switchover is triggered and/or indicated by an instruction, e.g., an instruction which describes an illegal operation (illOp), the instruction being generated by the switchover means, the mode switch unit in particular.
- an instruction e.g., an instruction which describes an illegal operation (illOp)
- the instruction being generated by the switchover means, the mode switch unit in particular.
- Input data of both processing units are advantageously compared for agreement in an operating mode which corresponds to a safety mode (F mode) and/or also output data of both processing units are compared for agreement in an operating mode which corresponds to a safety mode (F mode).
- F mode safety mode
- F mode safety mode
- the data to be distributed are advantageously relayed to at least one additional component, a processing unit for example, the data to be distributed being extended by an error detection code prior to relaying.
- the input data may also be relayed to at least one additional component, a processing unit in particular, the input data being extended by an error detection code prior to relaying.
- the output data may also be relayed to at least one additional component, the output data being extended by an error detection code prior to relaying.
- an error signal is advantageously output if an error is detected thanks to the error detection code.
- an error signal is output only in the safety mode (F mode).
- a delay component which delays the preceding data by a clock pulse offset as a function of the clock pulse offset between the two processing units in the particular operating mode, may be included according to the present invention.
- FIG. 1 shows a schematic illustration of a dual-core computer system.
- FIG. 2 shows an example embodiment of the data distribution unit according to the present invention.
- the data to be distributed are advantageously read from a memory and then distributed to the processing units.
- Data distribution is advantageously controlled by state machines, two state machines being provided for each processing unit. They are advantageously configured as one synchronous state machine and one asynchronous state machine.
- a system is provided with such a unit according to the present invention, a monitoring circuit external to the unit being also provided, which detects an error if an intended switchover between the operating modes does not take place.
- the DDU unit delays the data for the slave as needed, i.e., it stores the master's output data until they may be compared to the slave's output data for error detection.
- the clock pulse offset is elucidated in more detail with reference to FIG. 1 .
- FIG. 1 shows a dual-core system having a first computer 100 , in particular a master computer and a second computer 101 , in particular a slave computer.
- the entire system is operated at a predefinable clock pulse, i.e., in predefinable clock cycles CLK.
- the clock pulse is supplied to the computers via clock input CLK 1 of computer 100 and clock input CLK 2 of computer 101 .
- first computer 100 and second computer 101 operate at a predefinable time offset or a predefinable clock pulse offset. Any desired time period may be defined for a time offset, and also any desired clock pulse regarding an offset of the clock pulses.
- This may be an offset by an integral number of clock pulses, but also, as shown in this example, an offset by 1.5 clock pulses, first computer 100 working, i.e., being operated here 1.5 clock pulses ahead of second computer 101 .
- This offset may prevent common mode failures from interfering with the computers or processors, i.e., the cores of the dual-core system, in the same way and thus from remaining undetected.
- due to the offset such common mode failures affect the computers at different points in time during the program run and thus have different effects for the two computers, which makes errors detectable. Under certain circumstances, effects of errors of the same type would not be detectable in a comparison without a clock pulse offset; this is avoided by the method according to the present invention.
- 1.5 clock pulses in this particular case of a dual-core system offset modules 112 through 115 are provided.
- this system is designed to operate at a predefined time offset or clock pulse offset, here of 1.5 clock pulses, i.e., while one of the computers, e.g., computer 100 , is directly addressing external components 103 and 104 in particular, second computer 101 is running with a delay of exactly 1.5 clock pulses.
- computer 101 is supplied with the inverted clock signal at clock input CLK 2 .
- the above-mentioned terminals of the computer i.e., its data and/or instructions, must therefore also be delayed by the above-mentioned clock pulses, here 1.5 clock pulses in particular; as mentioned previously offset or delay modules 112 through 115 are provided for this purpose.
- components 103 and 104 are provided, which are connected to the two computers 100 and 101 via bus 116 , having bus lines 116 A, 116 B, and 116 C, and bus 117 , having bus lines 117 A and 117 B.
- Bus 117 is an instruction bus, 117 A being an instruction address bus and 117 B being the partial instruction (data) bus.
- Address bus 117 A is connected to computer 100 via an instruction address terminal IA 1 (instruction address 1 ) and to computer 101 via an instruction address terminal IA 2 (instruction address 2 ).
- the instructions proper are transmitted via partial instruction bus 117 B, which is connected to computer 100 via an instruction terminal I 1 (instruction 1 ) and to computer 101 via an instruction terminal I 2 (instruction 2 ).
- this instruction bus 117 having 117 A and 117 B one component 103 , an instruction memory, for example, a safe instruction memory in particular or the like, is connected in between. This component, in particular as an instruction memory, is also operated at clock rate CLK in this example.
- a data bus 116 has a data address bus or data address line 116 A and a data bus or data line 116 B.
- Data address bus or data address line 116 A is connected to computer 100 via a data address terminal DA 1 (data address 1 ) and to computer 101 via a data address terminal DA 2 (data address 2 ).
- data bus or data line 116 B is connected to computer 100 via a data terminal DO 1 (data out 1 ) and to computer 101 via a data terminal DO 2 (data out 2 ).
- data bus 116 has data bus line 116 C, which is connected to computer 100 via a data terminal DI 1 (data in 1 ) and to computer 101 via a data terminal DI 2 (data in 2 ).
- a component 104 a data memory for example, a safe data memory in particular or the like, is connected in between.
- This component 104 is also supplied with clock cycle CLK.
- Components 103 and 104 represent any components that are connected to the computers of the dual-core system via a data bus and/or instruction bus and are able to receive or output erroneous data and/or instructions corresponding to accesses via data and/or instructions of the dual-core system for read and/or write operations.
- Error identifier generators 105 , 106 , and 107 which generate an error identifier such as a parity bit, or another error code such as an error correction code (ECC), or the like, are provided for error prevention.
- ECC error correction code
- appropriate error identifier checking devices 108 and 109 are also provided for checking the particular error identifier, i.e., the parity bit or another error code such as ECC, for example.
- a computer, computer 100 in particular in this case may write or read erroneous data and/or instructions into components, external components in particular such as memory 103 or 104 in particular in this case, but also with regard to other users or actuators or sensors during this time or clock pulse offset.
- a delay unit 102 is connected into the lines of the data bus and/or into the instruction bus. For the sake of clarity, only connection into the data bus is depicted. Of course, connection into the instruction bus is also possible and conceivable.
- This delay unit 102 delays the accesses, the memory accesses in particular in this case, so that a possible time offset or clock pulse offset is compensated, in particular in the case of an error detection, for example, via comparators 110 and 111 , at least until the error signal is generated in the dual-core system, i.e., the error is detected in the dual-core system.
- Different variants may be implemented:
- a delayed write operation may then be converted into a read operation via a change signal, e.g., the error signal, in order to avoid erroneous writing.
- DDU data distribution unit
- switch detect Switchover between the two modes is detected by the “switch detect” units.
- the unit is situated between the cache and the processor on the instruction bus and shows whether the IllOp instruction is loaded into the processor. If the instruction is detected, this event is communicated to the mode switch unit.
- the switch detect unit is provided separately for each processor. The switch detect unit does not have to have an error-tolerant design, since it is present in duplicate, i.e., redundantly. It is also conceivable to design this unit to be error-tolerant and thus without redundancy.
- ModeSwitch Switchover between the two modes is triggered by the “switch detect” unit. If a switchover is to be performed from lock mode to split mode, both switch detect units detect the switchover, since both processors are processing the same program code in the lock mode.
- the switch detect unit of processor 1 detects these 1.5 clock pulses before the switch detect unit of processor 2 .
- the mode switch unit stops processor 1 for two pulses with the aid of the wait signal.
- Processor 2 is also stopped 1.5 clock pulses later, but only for one-half of a clock pulse, thus being synchronized to the system clock.
- the status signal is subsequently switched to split for the other components, and the two processors continue to operate. For the two processors to execute different tasks, they must diverge in the program code.
- the processor ID read is different for each of the two processors. If a comparison is to be made with a reference processor ID, the corresponding processor may be brought to another program point using a conditional jump instruction. When switching over from split mode to lock mode, this is noticed by a processor, i.e., by one before the other. This processor will execute program code containing the switchover instruction. This is now registered by the switch detect unit, which informs the mode switch unit accordingly. The mode switch unit stops the corresponding processor and informs the second one of the synchronization intent via an interrupt. The second processor receives an interrupt and may now execute a software routine to terminate its task. It then jumps to the program point where the switchover instruction is located.
- Its switch detect unit now also signals the intent to change modes to the mode switch unit.
- the wait signal is deactivated for processor 1 and, 1.5 clock pulses later, for processor 2 .
- both processors work synchronously with a clock pulse offset of 1.5 clock pulses.
- both switch detect units must inform the mode switch unit that they intend to switch to the split mode. If the switchover intent is only communicated by one unit, the error is detected by the comparator units, since these continue to receive data from one of the two processors, and these data are different from that of the stopped processor.
- both processors are in the split mode and one does not switch back to the lock mode, this may be detected by an external watchdog.
- the watchdog notices that the waiting processor is no longer sending messages. If there is only one watchdog signal for the processor system, the watchdog may only be triggered in the lock mode. The watchdog would thus detect that no mode switchover has taken place.
- the mode signal is in the form of a dual-rail signal, where 10 stands for the lock mode and 01 for the split mode. 00 and 11 indicate errors.
- IramControl Access to the instruction memory of both processors is controlled via the IRAM control, which must have a reliable design, since it is a single point of failure. It has two state machines for each processor: a synchronous state machine iram 1 clkreset and an asynchronous state machine readiram 1 . In the safety-critical mode, the state machines of the two processors monitor one another, and in the performance mode they operate separately.
- Reloading of the two caches of the processors is controlled by two state machines, one synchronous state machine iramclkreset and an asynchronous state machine readiram. These two state machines divide the memory accesses in the split mode. Processor 1 has the higher priority. After an access to the main memory by processor 1 , if both processors now intend to access the main memory, processor 2 receives the memory access permission. These two state machines are implemented for each processor. In the lock mode, the output signals of the state machines are compared in order to detect the occurrence of any error.
- the data for updating cache 2 in the lock mode are delayed by 1.5 clock pulses in the IRAM control unit.
- bit 5 in register 0 of SysControl the identity of the core is encoded. In the case of core 1 the bit is 0 and in the case of core 2 it is high. This register is mirrored in the memory area having the address 65528.
- the program counter of processor 1 is delayed by 3.5 clock pulses to enable a comparison with the program counter of processor 2 in the lock mode.
- the caches of both processors may be reloaded separately. If a switchover into the lock mode is performed, the two caches are not coherent with respect to one another. This may cause the two processors to diverge and the comparators to thus signal an error.
- a flag table is constructed in the IRAM control, where it is noted whether a cache line has been written in the lock mode or in the split mode. When the cache is reloaded in the lock mode, the entry corresponding to the cache line is set at 0, and when it is reloaded in the split mode or when the cache line of a single cache is updated, it is set at 1.
- this cache line has been updated in the lock mode, i.e., whether it is identical in the two caches.
- the processor may always access the cache line, regardless of the status of the Flag Vector. This table must be present only once, since in the event of an error, the two processors diverge and thus this error is reliably detected by the comparators. Since the access times to the central table are relatively long, this table may also be copied to each cache.
- DramControl The parity is formed in this component for the address, data, and memory control signals of each processor.
- the split mode state is in turn subdivided into seven states which resolve the access conflicts and are able to lock the data memory for the other processor.
- the order of execution represents the priorities at the same time.
- the DDU has the switchover intent detector (IllOPDetect), the mode switch unit, and the Iram and Dram control.
- IllOPDetect switchover intent detector
- the mode switch unit As mentioned previously, the DDU has the switchover intent detector (IllOPDetect), the mode switch unit, and the Iram and Dram control.
- the core of the invention is the general mode of operation of the data distribution unit DDU (different data assignment and thus also operating mode selection, depending on the mode).
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Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410051964 DE102004051964A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Überwachung einer Speichereinheit in einem Mehrprozessorsystem |
DE200410051937 DE102004051937A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Synchronisierung in einem Mehrprozessorsystem |
DE102004051950.1 | 2004-10-25 | ||
DE102004051952.8 | 2004-10-25 | ||
DE102004051964.1 | 2004-10-25 | ||
DE102004051937.4 | 2004-10-25 | ||
DE200410051950 DE102004051950A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Taktumschaltung bei einem Mehrprozessorsystem |
DE102004051992.7 | 2004-10-25 | ||
DE200410051952 DE102004051952A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem |
DE200410051992 DE102004051992A1 (de) | 2004-10-25 | 2004-10-25 | Verfahren und Vorrichtung zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Mehrprozessorsystems |
PCT/EP2005/055532 WO2006045798A1 (de) | 2004-10-25 | 2005-10-25 | Verfahren und vorrichtung zur datenverteilung aus wenigstens einer datenquelle in einem mehrprozessorsystem |
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US20080163035A1 true US20080163035A1 (en) | 2008-07-03 |
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Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
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US11/666,405 Active 2027-04-27 US7853819B2 (en) | 2004-10-25 | 2005-10-25 | Method and device for clock changeover in a multi-processor system |
US11/666,406 Abandoned US20080163035A1 (en) | 2004-10-25 | 2005-10-25 | Method for Data Distribution and Data Distribution Unit in a Multiprocessor System |
US11/666,407 Abandoned US20080126718A1 (en) | 2004-10-25 | 2005-10-25 | Method And Device For Monitoring A Memory Unit In A Mutliprocessor System |
US11/666,413 Abandoned US20090164826A1 (en) | 2004-10-25 | 2005-10-25 | Method and device for synchronizing in a multiprocessor system |
Family Applications Before (1)
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US11/666,405 Active 2027-04-27 US7853819B2 (en) | 2004-10-25 | 2005-10-25 | Method and device for clock changeover in a multi-processor system |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/666,407 Abandoned US20080126718A1 (en) | 2004-10-25 | 2005-10-25 | Method And Device For Monitoring A Memory Unit In A Mutliprocessor System |
US11/666,413 Abandoned US20090164826A1 (en) | 2004-10-25 | 2005-10-25 | Method and device for synchronizing in a multiprocessor system |
Country Status (8)
Country | Link |
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US (4) | US7853819B2 (de) |
EP (5) | EP1812861A1 (de) |
JP (5) | JP2008518310A (de) |
KR (4) | KR20070067168A (de) |
AT (2) | ATE409327T1 (de) |
DE (2) | DE502005005490D1 (de) |
RU (1) | RU2007119316A (de) |
WO (5) | WO2006045798A1 (de) |
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US20090249271A1 (en) * | 2008-03-27 | 2009-10-01 | Hiromichi Yamada | Microcontroller, control system and design method of microcontroller |
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