US20060057760A1 - Image sensor and method for forming the same - Google Patents

Image sensor and method for forming the same Download PDF

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Publication number
US20060057760A1
US20060057760A1 US11/217,962 US21796205A US2006057760A1 US 20060057760 A1 US20060057760 A1 US 20060057760A1 US 21796205 A US21796205 A US 21796205A US 2006057760 A1 US2006057760 A1 US 2006057760A1
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pattern
gate electrode
conductive layer
diffusion region
impurity diffusion
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Duk-min Yi
Sung-Keun Won
Jun-Yeoul You
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of US20060057760A1 publication Critical patent/US20060057760A1/en
Priority to US12/692,133 priority Critical patent/US8067301B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687Wafer level processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689MOS based technologies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14609Pixel-elements with integrated switching, control, storage or amplification elements

Definitions

  • the present invention relates to an image sensor and a method for forming the same, more particularly to a complementary metal-oxide semiconductor (CMOS) image sensor and a method for forming the same.
  • CMOS complementary metal-oxide semiconductor
  • Main elements for determining image quality of the digital camera are an optical lens and an image sensor.
  • the image sensor converts light input through the optical lens into an electric signal having an excellent image quality.
  • the image sensor includes a pixel array composed of a plurality of pixels that are two-dimensionally arranged in a matrix form. Each pixel includes photo-detective, transfer, and readout devices. According to the types of the transfer and readout devices, the image sensor is classified as a charge coupled device (hereinafter referred to as CCD) or a CMOS image sensor (hereinafter referred to as CIS).
  • CCD charge coupled device
  • CIS CMOS image sensor
  • the CCD uses MOS capacitors for transfer and readout operations. Respective MOS capacitors are arranged adjacent to each other, a charge carrier due to an electric potential difference is stored in one capacitor and is transferred to an adjacent capacitor.
  • a CIS is provided with MOS (metal-oxide semiconductor) transistors of the same number as the pixels and employs a switching mode to detect outputs in an orderly manner by using the MOS transistors.
  • the CCD image sensor has lower noise and higher image quality than the CIS.
  • the CIS compared to the CCD image sensor, has a simple operational scheme and is capable of implementing various scanning types.
  • a single processing circuit for the CIS can be integrated into a single chip so that it is possible to miniaturize products.
  • use of compatible CMOS technique provides advantages of reducing manufacturing costs, owing to low and single power, random access with image data.
  • the CIS can be used in any device that displays images, e.g., digital cameras, surveillance cameras, smart phones, PDAs, notebook computers, bar code reader, HDTV resolution cameras, toys and so forth.
  • CMOS image sensor Currently, uses and applications of the CMOS image sensor have become progressively broader.
  • the CIS is proper to integrate unit pixels, peripheral analog elements, and MOS elements on a single chip thereof by applying a CMOS fabricating process thereto.
  • CMOS fabricating process thereto.
  • each gate electrode of MOS transistors formed at the peripheral circuit region becomes lower in height.
  • it is impossible to implant halo ions because an aspect ratio of a space defined between the gate electrodes becomes larger. Accordingly, it is preferred that gate electrode of MOS transistors of the pixel array region be shallowly formed like those of the MOS transistors of the peripheral circuit region in the CIS.
  • FIG. 1 is a cross-sectional view showing a pixel of a pixel array region that illustrates an impurity ion implantation for a photo diode in a manufacturing process of a CIS, relevant to the problem arising from the CIS when the gate electrode of a MOS transistor is low in height.
  • reference numeral 11 represents a P-type substrate
  • reference numeral 13 represents a gate insulation layer
  • reference numerals 15 a and 15 b represent gate electrodes.
  • Reference numeral 17 notes an ion implantation mask
  • reference numeral 19 notes an N-type impurity ion implantation for forming a photo diode
  • reference numeral 21 denotes an N-type impurity diffusion region of the photo diode.
  • the N-type impurity diffusion region of the photo diode is formed at a gate electrode 15 a in the vicinity thereof by a self-alignment method, as indicated by a dotted line.
  • the gate electrodes 15 a and 15 b are shallow, they have a high energy, for example, about 500 keV.
  • an N-type impurity diffusion region 21 is formed at a lower portion of the gate electrode 15 a .
  • the present invention is directed to a reliable image sensor and a method of forming the same.
  • the invention is directed to an image sensor comprising a photo-detective device and at least one transistor electrically connected to the photo-detective device for outputting charges stored in the photo-detective device.
  • the transistor connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern.
  • the ion-implantation interrupting pattern covers a part of the gate electrode pattern, and one side of the ion-implantation interrupting pattern in the vicinity of the photo-detective device is vertically aligned with one side of the gate electrode pattern in the vicinity of the photo-detective device.
  • the ion-implantation interrupting pattern includes a dielectric layer pattern and a conductive layer pattern that are sequentially stacked.
  • the sensor can further comprise a metal interconnection electrically connected to a gate electrode pattern region that is exposed to an outer side of the ion implantation interrupting pattern.
  • the photo-detective device is a photo diode comprising: a first impurity diffusion region formed at a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductivity type; and an impurity diffusion region of the first conductivity type formed in the first impurity diffusion region of the second conductivity type.
  • the transistor directly connected to the photo-detective device includes a second impurity diffusion region of the second conductivity type formed on the semiconductor substrate at another outer side of the gate electrode pattern opposite to the photo-detective device.
  • the photo-detective device is a photo diode comprising: a first impurity diffusion region formed at a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductive type; and an impurity diffusion region of the first conductivity type formed in the first impurity diffusion region of the second conductivity type.
  • the at least one transistor includes a transfer transistor, a reset transistor, a sensing transistor, and an access transistor that are serially connected to the photo-detective device.
  • Third impurity diffusion regions of the second conductivity type are disposed in the semiconductor substrate between gate electrode patterns of the respective transistors.
  • a gate electrode pattern of the sensing transistor is electrically connected to a third impurity diffusion region of the second conductivity type between the transfer and reset transistors.
  • the gate electrode pattern and the conductive layer pattern are made of the same material
  • the dielectric layer pattern has a structure in which oxide layer-nitride layer-oxide layer are sequentially stacked.
  • the senor further comprises a capacitor formed of the gate electrode pattern, the dielectric layer pattern, and the conductive layer pattern which are sequentially stacked over the semiconductor substrate.
  • the ion-implantation interrupting pattern is smaller than the gate electrode pattern and partially exposes the gate electrode pattern at a portion that is not adjacent to the photo-detective device.
  • the invention is directed to an image sensor comprising a photo diode and a transistor directly connected to the photo diode.
  • the photo diode has a first impurity diffusion region formed on a semiconductor substrate of a first conductivity type, the first impurity diffusion region being of a second conductivity type, and an impurity diffusion region of the first conductivity type in the first impurity diffusion region of the second conductivity type.
  • the transistor includes a stacked gate pattern in the vicinity of the first impurity diffusion region of the second conductivity type, and a second impurity diffusion region of the second conductivity type formed on the semiconductor substrate at an outer side of the gate electrode pattern opposite to the first impurity diffusion region of the second conductivity type.
  • the stacked gate pattern includes a gate electrode pattern, a dielectric layer pattern, and a conductive layer pattern that are sequentially formed on the semiconductor substrate, interposing a gate insulation layer therebetween.
  • the dielectric and conductive layer patterns cover a part of the gate electrode pattern, and one side of the conductive layer pattern in the vicinity of the photo diode is vertically aligned with one side of the gate electrode pattern in the vicinity of the photo diode.
  • the sensor further comprises a metal interconnection electrically connected to a gate electrode pattern region that is exposed to an outer side of the conductive layer pattern through a contact plug.
  • the senor further comprises a capacitor formed of the gate electrode pattern, the dielectric layer pattern, and the conductive layer pattern which are sequentially stacked on the semiconductor substrate.
  • the invention is directed to a transfer transistor for transferring a charge stored in a photo-detective device.
  • the transfer transistor comprises: a gate electrode pattern to which a bias voltage is applied; and a dielectric layer pattern and a conductive layer pattern stacked on the gate electrode pattern.
  • the dielectric layer pattern and the conductive layer pattern are smaller than the gate electrode pattern, and one side of the conductive layer pattern and one side of the gate electrode pattern in the vicinity of the photo diode are vertically aligned with each other.
  • the transfer transistor further comprises a metal interconnection electrically connected to a gate electrode pattern region that is exposed to an outer side of the conductive layer pattern through a contact plug, for applying a bias to the transfer transistor.
  • the invention is directed to an image sensor comprising: a photo-detective device formed at a pixel array region of a semiconductor substrate; a transfer transistor connected to the photo-detective device for transferring charges stored in the photo-detective device; and a capacitor formed at a peripheral circuit region of the semiconductor substrate.
  • a gate electrode of the transfer transistor and the capacitor each are formed of a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern.
  • the second conductive layer pattern of the gate electrode of the transfer transistor partially covers the first conductive layer pattern of the gate electrode of the transfer transistor, allowing one side of the first conductive layer pattern in the vicinity of the photo-detective device to be vertically aligned with one side of the second conductive layer pattern.
  • the image sensor further comprises a metal interconnection electrically connected to the first conductive layer pattern exposed by the second conductive layer pattern of the transfer transistor through a contact plug, for applying a bias to the transfer transistor.
  • the transfer transistor transfers the charges stored in the photo-detective device to a floating diffusion region of a semiconductor substrate located at an outer side of the transfer transistor opposite to the photo-detective device.
  • the image sensor further comprises: a reset transistor connected to the transfer transistor and resetting the floating diffusion region; a sensing transistor sensing the charges stored in the floating diffusion region; and an access transistor selecting an output of the sensing transistor.
  • gate electrodes of the reset transistor, the sensing transistor, and the access transistor are formed of the first conductive layer pattern of the transfer transistor.
  • the invention is directed to a method of forming an image sensor, comprising: (i) sequentially forming a gate oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer on a semiconductor substrate; (ii) patterning the second conductive layer and the dielectric layer to form an ion-implantation interrupting pattern having sides; (iii) patterning the first conductive layer to form a gate electrode pattern having sides and being larger than the ion-implantation interrupting pattern so that one side of the ion-implantation interrupting pattern and one side of the gate electrode pattern are vertically aligned with each other; (iv) forming a first impurity diffusion region at the semiconductor substrate in contact with one side of the ion-implantation interrupting pattern and the gate electrode pattern; (v) forming an impurity diffusion region of a first conductivity type in the first impurity diffusion region, the first impurity diffusion region being of a second conductivity type; and (vi) forming a second impurity diffusion region of
  • the method further comprises forming an interlayer insulation layer; and forming a metal interconnection electrically connected to an upper side of the gate electrode pattern exposed to another side of the ion-implantation interrupting pattern through the interlayer insulation layer.
  • step (ii) comprises: (ii-1) forming a passivation layer on the second conductive layer; (ii-2) forming a first etch mask pattern on the passivation layer; (ii-3) etching the passivation layer, the second conductive layer, and the dielectric layer formed at an outer side of the first etch mask pattern until the first conductive layer is exposed; and (ii-4) removing the first etch mask pattern.
  • step (iii) comprises: (iii-1) forming a second etch mask pattern to cover a part of an upper surface of the ion-implantation interrupting pattern and a part of the second conductive layer at another outer side of the ion implantation pattern; (iii-2) etching the second conductive layer exposed by using the second etch mask pattern and the passivation layer as etch masks; and (iii-3) removing the second etch mask pattern.
  • step (iv) comprises: (iv-1) forming a first ion implantation mask to cover at least the gate electrode pattern; (iv-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of one side of the gate electrode pattern using the first ion implantation mask; and (iv-3) removing the first ion implantation mask.
  • step (v) comprises: (v-1) forming a second ion implantation mask to expose the first impurity diffusion region of the second conductivity type; (v-2) implanting impurity ions of the first conductivity type into the first impurity diffusion region of the second conductivity type using the second ion implantation mask; (v-3) removing the second ion implantation mask.
  • step (vi) comprises: (vi-1) forming a third ion implantation mask to cover at least the first impurity diffusion region of the second conductivity type and the impurity diffusion region of the first conductivity type; (vi-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of another side of the gate electrode pattern using the third ion implantation mask; and (vi-3) removing the third ion implantation mask.
  • an upper electrode pattern and a dielectric pattern are formed spaced from the ion-implantation interrupting pattern by a predetermined distance when an ion-implantation interrupting pattern having sides is formed by patterning the second conductive layer and the dielectric layer, and a lower aligned electrode pattern is formed under the upper electrode pattern and the dielectric pattern when a gate electrode pattern having sides are formed by patterning the first conductive layer.
  • a plurality of gate electrode patterns are formed spaced from the gate electrode pattern and the lower electrode pattern by a predetermined distance when a gate electrode pattern is formed by patterning the first conductive layer, and a third impurity diffusion region of the second conductivity type are formed at the semiconductor substrate between the plurality of gate electrode patterns during the formation of the second impurity diffusion region of the second conductivity type.
  • the first impurity diffusion region of the second conductivity type is formed deeper than the second impurity diffusion region of the second conductivity type.
  • the invention is directed to a method for forming an image sensor, comprising: (a) sequentially forming a gate oxide layer, a first conductive layer, a dielectric layer, and a second conductive layer on a semiconductor substrate having defined pixel array and peripheral circuit regions; (b) patterning the second conductive layer and the dielectric layer to form a second conductive layer pattern having sides and an ion-implantation interrupting pattern formed by a dielectric layer pattern at the pixel array region, and to form an upper electrode pattern and a dielectric pattern on the peripheral circuit region; (c) patterning the first conductive layer to form a gate electrode pattern at the pixel array region and to form a lower electrode pattern larger than the second conductive layer pattern at the peripheral circuit region so that one side of the second conductive pattern and one side of the gate electrode pattern are vertically aligned with each other; (d) forming a first impurity diffusion region at the semiconductor substrate in contact with sides of the ion-implantation interrupting pattern and the gate electrode pattern; (e) forming
  • a plurality of first gate electrode patterns and a plurality of second gate electrode patterns are further formed at the pixel array region and the peripheral circuit region, respectively, when a gate electrode pattern having sides is formed at the pixel array region, and a lower electrode pattern is formed at the peripheral circuit region by patterning the first conductive layer.
  • the method further comprises forming an interlayer insulation layer; and forming a metal interconnection electrically connected to an upper surface of the gate electrode pattern exposed to another side of the ion-implantation interrupting pattern through the interlayer insulation layer.
  • step (b) comprises: (b-1) forming a passivation layer on the second conductive layer; (b-2) forming a first etch mask pattern on the passivation layer; (b-3) etching the passivation layer, the second conductive layer, and the dielectric layer formed at an outer side of the first etch mask pattern until the first conductive layer is exposed; and (b-4) removing the first etch mask pattern.
  • step (c) comprises: (c-1) forming a second etch mask which covers a part of the upper electrode pattern and a part of a first conductive layer formed at an outer side of the upper electrode pattern, covers a second conductive layer formed at another outer side of the ion-implantation interrupting pattern, and exposes a part of an upper surface of the ion-implantation interrupting pattern; and (c-2) etching a first conductive layer exposed using the second etch mask pattern, the ion-implantation interrupting pattern, and the passivation layer as etch masks.
  • step (d) comprises: (d-1) forming a first ion implantation mask to expose a semiconductor substrate in the vicinity of one side of the gate electrode pattern; (d-2) implanting impurity ions of the second conductive type into the semiconductor substrate in the vicinity of the one side of the gate electrode pattern by using the first ion implantation mask; and (d-3) removing the first ion implantation mask.
  • step (e) comprises: (e-1) forming a second ion implantation mask to expose the first impurity diffusion region of the second conductivity type; (e-2) implanting impurity ions of the first conductivity type into the first impurity diffusion region of the second conductivity type using the second ion implantation mask; and (e-3) removing the second ion implantation mask.
  • step (f) comprises: (f-1) forming a second ion implantation mask to cover the first impurity diffusion region of the second conductivity type and the impurity diffusion region of the first conductivity type; (f-2) implanting impurity ions of the second conductivity type into the semiconductor substrate in the vicinity of another side of the gate electrode pattern and a semiconductor substrate between the plurality of first and second gate electrode patterns by using the second ion implantation mask, the gate electrode pattern, and the plurality of first and second gate electrode patterns as ion implantation masks; and (f-3) removing the second ion implantation mask.
  • FIG. 1 is a cross-sectional view showing a pixel of a pixel array region that illustrates an impurity ion implantation for a photo diode in a manufacturing process of a CIS.
  • FIG. 2 is an equivalent circuit diagram of a CIS pixel structure having a photo-detective device and one transistor.
  • FIG. 3A is an equivalent circuit diagram of a CIS pixel structure having a photo-detective device and three transistors.
  • FIG. 3B is a schematic cross-sectional view showing a pixel in a CIS pixel structure having a photo-detective device and three transistors.
  • FIG. 4A is an equivalent circuit diagram of a CIS pixel structure having a photo-detective device and four transistors.
  • FIG. 4B is a schematic cross-sectional view of a pixel that illustrates an operation of the CIS pixel structure shown in FIG. 4A .
  • FIG. 5 is an equivalent circuit diagram of a pixel array region of a CIS having four transistors according to an embodiment of the present invention.
  • FIG. 6 is a plan view showing a single pixel of the pixel array region shown in FIG. 5 .
  • FIG. 7 is a schematic cross-sectional view of a semiconductor substrate in FIG. 6 taken along the line I-I.
  • FIGS. 8 through 16 are schematic cross-sectional views of the semiconductor substrate that illustrate a method for forming a CIS according to an embodiment of the present invention.
  • first”, “second” and “third” are used to describe various regions and layers, the regions and layers are not limited thereto by such terms. Further, the terms are used only to distinguish regions or layers from other regions or layers.
  • a layer material referred to as a first layer material in one embodiment can be referred to as a second layer material in another embodiment.
  • one side relevant to a stacked gate pattern, a gate electrode pattern, a conductive layer pattern, or an ion-implantation interrupting pattern indicates one side of a stacked gate pattern, a gate electrode pattern, a conductive layer pattern, or an ion implantation interrupting pattern, in the vicinity of a photo-detective 0 . 15 device, respectively.
  • the other side for the stacked gate pattern, the gate electrode pattern, the conductive layer pattern, or the ion-implantation interrupting pattern indicates the other side for the stacked gate pattern, the gate electrode pattern, the conductive layer pattern, or the ion implantation interrupting pattern, opposite to the photo-detective device.
  • the gate electrode pattern, the conductive layer pattern, or the ion-implantation interrupting pattern has two sides, one side is in the vicinity of the photo-detective device and the other side is opposite to the photo-detective device.
  • the present invention relates to an image sensor such a CCD image sensor and a CIS, more particularly to a CIS and a method for forming the same.
  • the method for forming the CIS according to the present invention is applicable to a single chip CIS in that an analog element and a MOS element such as a unit pixel and peripheral circuit regions are simultaneously formed at one chip.
  • a CIS pixel structure includes a photo-detective device and transistors for transferring and outputting a charge stored in the photo-detective device. According to the number of transistors used, the CIS pixel structure may have various forms. For example, the CIS pixel may include one, two, three, four, or five transistors.
  • FIG. 2 is an equivalent circuit diagram of a CIS pixel structure (hereinafter, referred to as single-transistor CIS pixel structure) having a photo-detective device and one transistor. Since one pixel is composed of a photo-detective device 21 and one transfer transistor 23 , the single-transistor CIS pixel structure of the same pixel size has a light receiving section area greater than that of a pixel structure having 2 to 4 transistors.
  • the single-transistor CIS pixel structure can obtain a fill factor of 70 through 80%. However, when a signal is output, a significantly great noise occurs. Further, since a sense amplifier for signal amplification and a capacitor for signal storage are located at an end of a bus line, they are influenced by a parasitic capacitance, causing the occurrence of a great fixed pattern noise.
  • EHP Electron-Hole Pair
  • FIG. 3A is an equivalent circuit of a CIS pixel structure (hereinafter referred to as three transistor CIS pixel structure) having a photo-detective device and three transistors
  • FIG. 3B is a cross-sectional view showing a pixel in a CIS pixel structure having a photo-detective device and three transistors.
  • the three transistor CIS pixel structure is proposed. According to the three transistor CIS pixel structure, a source follower is inserted into a pixel. It is called a photo diode type APS (Active Pixel Sensor).
  • the three transistor CIS pixel structure Since one pixel is composed of one photo-detective device 31 and three transistors including a reset transistor 33 , a sensing transistor 35 , and an access transistor 37 , the three transistor CIS pixel structure has a fill factor lower than that of the single-transistor CIS pixel structure. Furthermore, a probability of noise occurring becomes high due to non-uniformity of a threshold voltage between pixels of the source follower that is inserted into the pixel for removing noise due to the parasitic capacitance.
  • Operation of the three transistor CIS pixel structure is as follows.
  • a reset transistor 33 turns on, a source electrode of the reset transistor 33 has a voltage of V DD .
  • an initialization is achieved, and at this time, a reference value is detected.
  • a photo diode 31 functioning as a photo-sensing means
  • An electric potential of a source electrode of the reset transistor 33 or a gate bias of the sensing transistor 35 changes in proportion to an amount of the produced signal charge EHP.
  • the change in the gate bias of the sensing transistor 35 results in a change of an electric potential of a source electrode of the sensing transistor 35 or a drain electrode of an access transistor 37 .
  • the access transistor 37 is turned on, and data are output to a column side.
  • an electric potential of the source electrode of the reset transistor 33 becomes V DD . Such a process is repeatedly performed.
  • FIG. 4A is an equivalent circuit diagram of a CIS pixel structure (hereinafter referred to as four transistor CIS pixel structure) having a photo-detective device and four transistors.
  • FIG. 4B is a cross-sectional view of a pixel that illustrates an operation of the CIS pixel structure shown in FIG. 4A .
  • the four transistor CIS pixel structure has a structure similar to that of an output terminal of a CCD.
  • the four transistor CIS pixel structure includes one photo-detective device 41 and four transistors including a transfer transistor 43 , a reset transistor 45 , a sensing transistor 47 , and an access transistor 49 . Since the four transistor CIS pixel structure uses a floating diffusion node as an output terminal as in the case of the CCD, a probability of image lagging occurring is high. A probability of noise occurring is high due to non-uniformity of threshold voltages of transistors existing in the pixel as in the case of the three transistor CIS pixel structure. Moreover, since the four transistor CIS pixel structure has more transistors per pixel than other structures, the structure has a disadvantage in that a fill factor is low.
  • MOS transistors are connected to a photo diode functioning as a photo-sensing means.
  • Each gate electrode of the MOS transistors has a structure similar to that of a capacitor of a peripheral circuit region. This assures formation of an impurity diffusion region of the photo diode at a gate electrode of the MOS transistor by a self-alignment method.
  • the transfer transistor 23 in the single-transistor CIS pixel structure, the reset transistor 33 in the three transistor CIS pixel structure, the transfer transistor 43 in the four transistor CIS pixel structure each has a gate electrode similar to that of a capacitor of the peripheral circuit region.
  • a transistor outputting a signal charge stored in a photo diode has a gate electrode similar to that of a capacitor of the peripheral circuit region.
  • FIG. 5 is an equivalent circuit diagram of a pixel array region of a CIS having four transistors according to an embodiment of the present invention.
  • a pixel array area 50 includes a plurality of pixels P 11 , P 12 , . . . , Pm 1 , . . . , and Pmn two-dimensionally arranged in columns and rows.
  • Each of the pixels includes a photo-detective device PD.
  • a photo diode is used as the photo-detective device.
  • the photo diode includes an N-type impurity region and a P-type impurity region. When incident light is irradiated to the photo diode, holes and electrons EHP are produced in the N-type impurity region and the P-type impurity region of the photo diode, respectively.
  • Each pixel may include a transfer transistor T TF , a reset transistor T R , a sensing transistor T S , and an access transistor T A in addition to the photo-detective device PD.
  • a first node N 1 between the sensing transistor T S and the reset transistor T R is connected to a gate electrode of the sensing transistor T S .
  • a second node between the reset transistor T R and the sensing transistor T S is connected to a power Supply V DD .
  • the photo-detective device PD is a photo diode having an N-type impurity region and a P-type impurity region, it is preferred that all of a transfer transistor, a reset transistor, a sensing transistor, and an access transistor are NMOS transistors. In this case, the N-type impurity region of the photo diode is formed in the gate electrode of the transfer transistor by a self-alignment method.
  • N pixels P 11 , P 12 , . . . , P 1 n arranged in a first row are connected to a first reset line RL 1 , a first transfer line TL 1 , and a first word line WL 1 parallel to the first row.
  • Gate electrodes of transfer transistors T TF in the first row are connected to the first transfer line TL 1
  • gate electrodes of reset transistors T R in the first row are connected to the first reset line RL 1 .
  • N pixels P 21 , P 22 , . . . , P 2 n arranged in a second row are connected to a second reset line RL 2 , a second transfer line TL 2 , and a second word line WL 2 parallel to the second row.
  • N pixels Pm 1 , Pm 2 , . . . Pmn arranged in an m-th row are connected to an m-th reset line RLm, an m-th line TLm, and an m-th word line WLm parallel to the an m-th row.
  • m pixels P 11 , P 21 , . . . , Pm 1 arranged in a first column are connected to a first pull-down transistor T PD1 ).
  • Source regions of access transistors T A arranged in the first column are connected to a drain region of the first pull down transistor T PD1 .
  • source regions of access transistors T A arranged in the second column are connected to a drain region of a second pull down transistor T PD2
  • source regions of access transistors T A arranged in an n-th column are connected to a drain region of an n-th pull down transistor T PDn .
  • Source regions and gate regions of the pull down transistors T PD1 , T PD2 . . . , T PDn are connected to a ground terminal and a selection line SL, respectively.
  • a voltage corresponding to a high-logic value is applied to a plurality of reset lines RL 1 , RL 2 , . . . , RLm to turn on all the reset transistors T R .
  • all charge remaining in the first node N 1 is removed and all the pixels are initialized.
  • all the reset transistors T R are turned off and an incident light is irradiated to the initialized pixels, charges are produced in the photo-detective devices PD by the incident light.
  • each of the photo-detective devices PD is a photo diode and each of the transfer transistors T TF , the reset transistors T R , the sensing transistors T S , and the access transistors T A is an NMOS transistor serially connected to an N-type impurity region of the photo diode, electrons are produced in the N-type impurity regions of the photo diodes.
  • a voltage corresponding to a high-logic value is applied to a first transfer line TL 1 , a first word line WL 1 , and a selection line SL. Accordingly, in addition to the transfer transistors T TF and the access transistors T A , n pull down transistors T PD1 , T PD2 , . . . , T PDn are turned on. Consequently, electrons in the N-type impurity region of photo diodes in the first row are transferred to first nodes N 1 adjacent thereto.
  • Drivabilities of the sensing transistors Ts are determined according to amount of electrons transferred to the first node N 1 .
  • first through n-th currents 11 , 12 , . . . , In flowing through sensing transistors T S in the first row are provided to a ground terminal through first through n-th pull down transistors T PD1 , T PD2 , . . . , T PDn .
  • V On are induced in drain regions of the pull down transistors T PD1 , T PD2 , . . . , T PDn , respectively.
  • the first through n-th output voltages V O1 , V O2 , . . . , V On correspond to data of first through n-th pixels P 11 , P 12 , . . . , P 1 n.
  • Data of all the pixels in a pixel array area 50 are output in the above-described method.
  • FIG. 6 is a plan view showing a single pixel of the pixel array region shown in FIG. 5
  • FIG. 7 is a cross-sectional view of a semiconductor substrate in FIG. 6 taken along the line I-I.
  • a device isolation layer 3 is disposed to define first and second active regions 3 a and 3 b in respective pixel regions.
  • the second active region 3 b is formed to extend from the first active region 3 a .
  • a shape of an active region shown in FIG. 6 or FIG. 7 is only an example. It is not limited to thereto.
  • a photo-detective device PD such as a photo diode is formed at the first active region 3 a .
  • a second conductive impurity diffusion region 7 for example, an N-type well region, is formed at the first active region 3 a .
  • An impurity diffusion region of a first conductive type 7 for example, a P-well region, is formed at the first active region 3 a .
  • At least one switching element is arranged at the second active region 3 b .
  • the at least one switching element includes a transfer transistor T TF , a reset transistor T R , a sensing transistor T S , and an access transistor T A (see FIG. 5 ) that are formed at the second active region 3 b.
  • the transfer transistor T TF includes a stacked gate electrode GSP that intersects an upper portion of the second active region 3 b and is arranged neighboring the first active region 3 a .
  • the access transistor T A also includes an access gate electrode AG that intersects an upper portion of the second active region 3 b .
  • the reset transistor T R includes a reset gate electrode RG that intersects an upper portion of the second active region 3 b between the stacked gate electrode GSP and the access gate electrode AG.
  • the sensing transistor T S includes a sensing gate electrode SG that intersects an upper portion of the second active region 3 b between the reset gate electrode RG and the access gate electrode AG.
  • Gate electrodes of the reset transistor, the sensing transistor, and the access transistor according to the present invention have the same construction and are made of the same material.
  • the stacked gate electrode GSP of the transfer transistor is different from each gate electrode of the other transistors and is thicker.
  • the stacked gate electrode GSP of the transfer transistor has the same thickness as that of each gate electrode of the other transistors.
  • the stacked gate electrode GSP of the transfer transistor is composed of a transfer gate electrode TG to which a bias voltage is applied and an ion-implantation interrupting pattern BP stacked on the transfer gate electrode TG.
  • the ion-implantation interrupting pattern BP is composed of a dielectric layer pattern DP and an upper electrode pattern TEP.
  • the ion-implantation interrupting pattern BP is smaller than a pattern of the transfer electrode pattern TG. That is, a part of the transfer gate electrode TG is exposed by the ion-implantation interrupting pattern BP and the exposed part of the transfer gate electrode TG is electrically connected to a metal interconnection. Preferably, the exposed part of the transfer gate electrode TG is located opposite to the photo-detective device PD.
  • One side of the transfer gate electrode TG and one side of the ion-implantation interrupting pattern BP are vertically aligned with each other. The other side of the transfer gate electrode TG and the other side of the ion-implantation interrupting pattern BP form a stepped portion.
  • An N-type well region of a photo diode functions as a source region of the transfer transistor.
  • a second active region 3 b between gate electrodes TG, RG, SG, and AG is doped by an N-type impurity.
  • the first conductivity type and the second conductivity type may be an N-type and a P-type, respectively.
  • a photo diode is composed of a P-well region formed at the first active region 3 a and an N-type well impurity region formed on a surface of the P-well region. Consequently, the transfer transistor, the reset transistor, the sensing transistor, and the access transistor correspond to PMOS transistors.
  • first conductivity type and the second conductivity type are an N-type and a P-type, respectively. It will be understood that the reverse of that configuration is within the scope of the invention.
  • a floating diffusion region FD (N 1 of FIG. 5 ) corresponds to the second active region 3 b between the transfer gate electrode TG and the reset gate electrode RG.
  • a reset diffusion region RD (N 2 of FIG. 5 ) corresponds to the second active region 3 b between the reset gate electrode RG and the sensing gate electrode SG, and is connected to a power supply V DD .
  • the semiconductor substrate 1 on which transistors are formed is covered by an interlayer insulation layer 9 .
  • the floating diffusion region FD and the sensing gate electrode SG are exposed by a contact hole CT that penetrates the interlayer insulation layer 9 .
  • a local wiring L 1 is disposed on the interlayer insulation layer 9 .
  • the local wiring L 1 electrically connects the sensing gate electrode SG to the floating diffusion region FD through the contact hole CT.
  • metal interconnections are not shown in the drawings, the metal interconnections are connected to gate electrodes TG, RG, and AG to apply a suitable bias voltage.
  • FIGS. 8 through 16 are cross-sectional views that illustrate a method for forming an image sensor according to an embodiment of the present invention.
  • the description will be given with respect to the case where a CIS in which a p-type semiconductor substrate is used and each pixel includes four transistors and a photo diode as a photo-detective means. It is not limited thereto. It will be apparent to those skilled in the art that the above-mentioned CIS of various structures and a CCD are applicable to the present invention without departing from the scope and spirit of the invention.
  • numeral reference “a” represents a pixel array region
  • numeral reference “b” represents a peripheral circuit region. Active and passive elements such as a MOS transistor, a resistor, a capacitor are formed at the peripheral circuit region. So as to simplify the drawings, only MOS transistors and capacitors are shown.
  • a P-type semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is prepared by doping a P-type impurity into a single crystalline silicon ingot after cutting it formed by a Czochralski method.
  • a device isolation process for the semiconductor substrate 101 is performed to form a device isolation layer 102 defining an active region. Shallow trench isolation is used as the device isolation process. Subsequently, a gate oxide layer 103 , a first conductive layer 105 , a dielectric layer 107 , and a second conductive layer 109 are sequentially formed.
  • the gate oxide layer 103 is formed, for example, by a thermal oxidation.
  • the first conductive layer 105 is used as a gate electrode of a transistor that defines each pixel in the pixel array region “a”.
  • the first conductive layer 105 of the peripheral circuit region “b” is used as a gate electrode of a transistor or a lower electrode of a capacitor.
  • the first conductive layer 105 is formed by 15 , polysilicon.
  • the dielectric layer 107 is used as a dielectric layer of a capacitor that is formed at the peripheral circuit region “b”.
  • the dielectric layer 107 is formed by a layer having a high dielectric constant, for example, such as multiple layers formed by sequentially stacking oxide layer-nitride layer-oxide layer.
  • the second conductive layer 109 is used as an upper electrode of a capacitor that is formed at the peripheral circuit region “b”.
  • the second conductive layer 109 is also used as a transistor in the vicinity of a photo-detective device in the pixel array region “a”. That is, in this embodiment, the second conductive layer 109 remains on a transfer gate electrode of a transfer transistor and functions as an ion-implantation interrupting pattern.
  • the second conductive layer 109 is comprised of polysilicon.
  • a passivation layer 108 is formed on the second conductive layer 109 .
  • the passivation layer 108 prevents the second conductive layer 109 from being etched in a next process of patterning the first conductive layer 105 .
  • the passivation layer 108 is formed by a material having an etching selectivity ratio for the first conductive layer 105 , such as silicon nitride or tungsten.
  • first etch mask patterns 111 a and 111 b are formed on the passivation layer 108 .
  • the first etch mask pattern 111 a on the pixel array region “a” functions as the ion-implantation interrupting pattern
  • the first etch mask pattern 111 b on the peripheral circuit region “b” functions as the upper electrode of the capacitor.
  • the first etch mask patterns 111 a and 111 b can be formed by a known photolithography process.
  • the passivation layer, the second conductive layer, and the dielectric layer exposed by the first etch mask patterns 111 a and 111 b are removed until the first conductive layer 105 is exposed, causing the formation of the ion-implantation interrupting pattern 110 composed a dielectric layer pattern 107 a and a second conductive layer pattern 109 at the pixel array region “a,”, and an upper electrode pattern 109 b and a dielectric layer pattern 107 b at the peripheral circuit region “b”.
  • An upper portion of the ion-implantation interrupting pattern 110 is covered by a passivation layer pattern 108 a .
  • the ion-implantation interrupting pattern 110 includes two sides 110 L and 110 R. One side 110 L of the ion-implantation interrupting pattern 110 is formed in the vicinity of the photo-detective device PD, the other side 110 R thereof is formed opposite to the photo-detective device PD.
  • second etch mask patterns 113 a , 113 a ′, 113 b , and 113 b ′ are formed.
  • the second etch mask patterns 113 a , 113 a ′, and 113 b ′ define a gate electrode of a transistor.
  • the second etch mask pattern 113 b defines a lower electrode of a capacitor.
  • the second etch mask pattern 113 a defines a transfer gate of a transfer transistor, and covers a part of the ion-implantation interrupting pattern 110 .
  • the second etch mask pattern 113 a exposes the one side 110 L of the ion-implantation interrupting pattern 110 , and covers a part of the first conductive layer outside the other side 110 R of the ion-implantation interrupting pattern 110 .
  • the second etch mask patterns 113 a ′ and 113 b ′ define a gate electrode of a reset transistor and a gate electrode of a transistor in a peripheral circuit region, respectively.
  • the second etch mask pattern 113 b defines a lower electrode of a capacitor, and covers an upper electrode pattern and a part of the first conductive layer outside the upper electrode pattern.
  • the second etch mask patterns 113 a , 113 a ′, 113 b , and 113 b ′ are formed by the same manner as the case in the first etch mask patterns.
  • a first conductive exposed layer is etched by using the second etch mask patterns 113 a , 113 a ′, 113 b , and 113 b ′ and the passivation layer pattern 108 a as an etch mask to form gate electrodes 105 a , 105 a ′ and 105 b ′, and a lower electrode pattern 105 b .
  • a transfer transistor in the pixel array region “a” includes a stacked gate electrode 115 a on which a transfer gate 105 a and the ion-implantation interrupting pattern 110 are stacked.
  • a capacitor 115 b is composed of a lower electrode pattern 105 b , a dielectric layer pattern 107 b , and an upper electrode pattern 109 b of the peripheral circuit region “b”.
  • One side 105 L of the transfer gate electrode 105 a is vertically aligned with one side 110 L of the ion-implantation interrupting pattern 110 , whereas the other side 105 R of the transfer gate electrode 105 a is not vertically aligned with the other side 110 R of the ion-implantation interrupting pattern 110 .
  • a size of the ion-implantation interrupting pattern 110 is smaller than that of the transfer gate electrode 105 a .
  • the ion-implantation interrupting pattern 110 covers a part of the transfer gate electrode 105 and exposes another part 105 as thereof.
  • a metal interconnection is electrically connected to the exposed part 105 as of the transfer transistor to apply a bias voltage thereto.
  • a first ion implantation mask 117 is formed to expose a region 3 a (see FIGS. 6 and 7 ) on which a photo-detective device in the pixel array region “a” will be formed.
  • the first ion implantation mask 117 may be formed by a known photolithography process.
  • the first ion implantation mask 117 covers other parts of the semiconductor substrate other than the region 3 a on which a photo-detective device in the pixel array region “a” will be formed.
  • the first ion implantation mask pattern 117 can be formed to expose a part of the ion-implantation interrupting pattern 110 due to the ion-implantation interrupting pattern 110 .
  • An extent to which the first ion implantation mask pattern 117 exposes the ion-implantation interrupting pattern 110 can be varied according to processes. This means that a misalignment margin of a photolithography process for the formation of the first ion implantation mask pattern 117 is great.
  • an ion implantation mask should not expose the transfer transistor.
  • the ion implantation mask exposes the transfer transistor, it should expose the transfer transistor by the same extent in every process.
  • an N-type well region 121 is formed at the semiconductor substrate 101 in the pixel array region “a” by performing a thermal oxidation.
  • the N-type well region 121 is formed at the one side 105 L of the transfer gate electrode 105 a in the transfer transistor by a self-alignment method.
  • a P-type impurity diffusion region 127 is formed in the N-type well region 121 by performing a heat treatment. Accordingly, a photo diode 129 is formed, and the second ion implantation mask pattern 123 is formed to expose the N-type well region 121 .
  • N-type impurity diffusion regions 135 S/D at a semiconductor substrate between gate electrodes are formed by a heat treatment.
  • Each of the N-type impurity diffusion regions 135 S/D is formed shallower than the N-type well region.
  • the spacer 130 is formed by a material having an etching selectivity ratio for an interlayer insulation layer 137 (see FIG. 16 ) to be formed by a following process, such as silicon nitride layer.
  • the N-type impurity diffusion regions 135 S/D between the transfer gate electrode 105 a and the reset gate electrode 105 b function as a floating diffusion region. Signal charges formed in the photo diode 129 are temporarily stored in the N-type impurity diffusion regions 135 S/D.
  • an interlayer insulation layer 137 is formed.
  • the interlayer insulation layer is composed of an insulation oxide layer.
  • a conductive layer is formed and patterned to form metal interconnections for applying a suitable bias voltage to all the gate electrodes and the source/drain regions. The metal interconnections are not shown in drawings.
  • a metal interconnection 139 for connecting a floating diffusion region FD between a transfer gate electrode and a reset gate electrode to a gate electrode of a sensing transistor is formed.
  • a transfer line ( 141 , TL of FIG. 5 ) is formed to be electrically connected to an exposed region 105 a of the transfer gate electrode.
  • a reset line (RL of FIG. 5 ) is formed to be electrically connected to a gate electrode of the reset transistor.
  • a word line (WL of FIG. 5 ) is formed to be electrically connected to a gate electrode of an access transistor.
  • a contact hole is formed to simultaneously penetrate the ion-implantation interrupting pattern as well as an interlayer insulation layer. After the contact hole is formed, a sidewall spacer can be formed at an inner wall of the contact hole as needed.
  • a reset transistor, a sensing transistor, and an access transistor can be formed to have the same structure as that of the transfer transistor.
  • a contact hole is formed to simultaneously penetrate an ion-implantation interrupting pattern as well as an interlayer insulation layer.
  • a gate electrode of the reset transistor 33 is indicative of a stacked gate pattern composed of a gate electrode and an ion-implantation interrupting pattern.
  • a gate electrode of a transistor for outputting a charge stored in a photo-detective device to a floating diffusion region indicates a stacked gate pattern.
  • an ion-implantation interrupting pattern is disposed on a gate electrode of a transfer transistor in the vicinity of a photo diode, a well region of the photo diode is formed at one side of a transfer gate electrode by a self-alignment method. Therefore, the present invention can stably form a threshold voltage of the transfer transistor.

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